Commits · 2b1975c3f63f015a30d4b7ef48f9da0358d250a5 · Elphel / x393

20 Oct, 2015 1 commit
- implemented optional skipping/fast forward of the data blocks when buffer is... · 2b1975c3
  Andrey Filippov authored 9 years ago
```
implemented optional skipping/fast forward of the data blocks when buffer is over/underrun during memory access
```
  2b1975c3
12 Sep, 2015 1 commit
- Fixed some errors in old memory controller modules · ccbfbf84
  Andrey Filippov authored 9 years ago
  
  ccbfbf84
23 Aug, 2015 2 commits
- continue multichannel simulation · 24011430
  Andrey Filippov authored 9 years ago
  
  24011430
- simulating multiple simultanerous sesnor/compressor channels · 225fccd0
  Andrey Filippov authored 9 years ago
  
  225fccd0
19 Aug, 2015 1 commit

Finished simulation/testing of a single-channel... · a500d197

Andrey Filippov authored 9 years ago

Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation

a500d197

15 Aug, 2015 1 commit
- continiuing co-simulation with 353 code, verified martching data to the compressor input · de641880
  Andrey Filippov authored 9 years ago
  
  de641880
05 Aug, 2015 1 commit
- continue with test fixture · 9afdf9d6
  Andrey Filippov authored 9 years ago
  
  9afdf9d6
01 Aug, 2015 1 commit
- making previous simulation tasks run on the full x393 code · 3af47156
  Andrey Filippov authored 9 years ago
  
  3af47156
28 Jul, 2015 1 commit
- CVC workarounds · 13382f62
  Alexey Grebenkin authored 9 years ago
  
  13382f62
25 Jul, 2015 1 commit
- CVC defines set, part1 · 26a449b6
  Alexey Grebenkin authored 9 years ago
  
  26a449b6
24 Jul, 2015 1 commit
- adjusting constraint attributes in the source · 64ff56ce
  Andrey Filippov authored 9 years ago
  
  64ff56ce
23 Jul, 2015 3 commits
- added ifndef wrappers for attributes · e19ac0d8
  Alexey Grebenkin authored 9 years ago
  
  e19ac0d8
- bug found with cvc · 64408d46
  Alexey Grebenkin authored 9 years ago
  
  64408d46
- made tools run successfully, no timing errors · 8b0a0f11
  Andrey Filippov authored 9 years ago
  
  8b0a0f11
22 Jul, 2015 1 commit
- More editing, trying to run Xilinx tools · 0cfebd24
  Andrey Filippov authored 9 years ago
  
  0cfebd24
21 Jul, 2015 2 commits
- removed most async resets · 210ed954
  Andrey Filippov authored 9 years ago
  
  210ed954
- continue playing · b721ae66
  Andrey Filippov authored 9 years ago
  
  b721ae66
20 Jul, 2015 1 commit
- fixed a bug caused by a counter-intuitive CLKINSEL in MMCME2_ADV · f026775f
  Andrey Filippov authored 9 years ago
  
  f026775f
19 Jul, 2015 1 commit
- working on synthesis errors · 48b08174
  Andrey Filippov authored 9 years ago
  
  48b08174
18 Jul, 2015 1 commit
- Trying synthesis, fixing revealed bugs · bf7c096d
  Andrey Filippov authored 9 years ago
  
  bf7c096d
16 Jul, 2015 2 commits
- done connecting sensor and compressor subsystems to the memory controller · 726a0234
  Andrey Filippov authored 9 years ago
  
  726a0234
- connecting sensor and compressor signals to the memory controller · 299231f6
  Andrey Filippov authored 9 years ago
  
  299231f6
15 Jul, 2015 1 commit
- Working a top-level compressor module · bdfcabf1
  Andrey Filippov authored 9 years ago
  
  bdfcabf1
14 Jul, 2015 1 commit
- connecting sensor subsystem to the top module · 6f36f6d1
  Andrey Filippov authored 9 years ago
  
  6f36f6d1
13 Jul, 2015 1 commit
- creating a top module for all four sensor channels · 3023d860
  Andrey Filippov authored 9 years ago
  
  3023d860
12 Jul, 2015 2 commits
- Increase command adderss space, modified address map to fit sesnor/compressor related registers · cadd05c1
  Andrey Filippov authored 9 years ago
  
  cadd05c1
- Changed 'author' to full name · 41babf8a
  Andrey Filippov authored 9 years ago
  
  41babf8a
06 Jul, 2015 1 commit
- Fixed teplate error in the headers · 93e8aa42
  Andrey Filippov authored 9 years ago
  
  93e8aa42
05 Jul, 2015 1 commit
- typo fix in multiple files · f92c85e2
  Andrey Filippov authored 9 years ago
  
  f92c85e2
24 Jun, 2015 1 commit
- porting jpeg/jp4 compressor · db90602d
  Andrey Filippov authored 9 years ago
  
  db90602d
29 May, 2015 1 commit
- typo fix · cad9a46e
  Andrey Filippov authored 9 years ago
  
  cad9a46e
19 May, 2015 1 commit
- working on sensor channel · 6021159e
  Andrey Filippov authored 9 years ago
  
  6021159e
15 May, 2015 1 commit
- working on files realted to sensor channels, added frame sequences to... · 6b2c4c47
  Andrey Filippov authored 9 years ago
```
working on files realted to sensor channels, added frame sequences to mcntrl_linear_rw.v and mcntrl_tiled_rw.v
```
  6b2c4c47
06 May, 2015 1 commit
- Debugging hardware, added functionality to detect cache-related problems · cdf97c98
  Andrey Filippov authored 9 years ago
  
  cdf97c98
29 Apr, 2015 1 commit
- connecting new modules for membridge to top module and test fixture · 890bad1c
  Andrey Filippov authored 9 years ago
  
  890bad1c
28 Apr, 2015 1 commit
- Working on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp · 7a0fa46b
  Andrey Filippov authored 9 years ago
  
  7a0fa46b
27 Apr, 2015 1 commit
- converted channel buffers to configurable width · e79823db
  Andrey Filippov authored 9 years ago
  
  e79823db
22 Apr, 2015 2 commits
- bug fixes in Verilog code · 286a6494
  Andrey Filippov authored 9 years ago
  
  286a6494
- Modified write module to support variable 'sel' input, adjustedg hardware to simulation timing · c8b52324
  Andrey Filippov authored 9 years ago
  
  c8b52324
21 Apr, 2015 1 commit
- minor adjustments · 1d2f08b7
  Andrey Filippov authored 9 years ago
  
  1d2f08b7