Skip to content

X
x393
Commit c8b52324 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

Modified write module to support variable 'sel' input, adjustedg hardware to simulation timing

parent 1d2f08b7
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 316 additions and 118 deletions
memctrl/cmd_encod_linear_wr.v
View file @ c8b52324
......@@ -26,7 +26,8 @@ module cmd_encod_linear_wr #(
parameter COLADDR_NUMBER= 10,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter WSEL= 1'b0
) (
input rst,
input clk,
......@@ -185,13 +186,14 @@ module cmd_encod_linear_wr #(
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);// | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);
4'h2: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT); // single cycle
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT); // single cycle
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT); // single cycle
// 4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT); // single cycle
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_ODT); // single cycle
// next may loop
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h6: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT);
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (WSEL << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h6: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (WSEL << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (WSEL << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
......
memctrl/cmd_encod_tiled_32_wr.v
View file @ c8b52324
......@@ -47,8 +47,8 @@ module cmd_encod_tiled_32_wr #(
parameter COLADDR_NUMBER= 10,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter WSEL= 1'b0
) (
input rst,
input clk,
......@@ -235,20 +235,21 @@ module cmd_encod_tiled_32_wr #(
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
// 4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// loop
4'h6: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h7: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h6: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h7: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// end loop
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hc: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hc: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_PGNEXT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'he: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT);
4'hf: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
......
memctrl/cmd_encod_tiled_wr.v
View file @ c8b52324
......@@ -49,8 +49,8 @@ module cmd_encod_tiled_wr #(
parameter COLADDR_NUMBER= 10,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter WSEL= 1'b0
) (
input rst,
input clk,
......@@ -235,17 +235,18 @@ module cmd_encod_tiled_wr #(
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT);
4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
// 4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN);
4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// start loop
4'h6: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h7: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h6: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h7: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// end loop
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h9: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h9: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
......
memctrl/phy/phy_cmd.v
View file @ c8b52324
......@@ -371,8 +371,8 @@ module phy_cmd#(
wire [7:0] dqs_data;
// assign dqs_data=phy_dqs_toggle_cur?dqs_pattern[7:0]:8'h0;
assign dqs_data=phy_dqs_toggle_cur?dqs_pattern[7:0]:8'hff;
assign dqs_data=phy_dqs_toggle_cur?dqs_pattern[7:0]:8'h0; // Has to be low to satisfy write levelling preamble
phy_top #(
.IOSTANDARD_DQ ("SSTL15_T_DCI"),
.IOSTANDARD_DQS ("DIFF_SSTL15_T_DCI"),
......
wrap/ddr3_wrap.v
View file @ c8b52324
This diff is collapsed.
x393_testbench01.sav
View file @ c8b52324
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Tue Apr 21 03:43:52 2015
[*] Wed Apr 22 06:13:24 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150420194727213.lxt"
[dumpfile_mtime] "Tue Apr 21 01:52:16 2015"
[dumpfile_size] 252456387
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150422000228091.lxt"
[dumpfile_mtime] "Wed Apr 22 06:07:54 2015"
[dumpfile_size] 272771001
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 41533420
[size] 1823 1173
[pos] 2065 0
*-13.595797 41566328 157271875 157546875 43667500 43655000 44285000 44297500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 42303990
[size] 1823 1180
[pos] 2071 0
*-12.659416 42321294 42321138 42326138 42321258 42321294 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.ddr3_i.
[treeopen] x393_testbench01.x393_i.
......@@ -40,17 +40,22 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_in_dly_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.iserdes_mem_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.iserdes_mem_i.iserdes_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dq_block[0].
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 347
[signals_width] 369
[sst_width] 373
[signals_width] 336
[sst_expanded] 1
[sst_vpaned_height] 635
[sst_vpaned_height] 636
@c00200
-top_simulation
@28
......@@ -1011,8 +1016,6 @@ x393_testbench01.x393_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_tri[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_tri[7:0]
@28
x393_testbench01.ddr3_i.en_dq[1:0]
x393_testbench01.ddr3_i.en_dqs[1:0]
x393_testbench01.ddr3_i.SDCLK_D[0]
@22
x393_testbench01.ddr3_i.SDA_D[14:0]
......@@ -1021,23 +1024,56 @@ x393_testbench01.ddr3_i.SDBA_D[2:0]
x393_testbench01.ddr3_i.SDRAS_D[0]
x393_testbench01.ddr3_i.SDCAS_D[0]
x393_testbench01.ddr3_i.SDWE_D[0]
x393_testbench01.ddr3_i.DQSL[0]
x393_testbench01.ddr3_i.DQSL_H3[0]
x393_testbench01.ddr3_i.DQSL_D[0]
x393_testbench01.ddr3_i.DQSL_DH1[0]
x393_testbench01.ddr3_i.DQSL_DH2[0]
x393_testbench01.ddr3_i.DQSL_DH3[0]
x393_testbench01.ddr3_i.DQSU_D[0]
@22
x393_testbench01.ddr3_i.SDD[15:0]
x393_testbench01.ddr3_i.SDD_H3[15:0]
x393_testbench01.ddr3_i.SDD_D[15:0]
@29
@28
x393_testbench01.ddr3_i.SDODT_D[0]
@1000200
-DDR3_wrap
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mclk[0]
@22
x393_testbench01.ddr3_i.SDD[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dout[63:0]
@28
x393_testbench01.ddr3_i.en_dq_dl[1:0]
x393_testbench01.ddr3_i.en_dq_d0[1:0]
x393_testbench01.ddr3_i.en_dq_d1[1:0]
x393_testbench01.ddr3_i.en_dq_out[1:0]
x393_testbench01.ddr3_i.en_dq_d3[1:0]
x393_testbench01.ddr3_i.en_dq_in[1:0]
x393_testbench01.ddr3_i.en_dqs_dl[1:0]
x393_testbench01.ddr3_i.en_dqs_out[1:0]
x393_testbench01.ddr3_i.en_dqs_in[1:0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dqsl[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.iclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_dly[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din[63:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.tin_dqs[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.tin_dq[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dout[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dqsu[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.iclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dq_block[0].dq_i.dq_dly[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dout[31:0]
@200
-
-
@1000200
-DDR3_wrap
@800200
-dqs0_dq0_out
@28
......@@ -1074,7 +1110,7 @@ x393_testbench01.x393_i.SDD[15:0]
x393_testbench01.x393_i.SDODT[0]
@1000200
-DDR3
@800200
@c00200
-phy_cmd_
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.mclk[0]
......@@ -1153,11 +1189,11 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy
-group_end
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rdata_r[63:0]
@1000200
@1401200
-phy_cmd_
@200
-
@800200
@c00200
-ch0_buf
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.data_in[63:0]
......@@ -1189,7 +1225,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.RAMB36E1_i.ADDRBWRADDR[15:0]
@200
-
@1000200
@1401200
-ch0_buf
@200
-
......@@ -1792,7 +1828,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq[0]
@1000200
-PS_PIO
@c00200
@800200
-LINEAR_CH1
@200
-
......@@ -2248,7 +2284,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want[0]
@1401200
@1000200
-LINEAR_CH1
@c00200
-TILED_CH2
......
x393_testbench01.tf
View file @ c8b52324
......@@ -33,14 +33,14 @@
`define TEST_READ_BLOCK 1
//`define TEST_SCANLINE_WRITE
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_SCANLINE_READ
`define TEST_READ_SHOW 1
//`define TEST_TILED_WRITE 0
`define TEST_TILED_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_TILED_READ 1
//`define TEST_TILED_READ 0
//`define TEST_TILED_WRITE32 0
//`define TEST_TILED_READ32 0
//`define TEST_TILED_WRITE32 1
//`define TEST_TILED_READ32 1
module x393_testbench01 #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
......@@ -721,14 +721,14 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
`ifdef USE_DDR3_WRAP
ddr3_wrap #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.TRISTATE_DELAY_CLK (1), // total 2
.TRISTATE_DELAY_CLK (4'h1), // total 2
.TRISTATE_DELAY (0),
.CLK_DELAY (0),
.CMDA_DELAY (0),
.DQS_IN_DELAY (0),
.DQ_IN_DELAY (0),
.DQS_OUT_DELAY (0),
.DQ_OUT_DELAY (0)
.CLK_DELAY (1550),
.CMDA_DELAY (1550),
.DQS_IN_DELAY (3150),
.DQ_IN_DELAY (1550),
.DQS_OUT_DELAY (1550),
.DQ_OUT_DELAY (1550)
) ddr3_i (
.mclk (WRAP_MCLK), // input
.dq_tri ({WRAP_PHY_DQ_TRI[4],WRAP_PHY_DQ_TRI[0]}), // input[1:0]
......@@ -749,7 +749,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.NDQSU (NDQSU),
.DQSL (DQSL),
.NDQSL (NDQSL),
.SDODT (SDODT) // input
.SDODT (SDODT) // input
);
`else
ddr3 #(
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment