Commit 286a6494 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

bug fixes in Verilog code

parent c8b52324

.project

+15 −15
Original line number Diff line number Diff line
@@ -62,77 +62,77 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150311172942225.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150422150006515.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150311172942225.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150422150006515.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150311172942225.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150422150006515.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150311172942225.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150422150006515.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150311172942225.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150422150006515.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150311172942225.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150422150006515.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150311172804030.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150422145717867.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150313235008423.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150422150006515.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150311172804030.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150422145717867.log</location>

		</link>

		<link>

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			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150316202414190.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150422150006515.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150311172804030.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150422145717867.log</location>

		</link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>

			<type>1</type>

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			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150422150006515.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-place.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-place-20150311172942225.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-place-20150422150006515.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-route.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-route-20150311172942225.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-route-20150422150006515.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150311172804030.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150422145717867.dcp</location>

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</projectDescription>

includes/x393_parameters.vh

+3 −1
Original line number Diff line number Diff line
@@ -244,5 +244,7 @@ 
    parameter MCNTRL_TEST01_STATUS_REG_CHN1_ADDR= 'h3c,  // status/readback register for channel 2

    parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d,  // status/readback register for channel 3

    parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e,  // status/readback register for channel 4

    parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f  // status/readback register for channel 4

    parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f,  // status/readback register for channel 4

    parameter RSEL=                               1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)

    parameter WSEL=                               1'b0  // late/early WRITE commands (to adjust timing by 1 SDCLK period)

    
 No newline at end of file

memctrl/cmd_encod_linear_rd.v

+6 −5
Original line number Diff line number Diff line
@@ -27,7 +27,8 @@ module cmd_encod_linear_rd #( 
    parameter COLADDR_NUMBER=       10,

    parameter NUM_XFER_BITS=         6,    // number of bits to specify transfer length

    parameter CMD_PAUSE_BITS=       10,

    parameter CMD_DONE_BIT=         10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!

    parameter CMD_DONE_BIT=         10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!

    parameter RSEL=                1'b1

) (

    input                        rst,

    input                        clk,
@@ -125,10 +126,10 @@ module cmd_encod_linear_rd #( 
        else case (gen_addr)

            4'h0: rom_r <= (ENC_CMD_ACTIVATE <<  ENC_CMD_SHIFT); 

            4'h1: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT); 

            4'h2: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 

            4'h3: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);

            4'h4: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT)                     | (1 << ENC_DCI) | (1 << ENC_SEL);

            4'h5: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT)                      | (1 << ENC_DCI) | (1 << ENC_SEL);

            4'h2: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL); 

            4'h3: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);

            4'h4: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT)                     | (1 << ENC_DCI) | (RSEL << ENC_SEL);

            4'h5: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT)                      | (1 << ENC_DCI) | (RSEL << ENC_SEL);

            4'h6: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT)                                              | (1 << ENC_DCI);

            4'h7: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT)                     | (1 << ENC_DCI);

            4'h8: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);

memctrl/cmd_encod_linear_rw.v

+8 −4
Original line number Diff line number Diff line
@@ -26,7 +26,9 @@ module cmd_encod_linear_rw#( 
    parameter COLADDR_NUMBER=       10,

    parameter NUM_XFER_BITS=         6,   // number of bits to specify transfer length

    parameter CMD_PAUSE_BITS=       10,

    parameter CMD_DONE_BIT=         10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!

    parameter CMD_DONE_BIT=         10,   // VDT BUG: CMD_DONE_BIT is used in a function call parameter!

    parameter RSEL=                 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)

    parameter WSEL=                 1'b0  // late/early WRITE commands (to adjust timing by 1 SDCLK period)

) (

    input                        rst,

    input                        clk,
@@ -58,7 +60,8 @@ module cmd_encod_linear_rw#( 
        .COLADDR_NUMBER    (COLADDR_NUMBER),

        .NUM_XFER_BITS     (NUM_XFER_BITS),

        .CMD_PAUSE_BITS    (CMD_PAUSE_BITS),

        .CMD_DONE_BIT      (CMD_DONE_BIT)

        .CMD_DONE_BIT      (CMD_DONE_BIT),

        .RSEL              (RSEL)

    ) cmd_encod_linear_rd_i (

        .rst                (rst), // input

        .clk                (clk), // input
@@ -78,7 +81,8 @@ module cmd_encod_linear_rw#( 
        .COLADDR_NUMBER    (COLADDR_NUMBER),

        .NUM_XFER_BITS     (NUM_XFER_BITS),

        .CMD_PAUSE_BITS    (CMD_PAUSE_BITS),

        .CMD_DONE_BIT      (CMD_DONE_BIT)

        .CMD_DONE_BIT      (CMD_DONE_BIT),

        .WSEL              (WSEL)

    ) cmd_encod_linear_wr_i (

        .rst                (rst), // input

        .clk                (clk), // input

memctrl/cmd_encod_tiled_32_rd.v

+13 −13
Original line number Diff line number Diff line
@@ -47,8 +47,8 @@ module cmd_encod_tiled_32_rd #( 
    parameter COLADDR_NUMBER=       10,

    parameter CMD_PAUSE_BITS=       10,

    parameter CMD_DONE_BIT=         10,  // VDT BUG: CMD_DONE_BIT is used in a function call parameter!

    parameter FRAME_WIDTH_BITS=     13  // Maximal frame width - 8-word (16 bytes) bursts 

    

    parameter FRAME_WIDTH_BITS=     13,  // Maximal frame width - 8-word (16 bytes) bursts 

    parameter RSEL=                 1'b1 // Late/early READ commands

) (

    input                        rst,

    input                        clk,
@@ -227,20 +227,20 @@ module cmd_encod_tiled_32_rd #( 
        else case (gen_addr)

            4'h0: rom_r <= (ENC_CMD_ACTIVATE <<  ENC_CMD_SHIFT)  | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE

            4'h1: rom_r <= (ENC_CMD_ACTIVATE <<  ENC_CMD_SHIFT);

            4'h2: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 

            4'h3: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 

            4'h2: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL); 

            4'h3: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL); 

// loop:            

            4'h4: rom_r <= (ENC_CMD_ACTIVATE <<  ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 

            4'h5: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 

            4'h6: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 

            4'h4: rom_r <= (ENC_CMD_ACTIVATE <<  ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL); 

            4'h5: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL); 

            4'h6: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL); 

// end loop            

            4'h7: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 

            4'h8: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);

            4'h9: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 

            4'h7: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL); 

            4'h8: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL);

            4'h9: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL); 

// do not combine this NOP -  ENC_CMD_READ + ENC_NOP enables autoprecharge

            4'ha: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 

            4'hb: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT)                     | (1 << ENC_DCI) | (1 << ENC_SEL); 

            4'hc: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (1 << ENC_BUF_PGNEXT); 

            4'ha: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (RSEL << ENC_SEL); 

            4'hb: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT)                     | (1 << ENC_DCI) | (RSEL << ENC_SEL); 

            4'hc: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_DCI) | (RSEL << ENC_SEL) | (1 << ENC_BUF_PGNEXT); 

            4'hd: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT)                     | (1 << ENC_DCI);

            4'he: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);

            default:rom_r <= 0;