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Elphel
x393
Commits
b721ae66
Commit
b721ae66
authored
Jul 21, 2015
by
Andrey Filippov
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69 changed files
with
2089 additions
and
1950 deletions
+2089
-1950
axibram_read.v
axi/axibram_read.v
+17
-20
axibram_write.v
axi/axibram_write.v
+19
-38
cmprs_afi_mux.v
axi/cmprs_afi_mux.v
+8
-3
cmprs_afi_mux_status.v
axi/cmprs_afi_mux_status.v
+15
-8
histogram_saxi.v
axi/histogram_saxi.v
+33
-28
membridge.v
axi/membridge.v
+105
-102
mult_saxi_wr.v
axi/mult_saxi_wr.v
+18
-14
cmd_mux.v
cmd_mux.v
+15
-12
cmd_readback.v
cmd_readback.v
+9
-8
cmprs_cmd_decode.v
compressor_jp/cmprs_cmd_decode.v
+31
-31
cmprs_frame_sync.v
compressor_jp/cmprs_frame_sync.v
+9
-7
cmprs_macroblock_buf_iface.v
compressor_jp/cmprs_macroblock_buf_iface.v
+9
-5
cmprs_out_fifo.v
compressor_jp/cmprs_out_fifo.v
+14
-11
compressor393.v
compressor_jp/compressor393.v
+20
-6
jp_channel.v
compressor_jp/jp_channel.v
+85
-64
stuffer393.v
compressor_jp/stuffer393.v
+12
-3
event_logger.v
logger/event_logger.v
+17
-11
imu_exttime393.v
logger/imu_exttime393.v
+21
-7
cmd_encod_linear_rd.v
memctrl/cmd_encod_linear_rd.v
+12
-85
cmd_encod_linear_rw.v
memctrl/cmd_encod_linear_rw.v
+6
-6
cmd_encod_linear_wr.v
memctrl/cmd_encod_linear_wr.v
+18
-39
cmd_encod_tiled_rd.v
memctrl/cmd_encod_tiled_rd.v
+35
-42
cmd_encod_tiled_rw.v
memctrl/cmd_encod_tiled_rw.v
+19
-19
cmd_encod_tiled_wr.v
memctrl/cmd_encod_tiled_wr.v
+22
-28
ddr_refresh.v
memctrl/ddr_refresh.v
+13
-13
mcntrl393.v
memctrl/mcntrl393.v
+77
-71
mcntrl393_test01.v
memctrl/mcntrl393_test01.v
+69
-63
mcntrl_linear_rw.v
memctrl/mcntrl_linear_rw.v
+67
-65
mcntrl_ps_pio.v
memctrl/mcntrl_ps_pio.v
+34
-31
mcntrl_tiled_rw.v
memctrl/mcntrl_tiled_rw.v
+67
-93
memctrl16.v
memctrl/memctrl16.v
+131
-120
mcontr_sequencer.v
memctrl/phy/mcontr_sequencer.v
+145
-139
phy_cmd.v
memctrl/phy/phy_cmd.v
+65
-82
phy_top.v
memctrl/phy/phy_top.v
+27
-7
scheduler16.v
memctrl/scheduler16.v
+7
-7
pxd_single.v
sensor/pxd_single.v
+7
-6
sens_gamma.v
sensor/sens_gamma.v
+22
-18
sens_histogram.v
sensor/sens_histogram.v
+9
-6
sens_parallel12.v
sensor/sens_parallel12.v
+83
-65
sens_sync.v
sensor/sens_sync.v
+9
-10
sensor_channel.v
sensor/sensor_channel.v
+36
-15
sensor_fifo.v
sensor/sensor_fifo.v
+30
-25
sensor_i2c.v
sensor/sensor_i2c.v
+5
-3
sensor_i2c_io.v
sensor/sensor_i2c_io.v
+32
-32
sensors393.v
sensor/sensors393.v
+24
-29
status_read.v
status_read.v
+15
-34
camsync393.v
timing/camsync393.v
+21
-19
rtc393.v
timing/rtc393.v
+17
-13
timestamp_fifo.v
timing/timestamp_fifo.v
+15
-10
timestamp_snapshot.v
timing/timestamp_snapshot.v
+5
-4
timing393.v
timing/timing393.v
+20
-8
clocks393.v
util_modules/clocks393.v
+15
-12
cmd_deser.v
util_modules/cmd_deser.v
+27
-11
cmd_frame_sequencer.v
util_modules/cmd_frame_sequencer.v
+10
-9
cmd_seq_mux.v
util_modules/cmd_seq_mux.v
+16
-14
fifo_1cycle.v
util_modules/fifo_1cycle.v
+22
-12
fifo_2regs.v
util_modules/fifo_2regs.v
+4
-4
fifo_cross_clocks.v
util_modules/fifo_cross_clocks.v
+17
-12
gpio393.v
util_modules/gpio393.v
+26
-22
level_cross_clocks.v
util_modules/level_cross_clocks.v
+1
-1
mcont_common_chnbuf_reg.v
util_modules/mcont_common_chnbuf_reg.v
+1
-1
mcont_to_chnbuf_reg.v
util_modules/mcont_to_chnbuf_reg.v
+6
-4
pulse_cross_clock.v
util_modules/pulse_cross_clock.v
+3
-3
status_generate.v
util_modules/status_generate.v
+38
-16
status_router16.v
util_modules/status_router16.v
+4
-0
status_router2.v
util_modules/status_router2.v
+14
-7
status_router4.v
util_modules/status_router4.v
+4
-0
status_router8.v
util_modules/status_router8.v
+4
-0
x393.v
x393.v
+256
-237
No files found.
axi/axibram_read.v
View file @
b721ae66
...
...
@@ -25,20 +25,16 @@ module axibram_read #(
parameter
ADDRESS_BITS
=
10
// number of memory address bits
)(
input
aclk
,
// clock - should be buffered
// input
aresetn, // reset, active low
input
rst
,
//
reset, active high
// input
rst, // reset, active high
input
arst
,
// @posedge aclk sync
reset, active high
// AXI Read Address
input
[
31
:
0
]
araddr
,
// ARADDR[31:0], input
input
arvalid
,
// ARVALID, input
output
arready
,
// ARREADY, output
input
[
11
:
0
]
arid
,
// ARID[11:0], input
// input [ 1:0] arlock, // ARLOCK[1:0], input
// input [ 3:0] archache,// ARCACHE[3:0], input
// input [ 2:0] arprot, // ARPROT[2:0], input
input
[
3
:
0
]
arlen
,
// ARLEN[3:0], input
input
[
1
:
0
]
arsize
,
// ARSIZE[1:0], input
input
[
1
:
0
]
arburst
,
// ARBURST[1:0], input
// input [ 3:0] adqos, // ARQOS[3:0], input
// AXI Read Data
output
[
31
:
0
]
rdata
,
// RDATA[31:0], output
output
reg
rvalid
,
// RVALID, output
...
...
@@ -145,30 +141,30 @@ module axibram_read #(
assign
rdata
[
31
:
0
]
=
bram_rdata
;
// data out
always
@
(
posedge
aclk
or
posedge
rst
)
begin
always
@
(
posedge
aclk
)
begin
`ifdef
USE_SHORT_REN_REGEN
if
(
rst
)
bram_regen_r
<=
0
;
if
(
a
rst
)
bram_regen_r
<=
0
;
else
bram_regen_r
<=
bram_ren
;
`endif
if
(
rst
)
pre_last_in_burst_r
<=
0
;
if
(
a
rst
)
pre_last_in_burst_r
<=
0
;
// else if (start_read_burst_w) pre_last_in_burst_r <= (read_left==4'b0);
else
if
(
bram_reg_re_w
)
pre_last_in_burst_r
<=
(
read_left
==
4'b0
)
;
if
(
rst
)
rburst
[
1
:
0
]
<=
0
;
if
(
a
rst
)
rburst
[
1
:
0
]
<=
0
;
else
if
(
start_read_burst_w
)
rburst
[
1
:
0
]
<=
arburst_out
[
1
:
0
]
;
if
(
rst
)
rlen
[
3
:
0
]
<=
0
;
if
(
a
rst
)
rlen
[
3
:
0
]
<=
0
;
else
if
(
start_read_burst_w
)
rlen
[
3
:
0
]
<=
arlen_out
[
3
:
0
]
;
if
(
rst
)
read_in_progress
<=
0
;
if
(
a
rst
)
read_in_progress
<=
0
;
else
read_in_progress
<=
read_in_progress_w
;
if
(
rst
)
read_in_progress_d
<=
0
;
if
(
a
rst
)
read_in_progress_d
<=
0
;
// else read_in_progress_d <= read_in_progress_d_w;
else
if
(
bram_reg_re_w
)
read_in_progress_d
<=
read_in_progress_d_w
;
if
(
rst
)
read_in_progress_or
<=
0
;
if
(
a
rst
)
read_in_progress_or
<=
0
;
// else read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// else if (bram_reg_re_w) read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// FIXME:
...
...
@@ -177,22 +173,23 @@ module axibram_read #(
// reg read_in_progress_d=0; // delayed by one active cycle (not skipped)
// reg read_in_progress_or=0; // read_in_progress || read_in_progress_d
if
(
rst
)
read_left
<=
0
;
if
(
arst
)
read_left
<=
0
;
else
if
(
start_read_burst_w
)
read_left
<=
arlen_out
[
3
:
0
]
;
// precedence over inc
else
if
(
bram_reg_re_w
)
read_left
<=
read_left
-
1
;
//SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if
(
rst
)
read_address
<=
{
ADDRESS_BITS
{
1'b0
}};
if
(
arst
)
read_address
<=
{
ADDRESS_BITS
{
1'b0
}};
else
if
(
start_read_burst_w
)
read_address
<=
araddr_out
[
ADDRESS_BITS
-
1
:
0
]
;
// precedence over inc
else
if
(
bram_reg_re_w
)
read_address
<=
next_rd_address_w
;
if
(
rst
)
rvalid
<=
1'b0
;
if
(
arst
)
rvalid
<=
1'b0
;
else
if
(
bram_reg_re_w
&&
read_in_progress_d
)
rvalid
<=
1'b1
;
else
if
(
rready
)
rvalid
<=
1'b0
;
if
(
rst
)
rlast
<=
1'b0
;
if
(
arst
)
rlast
<=
1'b0
;
else
if
(
last_in_burst_d_w
)
rlast
<=
1'b1
;
else
if
(
rready
)
rlast
<=
1'b0
;
end
always
@
(
posedge
aclk
)
begin
//SuppressThisWarning ISExst Assignment to bram_reg_re_0 ignored, since the identifier is never used
// bram_reg_re_0 <= read_in_progress_w && !pre_rvalid_w;
...
...
@@ -240,9 +237,9 @@ module axibram_read #(
fifo_same_clock
#(
.
DATA_WIDTH
(
ADDRESS_BITS
+
20
)
,.
DATA_DEPTH
(
4
))
raddr_i
(
.
rst
(
rst
)
,
.
rst
(
1'b0
)
,
.
clk
(
aclk
)
,
.
sync_rst
(
1'b0
)
,
// input
.
sync_rst
(
arst
)
,
.
we
(
arvalid
&&
arready
)
,
.
re
(
start_read_burst_w
)
,
.
data_in
(
{
arid
[
11
:
0
]
,
arburst
[
1
:
0
]
,
arsize
[
1
:
0
]
,
arlen
[
3
:
0
]
,
araddr
[
ADDRESS_BITS
+
1
:
2
]
}
)
,
...
...
axi/axibram_write.v
View file @
b721ae66
...
...
@@ -26,21 +26,16 @@ module axibram_write #(
parameter
ADDRESS_BITS
=
10
// number of memory address bits
)(
input
aclk
,
// clock - should be buffered
// input aresetn, // reset, active low
input
rst
,
// reset, active highw
input
arst
,
// @aclk sync reset, active high
// AXI Write Address
input
[
31
:
0
]
awaddr
,
// AWADDR[31:0], input
input
awvalid
,
// AWVALID, input
output
awready
,
// AWREADY, output
input
[
11
:
0
]
awid
,
// AWID[11:0], input
// input [ 1:0] awlock, // AWLOCK[1:0], input
// input [ 3:0] awcache, // AWCACHE[3:0], input
// input [ 2:0] awprot, // AWPROT[2:0], input
input
[
3
:
0
]
awlen
,
// AWLEN[3:0], input
input
[
1
:
0
]
awsize
,
// AWSIZE[1:0], input
input
[
1
:
0
]
awburst
,
// AWBURST[1:0], input
// input [ 3:0] awqos, // AWQOS[3:0], input
// AXI PS Master GP0: Write Data
input
[
31
:
0
]
wdata
,
// WDATA[31:0], input
input
wvalid
,
// WVALID, input
...
...
@@ -141,44 +136,30 @@ module axibram_write #(
assign
start_write_burst_w
=
w_nempty_ready
&&
aw_nempty_ready
&&
(
!
write_in_progress
||
(
w_nempty_ready
&&
((
write_left
[
3
:
0
]
==
4'b0
)
||
wlast_out
)))
;
assign
write_in_progress_w
=
w_nempty_ready
&&
aw_nempty_ready
||
(
write_in_progress
&&
!
(
w_nempty_ready
&&
((
write_left
[
3
:
0
]
==
4'b0
)
||
wlast_out
)))
;
always
@
(
posedge
aclk
or
posedge
rst
)
begin
if
(
rst
)
wburst
[
1
:
0
]
<=
0
;
always
@
(
posedge
aclk
)
begin
if
(
arst
)
wburst
[
1
:
0
]
<=
0
;
else
if
(
start_write_burst_w
)
wburst
[
1
:
0
]
<=
awburst_out
[
1
:
0
]
;
if
(
rst
)
wlen
[
3
:
0
]
<=
0
;
if
(
arst
)
wlen
[
3
:
0
]
<=
0
;
else
if
(
start_write_burst_w
)
wlen
[
3
:
0
]
<=
awlen_out
[
3
:
0
]
;
if
(
rst
)
write_in_progress
<=
0
;
else
write_in_progress
<=
write_in_progress_w
;
if
(
a
rst
)
write_in_progress
<=
0
;
else
write_in_progress
<=
write_in_progress_w
;
if
(
rst
)
write_left
<=
0
;
if
(
arst
)
write_left
<=
0
;
else
if
(
start_write_burst_w
)
write_left
<=
awlen_out
[
3
:
0
]
;
// precedence over inc
else
if
(
bram_we_w
)
write_left
<=
write_left
-
1
;
//SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if
(
rst
)
write_address
<=
{
ADDRESS_BITS
{
1'b0
}};
if
(
arst
)
write_address
<=
{
ADDRESS_BITS
{
1'b0
}};
else
if
(
start_write_burst_w
)
write_address
<=
awaddr_out
[
ADDRESS_BITS
-
1
:
0
]
;
// precedence over inc
else
if
(
bram_we_w
)
write_address
<=
next_wr_address_w
;
if
(
rst
)
dev_ready_r
<=
1'b0
;
else
dev_ready_r
<=
dev_ready
;
if
(
a
rst
)
dev_ready_r
<=
1'b0
;
else
dev_ready_r
<=
dev_ready
;
end
// **** Write response channel ****
wire
[
1
:
0
]
bresp_in
;
assign
bresp_in
=
2'b0
;
/*
output bvalid, // BVALID, output
input bready, // BREADY, input
output [11:0] bid, // BID[11:0], output
output [ 1:0] bresp // BRESP[1:0], output
*/
/*
reg bram_reg_re_r;
always @ (posedge aclk) begin
bram_reg_re_r <= bram_reg_re_w;
end
*/
// external memory interface (write only)
assign
pre_awaddr
=
awaddr_out
[
ADDRESS_BITS
-
1
:
0
]
;
...
...
@@ -199,9 +180,9 @@ module axibram_write #(
`endif
fifo_same_clock
#(
.
DATA_WIDTH
(
20
+
ADDRESS_BITS
)
,.
DATA_DEPTH
(
4
))
waddr_i
(
.
rst
(
rst
)
,
.
rst
(
1'b0
)
,
//
rst),
.
clk
(
aclk
)
,
.
sync_rst
(
1'b0
)
,
.
sync_rst
(
arst
)
,
.
we
(
awvalid
&&
awready
)
,
.
re
(
start_write_burst_w
)
,
.
data_in
(
{
awid
[
11
:
0
]
,
awburst
[
1
:
0
]
,
awsize
[
1
:
0
]
,
awlen
[
3
:
0
]
,
awaddr
[
ADDRESS_BITS
+
1
:
2
]
}
)
,
...
...
@@ -219,9 +200,9 @@ fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
)
;
fifo_same_clock
#(
.
DATA_WIDTH
(
49
)
,.
DATA_DEPTH
(
4
))
wdata_i
(
.
rst
(
rst
)
,
.
rst
(
1'b0
)
,
//
rst),
.
clk
(
aclk
)
,
.
sync_rst
(
1'b0
)
,
.
sync_rst
(
arst
)
,
.
we
(
wvalid
&&
wready
)
,
.
re
(
bram_we_w
)
,
//start_write_burst_w), // wrong
.
data_in
(
{
wid
[
11
:
0
]
,
wlast
,
wstb
[
3
:
0
]
,
wdata
[
31
:
0
]
}
)
,
...
...
@@ -241,16 +222,16 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
reg
was_bresp_re
=
0
;
wire
bresp_re
;
assign
bresp_re
=
bready
&&
bvalid
&&
!
was_bresp_re
;
always
@
(
posedge
rst
or
posedge
aclk
)
begin
if
(
rst
)
was_bresp_re
<=
0
;
else
was_bresp_re
<=
bresp_re
;
always
@
(
posedge
aclk
)
begin
if
(
a
rst
)
was_bresp_re
<=
0
;
else
was_bresp_re
<=
bresp_re
;
end
fifo_same_clock
#(
.
DATA_WIDTH
(
14
)
,.
DATA_DEPTH
(
4
))
wresp_i
(
.
rst
(
rst
)
,
.
rst
(
1'b0
)
,
//
rst),
.
clk
(
aclk
)
,
.
sync_rst
(
1'b0
)
,
.
sync_rst
(
arst
)
,
.
we
(
bram_we_w
&&
((
write_left
[
3
:
0
]
==
4'b0
)
||
wlast_out
))
,
// added ((write_left[3:0]==4'b0) || wlast_out) - only last wrtite -> bresp
// .re(bready && bvalid),
.
re
(
bresp_re
)
,
// not allowing RE next cycle after bvalid
...
...
axi/cmprs_afi_mux.v
View file @
b721ae66
...
...
@@ -34,9 +34,11 @@ module cmprs_afi_mux#(
parameter
CMPRS_AFIMUX_CYCBITS
=
3
,
parameter
AFI_MUX_BUF_LATENCY
=
2
// buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
)(
input
rst
,
//
input rst,
input
mclk
,
// for command/status
input
hclk
,
// global clock to run axi_hp @ 150MHz, shared by all compressor channels
input
mrst
,
// @posedge mclk, sync reset
input
hrst
,
// @posedge xclk, sync reset
// programming interface
input
[
7
:
0
]
cmd_ad
,
// byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input
cmd_stb
,
// strobe (with first byte) for the command a/d
...
...
@@ -386,8 +388,9 @@ module cmprs_afi_mux#(
.
ADDR_WIDTH
(
4
)
,
.
DATA_WIDTH
(
32
)
)
cmd_deser_32bit_i
(
.
rst
(
rst
)
,
// input
.
rst
(
1'b0
)
,
//
rst), // input
.
clk
(
mclk
)
,
// input
.
srst
(
mrst
)
,
// input
.
ad
(
cmd_ad
)
,
// input[7:0]
.
stb
(
cmd_stb
)
,
// input
.
addr
(
cmd_a
)
,
// output[3:0]
...
...
@@ -436,9 +439,11 @@ module cmprs_afi_mux#(
.
CMPRS_AFIMUX_WIDTH
(
CMPRS_AFIMUX_WIDTH
)
,
.
CMPRS_AFIMUX_CYCBITS
(
CMPRS_AFIMUX_CYCBITS
)
)
cmprs_afi_mux_status_i
(
.
rst
(
rst
)
,
// input
//
.rst (rst), // input
.
hclk
(
hclk
)
,
// input
.
mclk
(
mclk
)
,
// input
.
mrst
(
mrst
)
,
// input
.
hrst
(
hrst
)
,
// input
.
cmd_data
(
cmd_data
[
15
:
0
])
,
// input[15:0]
.
cmd_a
(
cmd_a
[
1
:
0
])
,
// input[1:0]
.
status_we
(
cmd_we_status_w
)
,
// input
...
...
axi/cmprs_afi_mux_status.v
View file @
b721ae66
...
...
@@ -29,9 +29,11 @@ module cmprs_afi_mux_status #(
parameter
CMPRS_AFIMUX_WIDTH
=
26
,
// maximal for status: currently only works with 26)
parameter
CMPRS_AFIMUX_CYCBITS
=
3
)
(
input
rst
,
//
input rst,
input
hclk
,
// global clock to run axi_hp @ 150MHz, shared by all compressor channels
input
mclk
,
// for command/status
input
mrst
,
// @posedge mclk, sync reset
input
hrst
,
// @posedge xclk, sync reset
// mclk domain
input
[
15
:
0
]
cmd_data
,
//
input
[
1
:
0
]
cmd_a
,
//
...
...
@@ -100,11 +102,12 @@ module cmprs_afi_mux_status #(
end
pulse_cross_clock
mode_we_hclk_i
(
.
rst
(
rst
)
,
.
src_clk
(
mclk
)
,
.
dst_clk
(
hclk
)
,
.
in_pulse
(
mode_we
)
,
.
out_pulse
(
mode_we_hclk
)
,.
busy
())
;
pulse_cross_clock
stb_mclk_i
(
.
rst
(
rst
)
,
.
src_clk
(
hclk
)
,
.
dst_clk
(
mclk
)
,
.
in_pulse
(
stb_r
)
,
.
out_pulse
(
stb_mclk
)
,
.
busy
())
;
pulse_cross_clock
mode_we_hclk_i
(
.
rst
(
m
rst
)
,
.
src_clk
(
mclk
)
,
.
dst_clk
(
hclk
)
,
.
in_pulse
(
mode_we
)
,
.
out_pulse
(
mode_we_hclk
)
,.
busy
())
;
pulse_cross_clock
stb_mclk_i
(
.
rst
(
h
rst
)
,
.
src_clk
(
hclk
)
,
.
dst_clk
(
mclk
)
,
.
in_pulse
(
stb_r
)
,
.
out_pulse
(
stb_mclk
)
,
.
busy
())
;
status_router4
status_router4_i
(
.
rst
(
rst
)
,
// input
.
rst
(
1'b0
)
,
//
rst), // input
.
clk
(
mclk
)
,
// input
.
srst
(
mrst
)
,
// input
.
db_in0
(
ad
[
0
*
8
+:
8
])
,
// input[7:0]
.
rq_in0
(
rq
[
0
])
,
// input
.
start_in0
(
start
[
0
])
,
// output
...
...
@@ -127,8 +130,9 @@ module cmprs_afi_mux_status #(
.
STATUS_REG_ADDR
(
CMPRS_AFIMUX_STATUS_REG_ADDR
+
0
)
,
.
PAYLOAD_BITS
(
CMPRS_AFIMUX_WIDTH
)
)
status_generate0_i
(
.
rst
(
rst
)
,
// input
.
rst
(
1'b0
)
,
//
rst), // input
.
clk
(
mclk
)
,
// input
.
srst
(
mrst
)
,
// input
.
we
(
status_we
&&
(
cmd_a
==
0
))
,
// input
.
wd
(
cmd_data
[
7
:
0
])
,
// input[7:0]
.
status
(
status_data
[
0
*
CMPRS_AFIMUX_WIDTH
+:
CMPRS_AFIMUX_WIDTH
])
,
// input[25:0]
...
...
@@ -141,8 +145,9 @@ module cmprs_afi_mux_status #(
.
STATUS_REG_ADDR
(
CMPRS_AFIMUX_STATUS_REG_ADDR
+
0
)
,
.
PAYLOAD_BITS
(
CMPRS_AFIMUX_WIDTH
)
)
status_generate1_i
(
.
rst
(
rst
)
,
// input
.
rst
(
1'b0
)
,
//
rst), // input
.
clk
(
mclk
)
,
// input
.
srst
(
mrst
)
,
// input
.
we
(
status_we
&&
(
cmd_a
==
1
))
,
// input
.
wd
(
cmd_data
[
7
:
0
])
,
// input[7:0]
.
status
(
status_data
[
1
*
CMPRS_AFIMUX_WIDTH
+:
CMPRS_AFIMUX_WIDTH
])
,
// input[25:0]
...
...
@@ -155,8 +160,9 @@ module cmprs_afi_mux_status #(
.
STATUS_REG_ADDR
(
CMPRS_AFIMUX_STATUS_REG_ADDR
+
0
)
,
.
PAYLOAD_BITS
(
CMPRS_AFIMUX_WIDTH
)
)
status_generate2_i
(
.
rst
(
rst
)
,
// input
.
rst
(
1'b0
)
,
//
rst), // input
.
clk
(
mclk
)
,
// input
.
srst
(
mrst
)
,
// input
.
we
(
status_we
&&
(
cmd_a
==
2
))
,
// input
.
wd
(
cmd_data
[
7
:
0
])
,
// input[7:0]
.
status
(
status_data
[
2
*
CMPRS_AFIMUX_WIDTH
+:
CMPRS_AFIMUX_WIDTH
])
,
// input[25:0]
...
...
@@ -169,8 +175,9 @@ module cmprs_afi_mux_status #(
.
STATUS_REG_ADDR
(
CMPRS_AFIMUX_STATUS_REG_ADDR
+
0
)
,
.
PAYLOAD_BITS
(
CMPRS_AFIMUX_WIDTH
)
)
status_generate3_i
(
.
rst
(
rst
)
,
// input
.
rst
(
1'b0
)
,
//
rst), // input
.
clk
(
mclk
)
,
// input
.
srst
(
mrst
)
,
// input
.
we
(
status_we
&&
(
cmd_a
==
3
))
,
// input
.
wd
(
cmd_data
[
7
:
0
])
,
// input[7:0]
.
status
(
status_data
[
3
*
CMPRS_AFIMUX_WIDTH
+:
CMPRS_AFIMUX_WIDTH
])
,
// input[25:0]
...
...
axi/histogram_saxi.v
View file @
b721ae66
...
...
@@ -37,9 +37,12 @@ module histogram_saxi#(
// parameter HIST_SAXI_STATUS_REG = 'h34,
parameter
NUM_FRAME_BITS
=
4
// number of bits use for frame number
)(
input
rst
,
//
input rst,
input
mclk
,
// for command/status
input
aclk
,
// global clock to run s_axi (@150MHz?)
input
mrst
,
// @posedge mclk, sync reset
input
arst
,
// @posedge aclk, sync reset
// sensor 0, data valid @posedge mclk
input
[
NUM_FRAME_BITS
-
1
:
0
]
frame0
,
// frame number for which the histogram is provided
input
hist_request0
,
// request to transfer a burst
...
...
@@ -248,8 +251,8 @@ module histogram_saxi#(
assign
page_sent_aclk
=
block_run
[
1
]
&&
!
block_run
[
0
]
;
// command interface
always
@
(
posedge
rst
or
posedge
mclk
)
begin
if
(
rst
)
mode
<=
0
;
always
@
(
posedge
mclk
)
begin
if
(
m
rst
)
mode
<=
0
;
else
if
(
we_mode
)
mode
<=
cmd_data
[
HIST_SAXI_MODE_WIDTH
-
1
:
0
]
;
end
always
@
(
posedge
mclk
)
begin
...
...
@@ -357,7 +360,7 @@ module histogram_saxi#(
pulse_cross_clock
pulse_cross_clock_page_sent_i
(
.
rst
(
rst
)
,
// input
.
rst
(
a
rst
)
,
// input
.
src_clk
(
aclk
)
,
// input
.
dst_clk
(
mclk
)
,
// input
.
in_pulse
(
page_sent_aclk
)
,
// input
...
...
@@ -365,7 +368,7 @@ module histogram_saxi#(
.
busy
()
// output
)
;
pulse_cross_clock
pulse_cross_clock_page_written_aclk_i
(
.
rst
(
rst
)
,
// input
.
rst
(
m
rst
)
,
// input
.
src_clk
(
mclk
)
,
// input
.
dst_clk
(
aclk
)
,
// input
.
in_pulse
(
burst_done_w
)
,
// input
...
...
@@ -384,12 +387,13 @@ module histogram_saxi#(
.
ADDR2
(
0
)
,
.
ADDR_MASK2
(
0
)
)
cmd_deser_sens_i2c_i
(
.
rst
(
rst
)
,
// input
.
clk
(
mclk
)
,
// input
.
ad
(
cmd_ad
)
,
// input[7:0]
.
stb
(
cmd_stb
)
,
// input
.
addr
(
cmd_wa
)
,
// output[3:0]
.
data
(
cmd_data
)
,
// output[31:0]
.
rst
(
1'b0
)
,
// input
.
clk
(
mclk
)
,
// input
.
srst
(
mrst
)
,
// input
.
ad
(
cmd_ad
)
,
// input[7:0]
.
stb
(
cmd_stb
)
,
// input
.
addr
(
cmd_wa
)
,
// output[3:0]
.
data
(
cmd_data
)
,
// output[31:0]
.
we
(
{
we_mode
,
we_addr
}
)
// output
)
;
...
...
@@ -399,31 +403,32 @@ module histogram_saxi#(
.
LOG2WIDTH_RD
(
5
)
,
.
DUMMY
(
0
)
)
ram_var_w_var_r_i
(
.
rclk
(
aclk
)
,
// input
.
raddr
(
{
page_rd
[
1
:
0
]
,
page_ra
[
7
:
0
]
}
)
,
// input[9:0]
.
ren
(
buf_re
[
0
])
,
// input
.
regen
(
buf_re
[
1
])
,
// input
.
data_out
(
inter_buf_data
)
,
// output[31:0]
.
wclk
(
mclk
)
,
// input
.
rclk
(
aclk
)
,
// input
.
raddr
(
{
page_rd
[
1
:
0
]
,
page_ra
[
7
:
0
]
}
)
,
// input[9:0]
.
ren
(
buf_re
[
0
])
,
// input
.
regen
(
buf_re
[
1
])
,
// input
.
data_out
(
inter_buf_data
)
,
// output[31:0]
.
wclk
(
mclk
)
,
// input
.
waddr
(
{
page_wr
[
1
:
0
]
,
page_wa
[
7
:
0
]
}
)
,
// input[9:0]
.
we
(
dav_r
)
,
// input
.
web
(
8'hff
)
,
// input[7:0]
.
data_in
(
din_r
)
// input[31:0]
.
we
(
dav_r
)
,
// input
.
web
(
8'hff
)
,
// input[7:0]
.
data_in
(
din_r
)
// input[31:0]
)
;
// Small extra FIFO to tolerate ram_var_w_var_r latency
fifo_same_clock
#(
.
DATA_WIDTH
(
32
)
,
.
DATA_DEPTH
(
4
)
)
fifo_same_clock_i
(
.
rst
(
rst
)
,
// input
.
clk
(
aclk
)
,
// input
.
sync_rst
(
!
en_aclk
)
,
// input
.
we
(
buf_re
[
2
])
,
// input
.
re
(
fifo_re
)
,
// input
.
rst
(
1'b0
)
,
// input
.
clk
(
aclk
)
,
// input
.
sync_rst
(
arst
)
,
// input
.
sync_rst
(
!
en_aclk
)
,
// input
.
we
(
buf_re
[
2
])
,
// input
.
re
(
fifo_re
)
,
// input
.
data_in
(
inter_buf_data
)
,
// input[31:0]
.
data_out
(
saxi_wdata
)
,
// output[31:0]
.
nempty
(
fifo_nempty
)
,
// output
.
half_full
(
fifo_half_full
)
// output reg
.
data_out
(
saxi_wdata
)
,
// output[31:0]
.
nempty
(
fifo_nempty
)
,
// output
.
half_full
(
fifo_half_full
)
// output reg
)
;
endmodule
axi/membridge.v
View file @
b721ae66
This diff is collapsed.
Click to expand it.
axi/mult_saxi_wr.v
View file @
b721ae66
...
...
@@ -39,9 +39,11 @@ module mult_saxi_wr #(
parameter
MULT_SAXI_ADV_RD
=
3
// number of clock cycles before end of write to genearte adv_wr_done
)
(
input
rst
,
// global reset
//
input rst, // global reset
input
mclk
,
// system clock
input
aclk
,
// global clock to run s_axi (@150MHz?)
input
mrst
,
// @mclk sync reset
input
arst
,
// @aclk sync reset
// command interface
input
[
7
:
0
]
cmd_ad
,
// byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input
cmd_stb
,
// strobe (with first byte) for the command a/d
...
...
@@ -161,8 +163,8 @@ module mult_saxi_wr #(
assign
en_chn_mclk
=
mode_reg
[
3
:
0
]
;
assign
run_chn_mclk
=
mode_reg
[
7
:
4
]
;
always
@
(
posedge
rst
or
posedge
mclk
)
begin
if
(
rst
)
mode_reg
<=
0
;
always
@
(
posedge
mclk
)
begin
if
(
mrst
)
mode_reg
<=
0
;
else
if
(
we_ctrl
&&
!
cmd_a
[
0
])
mode_reg
<=
cmd_data
[
7
:
0
]
;
end
...
...
@@ -420,15 +422,15 @@ module mult_saxi_wr #(
.
DATA_WIDTH
(
35
)
,
.
DATA_DEPTH
(
4
)
)
fifo_same_clock_i
(
.
rst
(
rst
)
,
// input
.
clk
(
aclk
)
,
// input
.
sync_rst
(
!
en_aclk
)
,
// input
.
we
(
buf_re
[
2
])
,
// input
.
re
(
fifo_re
)
,
// input
.
rst
(
1'b0
)
,
//
rst), // input
.
clk
(
aclk
)
,
// input
.
sync_rst
(
!
en_aclk
||
arst
)
,
// input
.
we
(
buf_re
[
2
])
,
// input
.
re
(
fifo_re
)
,
// input
.
data_in
(
{
chn_rd_data
,
is_last_rd
[
1
]
,
inter_buf_data
}
)
,
// input[31:0]
.
data_out
(
{
chn_fifo_out
,
saxi_wlast
,
saxi_wdata
}
)
,
// output[31:0]
.
nempty
(
fifo_nempty
)
,
// output
.
half_full
(
fifo_half_full
)
// output reg
.
nempty
(
fifo_nempty
)
,
// output
.
half_full
(
fifo_half_full
)
// output reg
)
;
generate
...
...
@@ -481,8 +483,9 @@ module mult_saxi_wr #(
.
ADDR2
(
0
)
,
.
ADDR_MASK2
(
0
)
)
cmd_deser_sens_i2c_i
(
.
rst
(
rst
)
,
// input
.
rst
(
1'b0
)
,
//
rst), // input
.
clk
(
mclk
)
,
// input
.
srst
(
mrst
)
,
// input
.
ad
(
cmd_ad
)
,
// input[7:0]
.
stb
(
cmd_stb
)
,
// input
.
addr
(
cmd_a
)
,
// output[3:0]
...
...
@@ -509,7 +512,7 @@ module mult_saxi_wr #(
if
(
pntr_we_mclk
&&
(
pntr_wa
==
2'h3
))
status_pntr3
<=
pntr_wd
;
end
pulse_cross_clock
status_wr_i
(
.
rst
(
rst
)
,
.
src_clk
(
aclk
)
,
.
dst_clk
(
mclk
)
,
.
in_pulse
(
pntr_we
)
,
.
out_pulse
(
pntr_we_mclk
)
,.
busy
())
;
pulse_cross_clock
status_wr_i
(
.
rst
(
a
rst
)
,
.
src_clk
(
aclk
)
,
.
dst_clk
(
mclk
)
,
.
in_pulse
(
pntr_we
)
,
.
out_pulse
(
pntr_we_mclk
)
,.
busy
())
;
status_generate
#(
.
STATUS_REG_ADDR
(
MULT_SAXI_STATUS_REG
+
4
)
,
// not used
...
...
@@ -518,8 +521,9 @@ module mult_saxi_wr #(
.
EXTRA_WORDS
(
4
)
,
.
EXTRA_REG_ADDR
(
MULT_SAXI_STATUS_REG
)
)
status_generate_i
(
.
rst
(
rst
)
,
// input
.
clk
(
mclk
)
,
// input
.
rst
(
1'b0
)
,
//rst), // input
.
clk
(
mclk
)
,
// input
.
srst
(
mrst
)
,
// input
.
we
(
we_ctrl
&&
cmd_a
[
0
])
,
// input
.
wd
(
cmd_data
[
7
:
0
])
,
// input[7:0]
.
status
(
status_data
)
,
// input[128:0]
...
...
cmd_mux.v
View file @
b721ae66
...
...
@@ -61,7 +61,8 @@ module cmd_mux #(
)
(
input
axi_clk
,
input
mclk
,
input
rst
,
input
mrst
,
// @posedge mclk - sync reset
input
arst
,
// @posedge axi_clk - sync reset
// direct commands from AXI. No wait but for multi-cycle output and command sequencer (having higher priority)
input
[
AXI_WR_ADDR_BITS
-
1
:
0
]
pre_waddr
,
// AXI write address, before actual writes (to generate busy), valid@start_burst
input
start_wburst
,
// burst start - should generate ~ready (should be AND-ed with !busy internally)
...
...
@@ -114,10 +115,10 @@ module cmd_mux #(
assign
seq_length_rom_a
=
par_ad
[
NUM_CYCLES_LOW_BIT
+:
5
]
;
assign
ss
=
seq_length
[
3
]
;
always
@
(
posedge
axi_clk
or
posedge
rst
)
begin
if
(
rst
)
selected
<=
1'b0
;
always
@
(
posedge
axi_clk
)
begin
if
(
arst
)
selected
<=
1'b0
;
else
if
(
start_wburst
)
selected
<=
selected_w
;
if
(
rst
)
busy_r
<=
1'b0
;
if
(
arst
)
busy_r
<=
1'b0
;
else
busy_r
<=
!
fifo_half_empty
;
end
...
...
@@ -158,8 +159,8 @@ module cmd_mux #(
5'h1e
:
seq_length
<=
NUM_CYCLES_30
;
5'h1f
:
seq_length
<=
NUM_CYCLES_31
;
endcase
always
@
(
posedge
rst
or
posedge
mclk
)
begin
if
(
rst
)
seq_busy_r
<=
0
;
always
@
(
posedge
mclk
)
begin
if
(
m
rst
)
seq_busy_r
<=
0
;
else
begin
if
(
ad_stb
)
begin
case
(
seq_length
)
...
...
@@ -177,9 +178,9 @@ module cmd_mux #(
assign
can_start_w
=
ad_stb_r
?
ss
:
!
seq_busy_r
[
1
]
;
assign
start_axi_w
=
can_start_w
&&
~
cmdseq_full_r
&&
fifo_nempty
;
assign
start_w
=
can_start_w
&&
(
cmdseq_full_r
||
fifo_nempty
)
;
always
@
(
posedge
rst
or
posedge
mclk
)
begin
if
(
rst
)
ad_stb_r
<=
0
;
else
ad_stb_r
<=
start_w
;
always
@
(
posedge
mclk
)
begin
if
(
m
rst
)
ad_stb_r
<=
0
;
else
ad_stb_r
<=
start_w
;
end
always
@
(
posedge
mclk
)
begin
if
(
start_w
)
par_ad
<={
cmdseq_full_r
?
cseq_wdata_r
:
wdata_fifo_out
,{
(
16
-
AXI_WR_ADDR_BITS
)
{
1'b0
}},
cmdseq_full_r
?
cseq_waddr_r
:
waddr_fifo_out
};
...
...
@@ -188,8 +189,8 @@ module cmd_mux #(
assign
cseq_ackn
=
cseq_wr_en
&&
(
!
cmdseq_full_r
||
can_start_w
)
;
// cmddseq_full has priority over axi, so (can_start_w && cmdseq_full_r)
always
@
(
posedge
rst
or
posedge
mclk
)
begin
if
(
rst
)
cmdseq_full_r
<=
0
;
always
@
(
posedge
mclk
)
begin
if
(
m
rst
)
cmdseq_full_r
<=
0
;
else
cmdseq_full_r
<=
cseq_ackn
||
(
cmdseq_full_r
&&
!
can_start_w
)
;
end
always
@
(
posedge
mclk
)
begin
...
...
@@ -204,7 +205,9 @@ module cmd_mux #(
.
DATA_WIDTH
(
AXI_WR_ADDR_BITS
+
32
)
,
.
DATA_DEPTH
(
4
)
)
fifo_cross_clocks_i
(
.
rst
(
rst
)
,
// input
.
rst
(
1'b0
)
,
// input
.
rrst
(
mrst
)
,
// input
.
wrst
(
arst
)
,
// input
.
rclk
(
mclk
)
,
// input
.
wclk
(
axi_clk
)
,
// input
.
we
(
wr_en
&&
selected
)
,
// input
...
...
cmd_readback.v
View file @
b721ae66
...
...
@@ -30,7 +30,8 @@ module cmd_readback#(
parameter
CONTROL_RBACK_ADDR
=
'h0000
,
// AXI write address of control write registers
parameter
CONTROL_RBACK_ADDR_MASK
=
'h3800
// AXI write address of control registers
)(
input
rst
,
input
mrst
,
// @posedge mclk - sync reset
input
arst
,
// @posedge axi_clk - sync reset
input
mclk
,
input
axi_clk
,
input
[
AXI_WR_ADDR_BITS
-
1
:
0
]
par_waddr
,
// parallel address
...
...
@@ -71,11 +72,11 @@ module cmd_readback#(
assign
axird_selected
=
select_r
;
always
@
(
posedge
rst
or
posedge
axi_clk
)
begin
if
(
rst
)
axird_regen
<=
0
;
else
axird_regen
<=
axird_ren
;
always
@
(
posedge
axi_clk
)
begin
if
(
a
rst
)
axird_regen
<=
0
;
else
axird_regen
<=
axird_ren
;
if
(
rst
)
select_r
<=
0
;
if
(
arst
)
select_r
<=
0
;
else
if
(
axird_start_burst
)
select_r
<=
select_w
;
end
...
...
@@ -85,9 +86,9 @@ module cmd_readback#(
select_d
<=
select_r
;
end
always
@
(
posedge
rst
or
posedge
mclk
)
begin
if
(
rst
)
we
<=
0
;
else
we
<=
we_w
;
always
@
(
posedge
mclk
)
begin
if
(
m
rst
)
we
<=
0
;
else
we
<=
we_w
;
end
always
@
(
posedge
mclk
)
begin
if
(
we_w
)
wdata
<=
par_data
;
...
...
compressor_jp/cmprs_cmd_decode.v
View file @
b721ae66
...
...
@@ -132,16 +132,16 @@ module cmprs_cmd_decode#(
parameter
CMPRS_CSAT_CB_BITS
=
10
,
// number of bits in blue scale field in color saturation word
parameter
CMPRS_CSAT_CR
=
12
,
// bit # of number of red scale field in color saturation word
parameter
CMPRS_CSAT_CR_BITS
=
10
,
// number of bits in red scale field in color saturation word
parameter
CMPRS_CORING_BITS
=
3
,
// number of bits in coring mode
parameter
CMPRS_CORING_BITS
=
3
// number of bits in coring mode
parameter
CMPRS_STUFFER_NEG
=
1
// stuffer runs @ negedge xclk2x
//
parameter CMPRS_STUFFER_NEG = 1 // stuffer runs @ negedge xclk2x
)(
input
rst
,
//
input rst,
input
xclk
,
// global clock input, compressor single clock rate
// input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
input
mclk
,
// global system/memory clock
input
mrst
,
// @posedge mclk, sync reset
input
ctrl_we
,
// input - @mclk control register write enable
input
format_we
,
// input - @mclk write number of tiles and left margin
input
color_sat_we
,
// input - @mclk write color saturation values
...
...
@@ -236,57 +236,57 @@ module cmprs_cmd_decode#(
wire
frame_start_xclk
;
assign
cmprs_en_mclk
=
cmprs_en_mclk_r
;
always
@
(
posedge
rst
or
posedge
mclk
)
begin
if
(
rst
)
ctrl_we_r
<=
0
;
else
ctrl_we_r
<=
ctrl_we
;
always
@
(
posedge
mclk
)
begin
if
(
m
rst
)
ctrl_we_r
<=
0
;
else
ctrl_we_r
<=
ctrl_we
;
if
(
rst
)
format_we_r
<=
0
;
else
format_we_r
<=
format_we
;
if
(
m
rst
)
format_we_r
<=
0
;
else
format_we_r
<=
format_we
;
if
(
rst
)
color_sat_we_r
<=
0
;
else
color_sat_we_r
<=
color_sat_we
;
if
(
m
rst
)
color_sat_we_r
<=
0
;
else
color_sat_we_r
<=
color_sat_we
;
if
(
rst
)
coring_we_r
<=
0
;
else
coring_we_r
<=
coring_we
;
if
(
m
rst
)
coring_we_r
<=
0
;
else
coring_we_r
<=
coring_we
;
if
(
rst
)
di_r
<=
0
;
if
(
mrst
)
di_r
<=
0
;
else
if
(
ctrl_we
||
format_we
||
color_sat_we
||
coring_we
)
di_r
<=
di
[
30
:
0
]
;
if
(
rst
)
cmprs_en_mclk_r
<=
0
;
if
(
mrst
)
cmprs_en_mclk_r
<=
0
;
else
if
(
ctrl_we_r
&&
di_r
[
CMPRS_CBIT_RUN
])
cmprs_en_mclk_r
<=
(
di_r
[
CMPRS_CBIT_RUN
-
1
-:
CMPRS_CBIT_RUN_BITS
]
!=
CMPRS_CBIT_RUN_RST
)
;
if
(
rst
)
cmprs_run_mclk
<=
0
;
if
(
mrst
)
cmprs_run_mclk
<=
0
;
else
if
(
ctrl_we_r
&&
di_r
[
CMPRS_CBIT_RUN
])
cmprs_run_mclk
<=
(
di_r
[
CMPRS_CBIT_RUN
-
1
-:
CMPRS_CBIT_RUN_BITS
]
==
CMPRS_CBIT_RUN_ENABLE
)
;
if
(
rst
)
cmprs_standalone
<=
0
;
if
(
mrst
)
cmprs_standalone
<=
0
;