Commit f92c85e2 authored by Andrey Filippov's avatar Andrey Filippov

typo fix in multiple files

parent 060dc308
......@@ -21,7 +21,7 @@
`timescale 1ns/1ps
module cmprs_afi_mux#(
parameter CMPRS_AFIMUX_ADDR= 'h140, //TODO: assign valid adderss
parameter CMPRS_AFIMUX_ADDR= 'h140, //TODO: assign valid address
parameter CMPRS_AFIMUX_MASK= 'h3f0,
parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel)
parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets
......@@ -29,7 +29,7 @@ module cmprs_afi_mux#(
parameter CMPRS_AFIMUX_STATUS_CNTRL= 'h4, // .. 'h7
parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf
parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid adderss
parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid address
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
......@@ -45,7 +45,7 @@ module cmprs_afi_mux#(
input status_start, // Acknowledge of the first status packet byte (address)
// compressor channel 0
output fifo_rst0, // reset FIFO (set read adderss to write, reset count)
output fifo_rst0, // reset FIFO (set read address to write, reset count)
output fifo_ren0,
input [63:0] fifo_rdata0,
// input fifo_eof0, // single rclk pulse signalling EOF
......@@ -54,7 +54,7 @@ module cmprs_afi_mux#(
input [7:0] fifo_count0, // number of 32-byte chunks in FIFO
// compressor channel 1
output fifo_rst1, // reset FIFO (set read adderss to write, reset count)
output fifo_rst1, // reset FIFO (set read address to write, reset count)
output fifo_ren1,
input [63:0] fifo_rdata1,
// input fifo_eof1, // single rclk pulse signalling EOF
......@@ -63,7 +63,7 @@ module cmprs_afi_mux#(
input [7:0] fifo_count1, // number of 32-byte chunks in FIFO
// compressor channel 2
output fifo_rst2, // reset FIFO (set read adderss to write, reset count)
output fifo_rst2, // reset FIFO (set read address to write, reset count)
output fifo_ren2,
input [63:0] fifo_rdata2,
// input fifo_eof2, // single rclk pulse signalling EOF
......@@ -72,7 +72,7 @@ module cmprs_afi_mux#(
input [7:0] fifo_count2, // number of 32-byte chunks in FIFO
// compressor channel 3
output fifo_rst3, // reset FIFO (set read adderss to write, reset count)
output fifo_rst3, // reset FIFO (set read address to write, reset count)
output fifo_ren3,
input [63:0] fifo_rdata3,
// input fifo_eof3, // single rclk pulse signalling EOF
......
......@@ -99,7 +99,7 @@ module cmprs_afi_mux_ptr(
(busy[2] && !busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
if (busy[0] && !busy[1]) begin // first clock of busy
// calculate full adderss for current AXI burst (valid 1 clk after busy)
// calculate full address for current AXI burst (valid 1 clk after busy)
chunk_addr <= ptr_ram[ptr_wa] + sa_len_ram[sa_len_ra];
chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc;
end
......
......@@ -25,7 +25,7 @@
`timescale 1ns/1ps
module cmprs_afi_mux_status #(
parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid adderss
parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid address
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3
) (
......
......@@ -32,7 +32,7 @@ module cmprs_out_fifo(
// rclk domain
input rclk,
input rst_fifo, // reset FIFO (set read adderss to write, reset count)
input rst_fifo, // reset FIFO (set read address to write, reset count)
input ren,
output [63:0] rdata,
output eof, // single rclk pulse signalling EOF
......
......@@ -21,7 +21,7 @@
`timescale 1ns/1ps
module jp_channel#(
parameter CMPRS_ADDR= 'h120, //TODO: assign valid adderss
parameter CMPRS_ADDR= 'h120, //TODO: assign valid address
parameter CMPRS_MASK= 'h3f8,
parameter CMPRS_CONTROL_REG= 0,
parameter CMPRS_STATUS_CNTRL= 1,
......@@ -29,7 +29,7 @@ module jp_channel#(
parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_TABLES= 6, // 6..7
parameter CMPRS_STATUS_REG_ADDR= 'h10, //TODO: assign valid adderss
parameter CMPRS_STATUS_REG_ADDR= 'h10, //TODO: assign valid address
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over)
......@@ -147,7 +147,7 @@ module jp_channel#(
// Output interface to the AFI mux
input hclk,
input fifo_rst, // reset FIFO (set read adderss to write, reset count)
input fifo_rst, // reset FIFO (set read address to write, reset count)
input fifo_ren,
output [63:0] fifo_rdata,
output fifo_eof, // single rclk pulse signalling EOF
......@@ -876,7 +876,7 @@ module jp_channel#(
.eof_written_wclk (eof_written_xclk2xn), // output - AFI had transferred frame data to the system memory
.rclk (hclk), // input - AFI clock
// AFI clock domain
.rst_fifo (fifo_rst), // input - reset FIFO (set read adderss to write, reset count)
.rst_fifo (fifo_rst), // input - reset FIFO (set read address to write, reset count)
.ren (fifo_ren), // input - fifo read from AFI channel mux
.rdata (fifo_rdata), // output[63:0] - data to AFI channel mux (latency == 2 from fifo_ren)
.eof (fifo_eof), // output single hclk pulse signalling EOF
......
......@@ -53,7 +53,7 @@
endfunction
function [31:0] func_encode_cmd;
input [14:0] addr; // 15-bit row/column adderss
input [14:0] addr; // 15-bit row/column address
input [2:0] bank; // bank (here OK to be any)
input [2:0] rcw; // RAS/CAS/WE, positive logic
input odt_en; // enable ODT
......@@ -69,7 +69,7 @@
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column adderss
addr[14:0], // 15-bit row/column address
bank [2:0], // bank
rcw[2:0], // RAS/CAS/WE
odt_en, // enable ODT
......
......@@ -22,7 +22,7 @@
task membridge_setup;
input [28:0] len64; // number of 64-bit words to transfer
input [28:0] width64; // frame width in 64-bit words
input [28:0] start64; // relative start adderss of the transfer (set to 0 when writing lo_addr64)
input [28:0] start64; // relative start address of the transfer (set to 0 when writing lo_addr64)
input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
input [28:0] size64; // size of the system memory range in 64-bit words
......
......@@ -165,7 +165,7 @@ module cmd_encod_linear_rd #(
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]?
row:
{{ADDRESS_NUMBER-COLADDR_NUMBER{1'b0}},col[COLADDR_NUMBER-4:0],3'b0}, // [14:0] addr; // 15-bit row/column adderss
{{ADDRESS_NUMBER-COLADDR_NUMBER{1'b0}},col[COLADDR_NUMBER-4:0],3'b0}, // [14:0] addr; // 15-bit row/column address
bank[2:0], // bank (here OK to be any)
full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic
1'b0, // odt_en; // enable ODT
......@@ -201,7 +201,7 @@ module cmd_encod_linear_rd #(
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column address
bank[2:0], // bank (here OK to be any)
3'b0, // RAS/CAS/WE, positive logic
odt_en, // enable ODT
......@@ -219,7 +219,7 @@ module cmd_encod_linear_rd #(
endfunction
function [31:0] func_encode_cmd;
input [14:0] addr; // 15-bit row/column adderss
input [14:0] addr; // 15-bit row/column address
input [2:0] bank; // bank (here OK to be any)
input [2:0] rcw; // RAS/CAS/WE, positive logic
input odt_en; // enable ODT
......@@ -235,7 +235,7 @@ module cmd_encod_linear_rd #(
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column adderss
addr[14:0], // 15-bit row/column address
bank [2:0], // bank
rcw[2:0], // RAS/CAS/WE
odt_en, // enable ODT
......
......@@ -233,7 +233,7 @@ module cmd_encod_linear_wr #(
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]?
row:
{{ADDRESS_NUMBER-COLADDR_NUMBER{1'b0}},col[COLADDR_NUMBER-4:0],3'b0}, // [14:0] addr; // 15-bit row/column adderss
{{ADDRESS_NUMBER-COLADDR_NUMBER{1'b0}},col[COLADDR_NUMBER-4:0],3'b0}, // [14:0] addr; // 15-bit row/column address
bank[2:0], // bank (here OK to be any)
full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic
rom_r[ENC_ODT], // odt_en; // enable ODT
......
......@@ -265,7 +265,7 @@ module cmd_encod_tiled_32_rd #(
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
enable_autopre & ~rom_r[ENC_NOP],
{col_bank[COLADDR_NUMBER-1:4],~rom_r[ENC_NOP]},
3'b0}, // [14:0] addr; // 15-bit row/column adderss
3'b0}, // [14:0] addr; // 15-bit row/column address
rom_cmd[1]?
row_col_bank[2:0]:
col_bank[2:0], //
......
......@@ -274,7 +274,7 @@ module cmd_encod_tiled_32_wr #(
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
enable_autopre & rom_r[ENC_AUTOPRE], // all writes w/o NOP are first writes, autoprecharge only fro the second ones
{col_bank[COLADDR_NUMBER-1:4], rom_r[ENC_AUTOPRE]},
3'b0}, // [14:0] addr; // 15-bit row/column adderss
3'b0}, // [14:0] addr; // 15-bit row/column address
rom_cmd[1]?
row_col_bank[2:0]:
col_bank[2:0], //
......
......@@ -260,7 +260,7 @@ module cmd_encod_tiled_rd #(
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
enable_autopre,
col_bank[COLADDR_NUMBER-1:3],
3'b0}, // [14:0] addr; // 15-bit row/column adderss
3'b0}, // [14:0] addr; // 15-bit row/column address
rom_cmd[1]?
row_col_bank[2:0]:
col_bank[2:0], //
......
......@@ -269,7 +269,7 @@ module cmd_encod_tiled_wr #(
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
enable_autopre,
col_bank[COLADDR_NUMBER-1:3],
3'b0}, // [14:0] addr; // 15-bit row/column adderss
3'b0}, // [14:0] addr; // 15-bit row/column address
rom_cmd[1]?
row_col_bank[2:0]:
col_bank[2:0], //
......
......@@ -142,7 +142,7 @@ module mcntrl_linear_rw #(
wire single_frame_w; // pulse
wire rst_frame_num_w;
reg single_frame_r; // pulse
reg [1:0] rst_frame_num_r; // reset frame number/next start adderss
reg [1:0] rst_frame_num_r; // reset frame number/next start address
reg frame_en; // enable next frame
reg busy_r;
......
......@@ -152,7 +152,7 @@ module mcntrl_tiled_rw#(
wire single_frame_w; // pulse
wire rst_frame_num_w;
reg single_frame_r; // pulse
reg [1:0] rst_frame_num_r; // reset frame number/next start adderss
reg [1:0] rst_frame_num_r; // reset frame number/next start address
reg frame_en; // enable next frame
reg busy_r;
......
......@@ -154,7 +154,7 @@ module ddrc_sequencer #(
wire rst=rst_in;
// wire [ 9:0] next_cmd_addr;
reg [ 9:0] cmd_addr; // command word adderss
reg [ 9:0] cmd_addr; // command word address
reg cmd_sel;
reg [ 2:0] cmd_busy; // bit 0 - immediately,
wire phy_cmd_nop; // decoded command (ras, cas, we) was NOP
......
......@@ -236,7 +236,7 @@ module mcontr_sequencer #(
wire rst=rst_in;
// wire [ 9:0] next_cmd_addr;
reg [ 9:0] cmd_addr; // command word adderss
reg [ 9:0] cmd_addr; // command word address
reg cmd_sel;
reg [ 2:0] cmd_busy; // bit 0 - immediately,
wire phy_cmd_nop; // decoded command (ras, cas, we) was NOP
......
......@@ -29,7 +29,7 @@
// TODO: see what depends on pclk and if can be made independent of the sensor clock.
module camsync393 #(
parameter CAMSYNC_ADDR = 'h160, //TODO: assign valid adderss
parameter CAMSYNC_ADDR = 'h160, //TODO: assign valid address
parameter CAMSYNC_MASK = 'h3f8,
parameter CAMSYNC_MODE = 'h0,
parameter CAMSYNC_TRIG_SRC = 'h4, // setup trigger source
......@@ -39,6 +39,7 @@ module camsync393 #(
parameter CAMSYNC_SNDEN_BIT = 'h1, // enable writing ts_snd_en
parameter CAMSYNC_EXTERNAL_BIT = 'h3, // enable writing ts_external
parameter CAMSYNC_TRIGGERED_BIT = 'h5, // enable writing ts_external
parameter CAMSYNC_PRE_MAGIC = 6'b110100,
parameter CAMSYNC_POST_MAGIC = 6'b001101
......@@ -51,6 +52,7 @@ module camsync393 #(
// 0 - mode: [1:0] +2 - reset ts_snd_en, +3 - set ts_snd_en - enable sending timestamp over sync line
// [3:2] +8 - reset ts_external, +'hc - set ts_external:
// 1 - use external timestamp, if available. 0 - always use local ts
// [5:4] +'h20 - reset triggered mode (free running sensor), +'h30 - set sensor triggered mode
// 4 - source of trigger (10 bit pairs, LSB - level to trigger, MSB - use this bit). All 0 - internal trigger
// in internal mode output has variable delay from the internal trigger (relative to sensor trigger)
......@@ -64,7 +66,8 @@ module camsync393 #(
// 256>=d - repetitive trigger
input pclk, // pixel clock (global)
input triggered_mode, // use triggered mode (0 - sensor is free-running)
output triggered_mode, // use triggered mode (0 - sensor is free-running) @mclk
// trigrst is already combined with cb_sensor_trigger
input trigrst, // single-clock start of frame input (resets trigger output) posedge
input [9:0] gpio_in, // 12-bit input from GPIO pins -> 10 bit
output [9:0] gpio_out,// 12-bit output to GPIO pins
......@@ -105,7 +108,7 @@ module camsync393 #(
// TODO: change to control bit fields
reg ts_snd_en; // enable sending timestamp over sync line
reg ts_external; // 1 - use external timestamp, if available. 0 - always use local ts
reg triggered_mode_r;
// TODO: remove next 2
wire [31:0] ts_snd_sec; // [31:0] timestamp seconds to be sent over the sync line
wire [19:0] ts_snd_usec; // [19:0] timestamp microseconds to be sent over the sync line
......@@ -209,6 +212,7 @@ module camsync393 #(
wire local_got; // received local timestamp (@ posedge mclk)
wire local_got_pclk; // local_got reclocked @pclk
reg ts_snap; // make a timestamp pulse single @(posedge pclk)
wire trigrst_or_freerun; // trigger reset (2pclk, vacts) or sensor is in fre running mode
//! in testmode GPIO[9] and GPIO[8] use internal signals instead of the outsync:
//! bit 11 - same as TRIGGER output to the sensor (signal to the sensor may be disabled externally)
......@@ -239,12 +243,16 @@ module camsync393 #(
assign set_trig_dst_w = cmd_we && (cmd_a == CAMSYNC_TRIG_DST);
assign set_trig_period_w = cmd_we && (cmd_a == CAMSYNC_TRIG_PERIOD);
assign pre_input_use = {cmd_data[19],cmd_data[17],cmd_data[15],cmd_data[13],cmd_data[11],cmd_data[9],cmd_data[7],cmd_data[5],cmd_data[3],cmd_data[1]};
assign pre_input_pattern = {cmd_data[18],cmd_data[16],cmd_data[14],cmd_data[12],cmd_data[10],cmd_data[8],cmd_data[6],cmd_data[4],cmd_data[2],cmd_data[0]};
assign pre_input_pattern = {cmd_data[18],cmd_data[16],cmd_data[14],cmd_data[12],cmd_data[10],cmd_data[8],cmd_data[6],cmd_data[4],cmd_data[2],cmd_data[0]};
assign triggered_mode = triggered_mode_r;
assign trigrst_or_freerun = trigrst || !triggered_mode_pclk;
always @(posedge mclk) begin
if (set_mode_reg_w) begin
if (cmd_data[CAMSYNC_SNDEN_BIT]) ts_snd_en <= cmd_data[CAMSYNC_SNDEN_BIT - 1];
if (cmd_data[CAMSYNC_EXTERNAL_BIT]) ts_external <= cmd_data[CAMSYNC_EXTERNAL_BIT - 1];
if (cmd_data[CAMSYNC_SNDEN_BIT]) ts_snd_en <= cmd_data[CAMSYNC_SNDEN_BIT - 1];
if (cmd_data[CAMSYNC_EXTERNAL_BIT]) ts_external <= cmd_data[CAMSYNC_EXTERNAL_BIT - 1];
if (cmd_data[CAMSYNC_TRIGGERED_BIT]) triggered_mode_r <= cmd_data[CAMSYNC_TRIGGERED_BIT - 1];
end
if (set_trig_src_w) begin
input_use <= pre_input_use;
......@@ -314,9 +322,9 @@ module camsync393 #(
always @ (posedge rst or posedge pclk) begin
if (rst) dly_cntr_run <= 0;
else dly_cntr_run <= triggered_mode && (start_dly || (dly_cntr_run && (dly_cntr[31:0]!=0)));
else dly_cntr_run <= triggered_mode_pclk && (start_dly || (dly_cntr_run && (dly_cntr[31:0]!=0)));
if (rst) trigger_r <= 0;
else trigger_r <= trigrst?1'b0:(trigger1_r ^ trigger_r);
else trigger_r <= trigrst_or_freerun ? 1'b0 : (trigger1_r ^ trigger_r);
end
......@@ -332,18 +340,17 @@ module camsync393 #(
/// if the trigger pulses continue to come.
assign pre_rcv_error= (sr_rcv_first[31:26]!=CAMSYNC_PRE_MAGIC) || (sr_rcv_second[5:0]!=CAMSYNC_POST_MAGIC);
// FD i_trigger (.C(pclk),.D(trigrst?1'b0:(trigger1_r ^ trigger)), .Q(trigger)); // for simulator to be happy
always @ (posedge pclk) begin
if (trigrst) overdue <= 1'b0;
else if (trigger1_r) overdue <= trigger;
if (trigrst_or_freerun) overdue <= 1'b0;
else if (trigger1_r) overdue <= trigger;
triggered_mode_pclk<= triggered_mode;
triggered_mode_pclk<= triggered_mode_r;
bit_length_short[7:0] <= bit_length[7:0]-bit_length_plus1[7:2]-1; // 3/4 of the duration
trigger_condition <= (((gpio_in[9:0] ^ input_pattern[9:0]) & input_use[9:0]) == 10'b0);
trigger_condition_d <= trigger_condition;
if (!triggered_mode || (trigger_condition !=trigger_condition_d)) trigger_filter_cntr <= {1'b0,bit_length[7:2]};
if (!triggered_mode_pclk || (trigger_condition !=trigger_condition_d)) trigger_filter_cntr <= {1'b0,bit_length[7:2]};
else if (!trigger_filter_cntr[6]) trigger_filter_cntr<=trigger_filter_cntr-1;
if (input_use_intern) trigger_condition_filtered <= 1'b0;
......
......@@ -48,7 +48,7 @@
// [13:12] - 3 - run seq, 2 - stop seq , 1,0 - no change to run state
module cmd_frame_sequencer#(
parameter CMDFRAMESEQ_ADDR= 'h160, //TODO: assign valid adderss
parameter CMDFRAMESEQ_ADDR= 'h160, //TODO: assign valid address
parameter CMDFRAMESEQ_MASK= 'h3e0,
parameter AXI_WR_ADDR_BITS = 14,
parameter CMDFRAMESEQ_DEPTH = 64, // 32/64/128
......
......@@ -29,8 +29,8 @@ module table_ad_transmit#(
input clk, // posedge mclk
input a_not_d_in, // address/not data input (valid @ we)
input we, // write address/data (single cycle) with at least 5 inactive between
input [31:0] din, // 32 bit data to send or 8-bit channel select concatenated with 24-bit byte adderss (@we)
output [ 7:0] ser_d, // 8-bit adderss/data to be sent to submodules that have table write port(s)
input [31:0] din, // 32 bit data to send or 8-bit channel select concatenated with 24-bit byte address (@we)
output [ 7:0] ser_d, // 8-bit address/data to be sent to submodules that have table write port(s)
output reg a_not_d, // sending adderass / not data - valid during all bytes
output reg [NUM_CHANNELS-1:0] chn_en // sending address or data
);
......
......@@ -550,7 +550,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
WINDOW_HEIGHT, // input [15:0] window_height; // 16 bit (only 14 are used here)
WINDOW_X0, // input [15:0] window_left;
WINDOW_Y0, // input [15:0] window_top;
0, // input [28:0] start64; // relative start adderss of the transfer (set to 0 when writing lo_addr64)
0, // input [28:0] start64; // relative start address of the transfer (set to 0 when writing lo_addr64)
AFI_LO_ADDR64, // input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words
0); // input continue; // 0 start from start64, 1 - continue from where it was
......@@ -569,7 +569,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
WINDOW_HEIGHT, // input [15:0] window_height; // 16 bit (only 14 are used here)
WINDOW_X0, // input [15:0] window_left;
WINDOW_Y0, // input [15:0] window_top;
0, // input [28:0] start64; // relative start adderss of the transfer (set to 0 when writing lo_addr64)
0, // input [28:0] start64; // relative start address of the transfer (set to 0 when writing lo_addr64)
AFI_LO_ADDR64, // input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words
0); // input continue; // 0 start from start64, 1 - continue from where it was
......@@ -583,7 +583,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
WINDOW_HEIGHT, // input [15:0] window_height; // 16 bit (only 14 are used here)
WINDOW_X0, // input [15:0] window_left;
WINDOW_Y0, // input [15:0] window_top;
0, // input [28:0] start64; // relative start adderss of the transfer (set to 0 when writing lo_addr64)
0, // input [28:0] start64; // relative start address of the transfer (set to 0 when writing lo_addr64)
AFI_LO_ADDR64, // input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words
0); // input continue; // 0 start from start64, 1 - continue from where it was
......@@ -1442,7 +1442,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
input [15:0] window_height; // 16 bit (only 14 are used here)
input [15:0] window_left;
input [15:0] window_top;
input [28:0] start64; // relative start adderss of the transfer (set to 0 when writing lo_addr64)
input [28:0] start64; // relative start address of the transfer (set to 0 when writing lo_addr64)
input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
input [28:0] size64; // size of the system memory range in 64-bit words
input continue; // 0 start from start64, 1 - continue from where it was
......
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