Skip to content

X
x393
Commit cadd05c1 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

Increase command adderss space, modified address map to fit sesnor/compressor related registers

parent d42644e2
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 184 additions and 137 deletions
axi/cmprs_afi_mux.v
View file @ cadd05c1
......@@ -22,7 +22,7 @@
module cmprs_afi_mux#(
parameter CMPRS_AFIMUX_ADDR= 'h140, //TODO: assign valid address
parameter CMPRS_AFIMUX_MASK= 'h3f0,
parameter CMPRS_AFIMUX_MASK= 'h7f0,
parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel)
parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets
parameter CMPRS_AFIMUX_MODE= 'h2, // per-channel select - which register to return as status
......
axi/histogram_saxi.v
View file @ cadd05c1
......@@ -25,7 +25,7 @@
module histogram_saxi#(
parameter HIST_SAXI_ADDR = 'h380, // need to modify addresses and masks to fit into overall command range
parameter HIST_SAXI_ADDR_MASK = 'h3f0,
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_ADDR = 'h390,
parameter HIST_SAXI_MODE_WIDTH = 8,
parameter HIST_SAXI_EN = 0,
......@@ -33,7 +33,7 @@ module histogram_saxi#(
parameter HIST_CONFIRM_WRITE = 2, // wait write confirmation for each block
parameter HIST_SAXI_AWCACHE = 4'h3, //..7 cache mode (4 bits, default 4'h3)
parameter HIST_SAXI_MODE_ADDR_MASK = 'h3ff,
parameter HIST_SAXI_MODE_ADDR_MASK = 'h7ff,
// parameter HIST_SAXI_STATUS_REG = 'h34,
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
)(
......@@ -233,7 +233,7 @@ module histogram_saxi#(
assign saxi_bready = 1'b1; // always ready
assign saxi_wlast = &wburst_cntr;
assign saxi_wid[5:0] = {attrib_chn,attrib_color};
assign saxi_wid[5:0] = {attrib_chn,attrib_color}; // TODO: Verify they match FIFO output (otherwise save them in FIFO too) block_start waits for FIFO?
assign saxi_wstrb = 4'hf; // All bytes
......
axi/membridge.v
View file @ cadd05c1
......@@ -22,7 +22,7 @@
//`define MEMBRIDGE_DEBUG_READ 1
module membridge#(
parameter MEMBRIDGE_ADDR= 'h200,
parameter MEMBRIDGE_MASK= 'h3f0,
parameter MEMBRIDGE_MASK= 'h7f0,
parameter MEMBRIDGE_CTRL= 'h0, // bit 0 - enable, bits[2:1]: 11 - start(continue), 01 - start and reset address
parameter MEMBRIDGE_STATUS_CNTRL= 'h1,
parameter MEMBRIDGE_LO_ADDR64= 'h2, // low address of the system memory, in 64-bit words (<<3 to get byte address)
......
axi/mult_saxi_wr.v
View file @ cadd05c1
......@@ -32,8 +32,8 @@ module mult_saxi_wr #(
parameter MULT_SAXI_BSLOG1 = 4,
parameter MULT_SAXI_BSLOG2 = 4,
parameter MULT_SAXI_BSLOG3 = 4,
parameter MULT_SAXI_MASK = 'h3f8, // 4 address/length pairs. In bytes, but lower bits are set to 0?
parameter MULT_SAXI_CNTRL_MASK = 'h3fe, // mode and status - 2 locations
parameter MULT_SAXI_MASK = 'h7f8, // 4 address/length pairs. In bytes, but lower bits are set to 0?
parameter MULT_SAXI_CNTRL_MASK = 'h7fe, // mode and status - 2 locations
parameter HIST_SAXI_AWCACHE = 4'h3, //..7 cache mode (4 bits, default 4'h3)
parameter MULT_SAXI_ADV_WR = 4, // number of clock cycles before end of write to genearte adv_wr_done
parameter MULT_SAXI_ADV_RD = 3 // number of clock cycles before end of write to genearte adv_wr_done
......
cmd_mux.v
View file @ cadd05c1
......@@ -22,25 +22,42 @@
module cmd_mux #(
parameter AXI_WR_ADDR_BITS= 14,
parameter CONTROL_ADDR = 'h2000, // AXI write address of control write registers
parameter CONTROL_ADDR_MASK = 'h3c00, // AXI write address of control registers
parameter NUM_CYCLES_LOW_BIT= 6, // decode addresses [NUM_CYCLES_LOW_BIT+:4] into command a/d length
parameter NUM_CYCLES_00 = 9, // single-cycle
parameter NUM_CYCLES_01 = 2, // 2-cycle
parameter NUM_CYCLES_02 = 3, // 3-cycle
parameter NUM_CYCLES_03 = 4, // 4-cycle
parameter NUM_CYCLES_04 = 5, // 5-cycle
parameter NUM_CYCLES_05 = 6, // 6-cycle
parameter NUM_CYCLES_06 = 6, //
parameter NUM_CYCLES_07 = 6, //
parameter NUM_CYCLES_08 = 6, //
parameter CONTROL_ADDR = 'h0000, // AXI write address of control write registers
parameter CONTROL_ADDR_MASK = 'h3800, // AXI write address of control registers
parameter NUM_CYCLES_LOW_BIT= 6, // decode addresses [NUM_CYCLES_LOW_BIT+:5] into command a/d length
parameter NUM_CYCLES_00 = 2, // 2-cycle 000.003f
parameter NUM_CYCLES_01 = 4, // 4-cycle 040.007f
parameter NUM_CYCLES_02 = 3, // 3-cycle 080.00bf
parameter NUM_CYCLES_03 = 3, // 3-cycle 0c0.00ff
parameter NUM_CYCLES_04 = 6, // 6-cycle 100.013f
parameter NUM_CYCLES_05 = 6, // 6-cycle 140.017f
parameter NUM_CYCLES_06 = 4, // 4-cycle 180.01bf
parameter NUM_CYCLES_07 = 4, // 4-cycle 1c0.01ff
parameter NUM_CYCLES_08 = 6, // 6-cycle 200.023f
parameter NUM_CYCLES_09 = 6, //
parameter NUM_CYCLES_10 = 6, //
parameter NUM_CYCLES_11 = 6, //
parameter NUM_CYCLES_12 = 6, //
parameter NUM_CYCLES_13 = 6, //
parameter NUM_CYCLES_14 = 6, //
parameter NUM_CYCLES_15 = 6 //
parameter NUM_CYCLES_13 = 5, // 5-cycle - not yet used
parameter NUM_CYCLES_14 = 6, // 6-cycle - not yet used
parameter NUM_CYCLES_15 = 9, // single-cycle
parameter NUM_CYCLES_16 = 6, //
parameter NUM_CYCLES_17 = 6, //
parameter NUM_CYCLES_18 = 6, //
parameter NUM_CYCLES_19 = 6, //
parameter NUM_CYCLES_20 = 6, //
parameter NUM_CYCLES_21 = 6, //
parameter NUM_CYCLES_22 = 6, //
parameter NUM_CYCLES_23 = 6, //
parameter NUM_CYCLES_24 = 6, //
parameter NUM_CYCLES_25 = 6, //
parameter NUM_CYCLES_26 = 6, //
parameter NUM_CYCLES_27 = 6, //
parameter NUM_CYCLES_28 = 6, //
parameter NUM_CYCLES_29 = 6, //
parameter NUM_CYCLES_30 = 6, //
parameter NUM_CYCLES_31 = 6 //
) (
input axi_clk,
input mclk,
......@@ -77,7 +94,7 @@ module cmd_mux #(
reg [31:0] cseq_wdata_r; // registered command data from the sequencer
reg [3:0] seq_length; // encoded ROM output - number of cycles in command sequence, [3] - single cycle
reg [4:0] seq_busy_r; // shift register loaded by decoded seq_length
wire [3:0] seq_length_rom_a; // address range used to determine command length
wire [4:0] seq_length_rom_a; // address range used to determine command length
wire can_start_w; // can start command cycle (either from sequencer or from AXI)
wire start_w; // start cycle
......@@ -94,7 +111,7 @@ module cmd_mux #(
assign byte_ad=par_ad[7:0]; // byte-wide address/data (AL-AH-DB0-DB1-DB2-DB3)
assign ad_stb=ad_stb_r; // low address output strobe (and parallel A/D)
assign seq_length_rom_a=par_ad[NUM_CYCLES_LOW_BIT+:4];
assign seq_length_rom_a=par_ad[NUM_CYCLES_LOW_BIT+:5];
assign ss= seq_length[3];
always @ (posedge axi_clk or posedge rst) begin
......@@ -108,22 +125,38 @@ module cmd_mux #(
// always @ (seq_length_rom_a) begin
always @*
case (seq_length_rom_a) // just temporary - fill out later
4'h0:seq_length <= NUM_CYCLES_00;
4'h1:seq_length <= NUM_CYCLES_01;
4'h2:seq_length <= NUM_CYCLES_02;
4'h3:seq_length <= NUM_CYCLES_03;
4'h4:seq_length <= NUM_CYCLES_04;
4'h5:seq_length <= NUM_CYCLES_05;
4'h6:seq_length <= NUM_CYCLES_06;
4'h7:seq_length <= NUM_CYCLES_07;
4'h8:seq_length <= NUM_CYCLES_08;
4'h9:seq_length <= NUM_CYCLES_09;
4'ha:seq_length <= NUM_CYCLES_10;
4'hb:seq_length <= NUM_CYCLES_11;
4'hc:seq_length <= NUM_CYCLES_12;
4'hd:seq_length <= NUM_CYCLES_13;
4'he:seq_length <= NUM_CYCLES_14;
4'hf:seq_length <= NUM_CYCLES_15;
5'h00:seq_length <= NUM_CYCLES_00;
5'h01:seq_length <= NUM_CYCLES_01;
5'h02:seq_length <= NUM_CYCLES_02;
5'h03:seq_length <= NUM_CYCLES_03;
5'h04:seq_length <= NUM_CYCLES_04;
5'h05:seq_length <= NUM_CYCLES_05;
5'h06:seq_length <= NUM_CYCLES_06;
5'h07:seq_length <= NUM_CYCLES_07;
5'h08:seq_length <= NUM_CYCLES_08;
5'h09:seq_length <= NUM_CYCLES_09;
5'h0a:seq_length <= NUM_CYCLES_10;
5'h0b:seq_length <= NUM_CYCLES_11;
5'h0c:seq_length <= NUM_CYCLES_12;
5'h0d:seq_length <= NUM_CYCLES_13;
5'h0e:seq_length <= NUM_CYCLES_14;
5'h0f:seq_length <= NUM_CYCLES_15;
5'h10:seq_length <= NUM_CYCLES_16;
5'h11:seq_length <= NUM_CYCLES_17;
5'h12:seq_length <= NUM_CYCLES_18;
5'h13:seq_length <= NUM_CYCLES_19;
5'h14:seq_length <= NUM_CYCLES_20;
5'h15:seq_length <= NUM_CYCLES_21;
5'h16:seq_length <= NUM_CYCLES_22;
5'h17:seq_length <= NUM_CYCLES_23;
5'h18:seq_length <= NUM_CYCLES_24;
5'h19:seq_length <= NUM_CYCLES_25;
5'h1a:seq_length <= NUM_CYCLES_26;
5'h1b:seq_length <= NUM_CYCLES_27;
5'h1c:seq_length <= NUM_CYCLES_28;
5'h1d:seq_length <= NUM_CYCLES_29;
5'h1e:seq_length <= NUM_CYCLES_30;
5'h1f:seq_length <= NUM_CYCLES_31;
endcase
always @ (posedge rst or posedge mclk) begin
if (rst) seq_busy_r<=0;
......
cmd_readback.v
View file @ cadd05c1
......@@ -23,12 +23,12 @@
module cmd_readback#(
parameter AXI_WR_ADDR_BITS= 14,
parameter AXI_RD_ADDR_BITS = 14,
parameter CONTROL_RBACK_DEPTH= 10, //
parameter CONTROL_RBACK_DEPTH= 11, // 10 - 1xbram, 11 - 2xbram
parameter CONTROL_ADDR = 'h2000, // AXI write address of control write registers
parameter CONTROL_ADDR_MASK = 'h3c00, // AXI write address of control registers
parameter CONTROL_RBACK_ADDR = 'h2000, // AXI write address of control write registers
parameter CONTROL_RBACK_ADDR_MASK = 'h3c00 // AXI write address of control registers
parameter CONTROL_ADDR = 'h0000, // AXI write address of control write registers
parameter CONTROL_ADDR_MASK = 'h3800, // AXI write address of control registers
parameter CONTROL_RBACK_ADDR = 'h0000, // AXI write address of control write registers
parameter CONTROL_RBACK_ADDR_MASK = 'h3800 // AXI write address of control registers
)(
input rst,
input mclk,
......
compressor_jp/jp_channel.v
View file @ cadd05c1
......@@ -22,7 +22,7 @@
module jp_channel#(
parameter CMPRS_ADDR= 'h120, //TODO: assign valid address
parameter CMPRS_MASK= 'h3f8,
parameter CMPRS_MASK= 'h7f8,
parameter CMPRS_CONTROL_REG= 0,
parameter CMPRS_STATUS_CNTRL= 1,
parameter CMPRS_FORMAT= 2,
......
includes/x393_parameters.vh
View file @ cadd05c1
This diff is collapsed.
includes/x393_tasks_mcntrl_buffers.vh
View file @ cadd05c1
......@@ -142,7 +142,6 @@ task read_block_buf_chn; // S uppressThisWarning VEditor : may be unused
begin
case (chn)
0: start_addr=MCONTR_BUF0_RD_ADDR + (page << 8);
// 1: start_addr=MCONTR_BUF1_RD_ADDR + (page << 8);
2: start_addr=MCONTR_BUF2_RD_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_RD_ADDR + (page << 8);
4: start_addr=MCONTR_BUF4_RD_ADDR + (page << 8);
......
logger/event_logger.v
View file @ cadd05c1
......@@ -24,8 +24,8 @@ module event_logger#(
parameter LOGGER_ADDR = 'h1a0, //TODO: assign valid address
parameter LOGGER_STATUS = 'h1a2, //TODO: assign valid address (just 1 location)
parameter LOGGER_STATUS_REG_ADDR = 'h0b, //TODO: assign valid address (just 1 location)
parameter LOGGER_MASK = 'h3fe,
parameter LOGGER_STATUS_MASK = 'h3ff,
parameter LOGGER_MASK = 'h7fe,
parameter LOGGER_STATUS_MASK = 'h7ff,
parameter LOGGER_PAGE_IMU = 0, // 'h00..'h1f - overlaps with period/duration/halfperiod/config?
parameter LOGGER_PAGE_GPS = 1, // 'h20..'h3f
......
memctrl/mcntrl393.v
View file @ cadd05c1
......@@ -22,19 +22,19 @@
`include "system_defines.vh"
module mcntrl393 #(
// AXI
parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy
parameter MCONTR_CMD_WR_ADDR = 'h0000, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h0400, // AXI read address from buffer 0 (PS sequence, memory read)
parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
// parameter MCONTR_BUF1_RD_ADDR = 'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read) // not used - replaced with membridge
// parameter MCONTR_BUF1_WR_ADDR = 'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write) // not used - replaced with membridge
parameter MCONTR_BUF2_RD_ADDR = 'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
parameter MCONTR_BUF2_WR_ADDR = 'h0c00, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
parameter MCONTR_BUF3_RD_ADDR = 'h1000, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h1000, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h1400, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF4_WR_ADDR = 'h1400, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy
parameter MCONTR_CMD_WR_ADDR = 'h0c00, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h1000, // AXI read address from buffer 0 (PS sequence, memory read) (was 'h400)
parameter MCONTR_BUF0_WR_ADDR = 'h1000, // AXI write address to buffer 0 (PS sequence, memory write) (was 'h400)
// MCONTR_BUF[2-4]_* - temporary, will be removed in the futire
parameter MCONTR_BUF2_RD_ADDR = 'h1400, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
parameter MCONTR_BUF2_WR_ADDR = 'h1400, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
parameter MCONTR_BUF3_RD_ADDR = 'h1800, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h1800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h1c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF4_WR_ADDR = 'h1c00, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
parameter AXI_WR_ADDR_BITS = 14,
parameter AXI_RD_ADDR_BITS = 14,
......@@ -44,7 +44,7 @@ module mcntrl393 #(
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h3f0, // address mask to generate sequencer channel/run
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
// 0x1020 - DLY_SET // 0 bits -set pre-programmed delays
// 0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs
// 0x1026..1027 - SDRST_ACT // 0 bits - enable/disable active-low reset signal to DDR3 memory
......@@ -59,7 +59,7 @@ module mcntrl393 #(
parameter MCONTR_PHY_0BIT_DLY_RST = 'hc, // enable/disable CKE signal to memory
//0x1030..1037 - 0-bit memory cotroller (set/reset)
parameter MCONTR_TOP_0BIT_ADDR = 'h030, // address to turn on/off memory controller features
parameter MCONTR_TOP_0BIT_ADDR_MASK = 'h3f8, // address mask to generate sequencer channel/run
parameter MCONTR_TOP_0BIT_ADDR_MASK = 'h7f8, // address mask to generate sequencer channel/run
// 0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller
// 0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh
// 0x1034..1037 - reserved
......@@ -68,10 +68,10 @@ module mcntrl393 #(
//0x1040..107f - 16-bit data
// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?
// parameter RUN_CHN_REL = 'h040, // address to set sequnecer channel and run (4 LSB-s - channel)
// parameter RUN_CHN_REL_MASK = 'h3f0, // address mask to generate sequencer channel/run
// parameter RUN_CHN_REL_MASK = 'h7f0, // address mask to generate sequencer channel/run
// 0x1050..1057: MCONTR_PHY16
parameter MCONTR_PHY_16BIT_ADDR = 'h050, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h3f8, // address mask to generate sequencer channel/run
parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h7f8, // address mask to generate sequencer channel/run
// 0x1050 - PATTERNS // 16 bits
// 0x1051 - PATTERNS_TRI // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
// 0x1052 - WBUF_DELAY // 4 bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
......@@ -85,10 +85,10 @@ module mcntrl393 #(
//0x1060..106f: arbiter priority data
parameter MCONTR_ARBIT_ADDR = 'h060, // Address to set channel priorities
parameter MCONTR_ARBIT_ADDR_MASK = 'h3f0, // Address mask to set channel priorities
parameter MCONTR_ARBIT_ADDR_MASK = 'h7f0, // Address mask to set channel priorities
//0x1070..1077 - 16-bit top memory controller:
parameter MCONTR_TOP_16BIT_ADDR = 'h070, // address to set mcontr top control registers
parameter MCONTR_TOP_16BIT_ADDR_MASK = 'h3f8, // address mask to set mcontr top control registers
parameter MCONTR_TOP_16BIT_ADDR_MASK = 'h7f8, // address mask to set mcontr top control registers
// 0x1070 - MCONTR_CHN_EN // 16 bits per-channel enable (want/need requests)
// 0x1071 - REFRESH_PERIOD // 8-bit refresh period
// 0x1072 - REFRESH_ADDRESS // 10 bits
......@@ -169,7 +169,7 @@ module mcntrl393 #(
parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over)
parameter MCNTRL_SCANLINE_CHN1_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MASK= 'h7f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
......@@ -194,7 +194,7 @@ module mcntrl393 #(
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN2_ADDR= 'h140,
parameter MCNTRL_TILED_CHN4_ADDR= 'h150,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MASK= 'h7f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
......@@ -676,8 +676,6 @@ module mcntrl393 #(
assign select_cmd0_w = ((axiwr_pre_awaddr ^ MCONTR_CMD_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf0rd_w = ((axird_pre_araddr ^ MCONTR_BUF0_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf0wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF0_WR_ADDR) & MCONTR_WR_MASK)==0;
// assign select_buf1rd_w = ((axird_pre_araddr ^ MCONTR_BUF1_RD_ADDR) & MCONTR_RD_MASK)==0; // not used - replaced with membridge
// assign select_buf1wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF1_WR_ADDR) & MCONTR_WR_MASK)==0; // not used - replaced with membridge
assign select_buf2rd_w = ((axird_pre_araddr ^ MCONTR_BUF2_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf2wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF2_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf3rd_w = ((axird_pre_araddr ^ MCONTR_BUF3_RD_ADDR) & MCONTR_RD_MASK)==0;
......
memctrl/mcntrl393_test01.v
View file @ cadd05c1
......@@ -22,7 +22,7 @@
module mcntrl393_test01#(
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h3f0,
parameter MCNTRL_TEST01_MASK= 'h7f0,
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_TEST01_CHN1_MODE= 'h2, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN1_STATUS_CNTRL= 'h3, // control status reporting for channel 5
......
memctrl/mcntrl_linear_rw.v
View file @ cadd05c1
......@@ -29,7 +29,7 @@ module mcntrl_linear_rw #(
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over)
parameter MCNTRL_SCANLINE_ADDR= 'h120,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MASK= 'h7f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
......
memctrl/mcntrl_tiled_rw.v
View file @ cadd05c1
......@@ -32,7 +32,7 @@ module mcntrl_tiled_rw#(
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over)
parameter MCNTRL_TILED_ADDR= 'h120,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MASK= 'h7f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
......
memctrl/memctrl16.v
View file @ cadd05c1
......@@ -28,7 +28,7 @@ module memctrl16 #(
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h3f0, // address mask to generate sequencer channel/run
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
// 0x1020 - DLY_SET // 0 bits -set pre-programmed delays
// 0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs
// 0x1026..1027 - SDRST_ACT // 0 bits - enable/disable active-low reset signal to DDR3 memory
......@@ -43,7 +43,7 @@ module memctrl16 #(
parameter MCONTR_PHY_0BIT_DLY_RST = 'hc, // enable/disable CKE signal to memory
//0x1030..1037 - 0-bit memory cotroller (set/reset)
parameter MCONTR_TOP_0BIT_ADDR = 'h030, // address to turn on/off memory controller features
parameter MCONTR_TOP_0BIT_ADDR_MASK = 'h3f8, // address mask to generate sequencer channel/run
parameter MCONTR_TOP_0BIT_ADDR_MASK = 'h7f8, // address mask to generate sequencer channel/run
// 0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller
// 0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh
// 0x1034..1037 - reserved
......@@ -52,10 +52,10 @@ module memctrl16 #(
//0x1040..107f - 16-bit data
// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?
// parameter RUN_CHN_REL = 'h040, // address to set sequnecer channel and run (4 LSB-s - channel)
// parameter RUN_CHN_REL_MASK = 'h3f0, // address mask to generate sequencer channel/run
// parameter RUN_CHN_REL_MASK = 'h7f0, // address mask to generate sequencer channel/run
// 0x1050..1057: MCONTR_PHY16
parameter MCONTR_PHY_16BIT_ADDR = 'h050, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h3f8, // address mask to generate sequencer channel/run
parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h7f8, // address mask to generate sequencer channel/run
// 0x1050 - PATTERNS // 16 bits
// 0x1051 - PATTERNS_TRI // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
// 0x1052 - WBUF_DELAY // 4 bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
......@@ -69,10 +69,10 @@ module memctrl16 #(
//0x1060..106f: arbiter priority data
parameter MCONTR_ARBIT_ADDR = 'h060, // Address to set channel priorities
parameter MCONTR_ARBIT_ADDR_MASK = 'h3f0, // Address mask to set channel priorities
parameter MCONTR_ARBIT_ADDR_MASK = 'h7f0, // Address mask to set channel priorities
//0x1070..1077 - 16-bit top memory controller:
parameter MCONTR_TOP_16BIT_ADDR = 'h070, // address to set mcontr top control registers
parameter MCONTR_TOP_16BIT_ADDR_MASK = 'h3f8, // address mask to set mcontr top control registers
parameter MCONTR_TOP_16BIT_ADDR_MASK = 'h7f8, // address mask to set mcontr top control registers
// 0x1070 - MCONTR_CHN_EN // 16 bits per-channel enable (want/need requests)
// 0x1071 - REFRESH_PERIOD // 8-bit refresh period
// 0x1072 - REFRESH_ADDRESS // 10 bits
......
memctrl/phy/mcontr_sequencer.v
View file @ cadd05c1
......@@ -31,7 +31,7 @@ module mcontr_sequencer #(
// 0x10e0 - set delay for MMCM
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h3f0, // address mask to generate sequencer channel/run
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
// 0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs
// 0x1026..1027 - SDRST_ACT // 0 bits - enable/disable active-low reset signal to DDR3 memory
// 0x1028..1029 - CKE_EN // 0 bits - enable/disable CKE signal to memory
......@@ -48,10 +48,10 @@ module mcontr_sequencer #(
//0x1040..107f - 16-bit data
// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?
// parameter RUN_CHN_REL = 'h040, // address to set sequnecer channel and run (4 LSB-s - channel)
// parameter RUN_CHN_REL_MASK = 'h3f0, // address mask to generate sequencer channel/run
// parameter RUN_CHN_REL_MASK = 'h7f0, // address mask to generate sequencer channel/run
// 0x1050..1057: MCONTR_PHY16
parameter MCONTR_PHY_16BIT_ADDR = 'h050, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h3f8, // address mask to generate sequencer channel/run
parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h7f8, // address mask to generate sequencer channel/run
parameter MCONTR_PHY_16BIT_PATTERNS = 'h0, // set DQM and DQS patterns (16'h0055)
parameter MCONTR_PHY_16BIT_PATTERNS_TRI = 'h1, // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
parameter MCONTR_PHY_16BIT_WBUF_DELAY = 'h2, // 4? bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
......
py393/x393_mcntrl_buffers.py
View file @ cadd05c1
......@@ -217,7 +217,6 @@ class X393McntrlBuffers(object):
"""
start_addr=-1
if chn==0: start_addr=vrlg.MCONTR_BUF0_RD_ADDR + (page << 8)
# elif chn==1: start_addr=vrlg.MCONTR_BUF1_RD_ADDR + (page << 8)
elif chn==2: start_addr=vrlg.MCONTR_BUF2_RD_ADDR + (page << 8)
elif chn==3: start_addr=vrlg.MCONTR_BUF3_RD_ADDR + (page << 8)
elif chn==4: start_addr=vrlg.MCONTR_BUF4_RD_ADDR + (page << 8)
......
sensor/sens_gamma.v
View file @ cadd05c1
......@@ -24,7 +24,7 @@ module sens_gamma #(
parameter SENS_GAMMA_NUM_CHN = 3, // number of subchannels for his sensor ports (1..4)
parameter SENS_GAMMA_BUFFER = 0, // 1 - use "shadow" table for clean switching, 0 - single table per channel
parameter SENS_GAMMA_ADDR = 'h338,
parameter SENS_GAMMA_ADDR_MASK = 'h3fc,
parameter SENS_GAMMA_ADDR_MASK = 'h7fc,
parameter SENS_GAMMA_CTRL = 'h0,
parameter SENS_GAMMA_ADDR_DATA = 'h1, // bit 20 ==1 - table address, bit 20==0 - table data (18 bits)
parameter SENS_GAMMA_HEIGHT01 = 'h2, // bits [15:0] - height minus 1 of image 0, [31:16] - height-1 of image1
......
sensor/sens_histogram.v
View file @ cadd05c1
......@@ -23,7 +23,7 @@
module sens_histogram #(
parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter HISTOGRAM_ADDR = 'h33c,
parameter HISTOGRAM_ADDR_MASK = 'h3fe,
parameter HISTOGRAM_ADDR_MASK = 'h7fe,
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1 // 1.. 2^16, 0 - use HACT
)(
......
sensor/sens_parallel12.v
View file @ cadd05c1
......@@ -22,7 +22,7 @@
module sens_parallel12 #(
parameter SENSIO_ADDR = 'h330,
parameter SENSIO_ADDR_MASK = 'h3f8,
parameter SENSIO_ADDR_MASK = 'h7f8,
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
......
sensor/sensor_channel.v
View file @ cadd05c1
......@@ -32,7 +32,7 @@ module sensor_channel#(
// parameters defining address map
parameter SENSOR_CTRL_RADDR = 0, //'h300
parameter SENSOR_CTRL_ADDR_MASK = 'h3ff, //
parameter SENSOR_CTRL_ADDR_MASK = 'h7ff, //
// bits of the SENSOR mode register
parameter SENSOR_MODE_WIDTH = 9,
parameter SENSOR_HIST_EN_BIT = 0, // 0..3 1 - enable histogram modules, disable after processing the started frame
......@@ -40,13 +40,13 @@ module sensor_channel#(
parameter SENSOR_16BIT_BIT = 8, // 0 - 8 bpp mode, 1 - 16 bpp (bypass gamma). Gamma-processed data is still used for histograms
parameter SENSI2C_CTRL_RADDR = 2, // 302..'h303
parameter SENSI2C_CTRL_MASK = 'h3fe,
parameter SENSI2C_CTRL_MASK = 'h7fe,
// sensor_i2c_io relative control register addresses
parameter SENSI2C_CTRL = 'h0,
parameter SENSI2C_STATUS = 'h1,
parameter SENS_GAMMA_RADDR = 4,
parameter SENS_GAMMA_ADDR_MASK = 'h3fc,
parameter SENS_GAMMA_ADDR_MASK = 'h7fc,
// sens_gamma registers
parameter SENS_GAMMA_CTRL = 'h0,
parameter SENS_GAMMA_ADDR_DATA = 'h1, // bit 20 ==1 - table address, bit 20==0 - table data (18 bits)
......@@ -61,7 +61,7 @@ module sensor_channel#(
parameter SENS_GAMMA_MODE_TRIG = 5,
parameter SENSIO_RADDR = 8, //'h308 .. 'h30c
parameter SENSIO_ADDR_MASK = 'h3f8,
parameter SENSIO_ADDR_MASK = 'h7f8,
// sens_parallel12 registers
parameter SENSIO_CTRL = 'h0,
// SENSIO_CTRL register bits
......@@ -86,14 +86,14 @@ module sensor_channel#(
// sensor_i2c_io command/data write registers s (relative to SENSOR_BASE_ADDR)
parameter SENSI2C_ABS_RADDR = 'h10, // 'h310..'h31f
parameter SENSI2C_REL_RADDR = 'h20, // 'h320..'h32f
parameter SENSI2C_ADDR_MASK = 'h3f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
// sens_hist registers (relative to SENSOR_BASE_ADDR)
parameter HISTOGRAM_RADDR0 = 'h30, //
parameter HISTOGRAM_RADDR1 = 'h32, //
parameter HISTOGRAM_RADDR2 = 'h34, //
parameter HISTOGRAM_RADDR3 = 'h36, //
parameter HISTOGRAM_ADDR_MASK = 'h3fe, // for each channel
parameter HISTOGRAM_ADDR_MASK = 'h7fe, // for each channel
// sens_hist registers
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
......
sensor/sensor_i2c.v
View file @ cadd05c1
......@@ -23,9 +23,9 @@
module sensor_i2c#(
parameter SENSI2C_ABS_ADDR = 'h300,
parameter SENSI2C_REL_ADDR = 'h310,
parameter SENSI2C_ADDR_MASK = 'h3f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
parameter SENSI2C_CTRL_ADDR = 'h320,
parameter SENSI2C_CTRL_MASK = 'h3fe,
parameter SENSI2C_CTRL_MASK = 'h7fe,
parameter SENSI2C_CTRL = 'h0,
parameter SENSI2C_STATUS = 'h1,
parameter SENSI2C_STATUS_REG = 'h30
......
sensor/sensor_i2c_io.v
View file @ cadd05c1
......@@ -23,9 +23,9 @@
module sensor_i2c_io#(
parameter SENSI2C_ABS_ADDR = 'h300,
parameter SENSI2C_REL_ADDR = 'h310,
parameter SENSI2C_ADDR_MASK = 'h3f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
parameter SENSI2C_CTRL_ADDR = 'h320,
parameter SENSI2C_CTRL_MASK = 'h3fe,
parameter SENSI2C_CTRL_MASK = 'h7fe,
parameter SENSI2C_CTRL = 'h0,
parameter SENSI2C_STATUS = 'h1,
parameter SENSI2C_STATUS_REG = 'h30,
......
status_read.v
View file @ cadd05c1
......@@ -29,7 +29,7 @@
`timescale 1ns/1ps
module status_read#(
parameter STATUS_ADDR = 'h2400, // AXI write address of status read registers
parameter STATUS_ADDR = 'h0800, // AXI read address of status read registers
parameter STATUS_ADDR_MASK = 'h3c00, // AXI write address of status registers
parameter AXI_RD_ADDR_BITS = 14,
parameter integer STATUS_DEPTH= 8 // 256 cells, maybe just 16..64 are enough?
......
timing/camsync393.v
View file @ cadd05c1
......@@ -31,7 +31,7 @@
`undef GENERATE_TRIG_OVERDUE
module camsync393 #(
parameter CAMSYNC_ADDR = 'h160, //TODO: assign valid address
parameter CAMSYNC_MASK = 'h3f8,
parameter CAMSYNC_MASK = 'h7f8,
parameter CAMSYNC_MODE = 'h0,
parameter CAMSYNC_TRIG_SRC = 'h1, // setup trigger source
parameter CAMSYNC_TRIG_DST = 'h2, // setup trigger destination line(s)
......
timing/rtc393.v
View file @ cadd05c1
......@@ -27,7 +27,7 @@ module rtc393 #(
parameter RTC_STATUS_REG_ADDR = 7, // address where status can be read out (currently just sequence # and alternating bit)
parameter RTC_SEC_USEC_ADDR = 8, // address where seconds of the snapshot can be read (microseconds - next adderss)
parameter RTC_MASK = 'h3fc,
parameter RTC_MASK = 'h7fc,
parameter RTC_MHZ = 25, // RTC input clock in MHz (should be interger number)
parameter RTC_BITC_PREDIV = 5, // number of bits to generate 2 MHz pulses counting refclk
parameter RTC_SET_USEC = 0, // 20-bit number of microseconds
......
timing/timing393.v
View file @ cadd05c1
......@@ -26,8 +26,8 @@ module timing393 #(
parameter RTC_STATUS_REG_ADDR = 7, // address where status can be read out (currnelti just sequence # and alternating bit)
parameter RTC_SEC_USEC_ADDR = 8, // address where seconds of the snapshot can be read (microseconds - next adderss)
parameter CAMSYNC_MASK = 'h3f8,
parameter RTC_MASK= 'h3fc,
parameter CAMSYNC_MASK = 'h7f8,
parameter RTC_MASK = 'h7fc,
parameter CAMSYNC_MODE = 'h0,
parameter CAMSYNC_TRIG_SRC = 'h1, // setup trigger source
parameter CAMSYNC_TRIG_DST = 'h2, // setup trigger destination line(s)
......
util_modules/gpio393.v
View file @ cadd05c1
......@@ -51,7 +51,7 @@
// Enabled bits will be priority encoded (C - highest, software - lowest)
module gpio393 #(
parameter GPIO_ADDR = 'h180, //TODO: assign valid address
parameter GPIO_MASK = 'h3fe,
parameter GPIO_MASK = 'h7fe,
parameter GPIO_STATUS_REG_ADDR = 'ha, // address where status can be read out (10 GPIO inputs)
parameter integer GPIO_DRIVE = 12,
......
x393.v
View file @ cadd05c1
......@@ -182,8 +182,8 @@ module x393 #(
// parallel address/data - where higher bandwidth (single-cycle) is needed
wire [AXI_WR_ADDR_BITS-1:0] par_waddr; /// SuppressThisWarning VEditor ****** multiplexed address (full, parallel) to slave devices
wire [31:0] par_data; /// SuppressThisWarning VEditor ****** multiplexed data (full, parallel) to slave devices
wire [AXI_WR_ADDR_BITS-1:0] par_waddr;
wire [31:0] par_data;
......@@ -607,8 +607,6 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR),
.MCONTR_BUF0_RD_ADDR (MCONTR_BUF0_RD_ADDR),
.MCONTR_BUF0_WR_ADDR (MCONTR_BUF0_WR_ADDR),
// .MCONTR_BUF1_RD_ADDR (MCONTR_BUF1_RD_ADDR), // not used - replaced with membridge
// .MCONTR_BUF1_WR_ADDR (MCONTR_BUF1_WR_ADDR), // not used - replaced with membridge
.MCONTR_BUF2_RD_ADDR (MCONTR_BUF2_RD_ADDR),
.MCONTR_BUF2_WR_ADDR (MCONTR_BUF2_WR_ADDR),
.MCONTR_BUF3_RD_ADDR (MCONTR_BUF3_RD_ADDR),
......
x393_testbench01.tf
View file @ cadd05c1
......@@ -670,8 +670,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR),
.MCONTR_BUF0_RD_ADDR (MCONTR_BUF0_RD_ADDR),
.MCONTR_BUF0_WR_ADDR (MCONTR_BUF0_WR_ADDR),
// .MCONTR_BUF1_RD_ADDR (MCONTR_BUF1_RD_ADDR),
// .MCONTR_BUF1_WR_ADDR (MCONTR_BUF1_WR_ADDR),
.MCONTR_BUF2_RD_ADDR (MCONTR_BUF2_RD_ADDR),
.MCONTR_BUF2_WR_ADDR (MCONTR_BUF2_WR_ADDR),
.MCONTR_BUF3_RD_ADDR (MCONTR_BUF3_RD_ADDR),
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment