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Commit 7a0fa46b authored by Andrey Filippov's avatar Andrey Filippov
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Working on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp

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.project
View file @ 7a0fa46b
......@@ -62,77 +62,77 @@
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axi/membridge.v 0 → 100644
View file @ 7a0fa46b
This diff is collapsed.
axi_hp_clk.v 0 → 100644
View file @ 7a0fa46b
/*******************************************************************************
* Module: axi_hp_clk
* Date:2015-04-27
* Author: andrey
* Description: Generate global clock for axi_hp
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* axi_hp_clk.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* axi_hp_clk.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module axi_hp_clk#(
parameter CLKIN_PERIOD = 20, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_AXIHP = 6 // To get 150MHz for the reference clock
)(
input rst,
input clk_in,
output clk_axihp,
output locked_axihp
);
wire clkfb_axihp, clk_axihp_pre;
BUFG clk_axihp_i (.O(clk_axihp), .I(clk_axihp_pre));
pll_base #(
.CLKIN_PERIOD(CLKIN_PERIOD), // 20
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(CLKFBOUT_MULT_AXIHP), // 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
.CLKOUT0_DIVIDE(CLKFBOUT_DIV_AXIHP), // 6, // To get 300MHz for the reference clock
.REF_JITTER1(0.010),
.STARTUP_WAIT("FALSE")
) pll_base_i (
.clkin(clk_in), // input
.clkfbin(clkfb_axihp), // input
// .rst(rst), // input
.rst(rst), // input
.pwrdwn(1'b0), // input
.clkout0(clk_axihp_pre), // output
.clkout1(), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout(clkfb_axihp), // output
.locked(locked_axihp) // output
);
endmodule
includes/x393_parameters.vh
View file @ 7a0fa46b
......@@ -163,7 +163,7 @@
parameter NUM_CYCLES_05 = 6, // 6-cycle 140.017f
parameter NUM_CYCLES_06 = 4, // 4-cycle 180.01bf
parameter NUM_CYCLES_07 = 4, // 4-cycle 1c0.01ff
parameter NUM_CYCLES_08 = 6, //
parameter NUM_CYCLES_08 = 6, // 6-cycle 200.023f
parameter NUM_CYCLES_09 = 6, //
parameter NUM_CYCLES_10 = 6, //
parameter NUM_CYCLES_11 = 6, //
......@@ -245,6 +245,20 @@
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f, // status/readback register for channel 4
// membridge module parameters
parameter MEMBRIDGE_ADDR= 'h200,
parameter MEMBRIDGE_MASK= 'h3f0,
parameter MEMBRIDGE_CTRL= 'h0,
parameter MEMBRIDGE_STATUS_CNTRL= 'h1,
parameter MEMBRIDGE_RD_LOADDR64= 'h2,
parameter MEMBRIDGE_RD_RUNADDR64= 'h3,
parameter MEMBRIDGE_RD_LEN64= 'h5,
parameter MEMBRIDGE_WR_LOADDR64= 'h2,
parameter MEMBRIDGE_WR_RUNADDR64= 'h3,
parameter MEMBRIDGE_WR_LEN64= 'h5,
parameter MEMBRIDGE_STATUS_REG= 'h3b,
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
\ No newline at end of file
memctrl/mcntrl393.v
View file @ 7a0fa46b
......@@ -962,7 +962,8 @@ module mcntrl393 #(
.xfer_partial (lin_rw_chn1_partial), // output
.xfer_done (seq_done1), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page1_wr), // output
.xfer_page_rst_rd (xfer_reset_page1_rd) // output
.xfer_page_rst_rd (xfer_reset_page1_rd), // output
.cmd_wrmem () // output
);
mcntrl_linear_rw #(
......@@ -1009,7 +1010,8 @@ module mcntrl393 #(
.xfer_partial (lin_rw_chn3_partial), // output
.xfer_done (seq_done3), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page3_wr), // output
.xfer_page_rst_rd (xfer_reset_page3_rd) // output
.xfer_page_rst_rd (xfer_reset_page3_rd), // output
.cmd_wrmem () // output
);
mcntrl_tiled_rw #(
......
memctrl/mcntrl_linear_rw.v
View file @ 7a0fa46b
......@@ -77,7 +77,8 @@ module mcntrl_linear_rw #(
output xfer_partial, // partial tile (first of 2) , sequencer will not generate page_next at the end of block
input xfer_done, // transfer to/from the buffer finished
output xfer_page_rst_wr, // reset buffer internal page - at each frame start or when specifically reset (write to memory channel), @posedge
output xfer_page_rst_rd // reset buffer internal page - at each frame start or when specifically reset (read memory channel), @negedge
output xfer_page_rst_rd, // reset buffer internal page - at each frame start or when specifically reset (read memory channel), @negedge
output cmd_wrmem
);
localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
localparam MPY_WIDTH= NUM_RC_BURST_BITS; // 22
......@@ -129,7 +130,7 @@ module mcntrl_linear_rw #(
reg [2:0] page_cntr;
wire cmd_wrmem; //=MCNTRL_SCANLINE_WRITE_MODE; // 0: read from memory, 1:write to memory
// wire cmd_wrmem; //=MCNTRL_SCANLINE_WRITE_MODE; // 0: read from memory, 1:write to memory
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
reg busy_r;
reg want_r;
......@@ -247,7 +248,7 @@ module mcntrl_linear_rw #(
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished=line_unfinished_r[1];
assign chn_en = &mode_reg[1:0]; // enable requests by channle (continue ones in progress)
assign chn_en = &mode_reg[1:0]; // enable requests by channel (continue ones in progress)
assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
assign cmd_wrmem = mode_reg[2];// 0: read from memory, 1:write to memory
assign cmd_extra_pages = mode_reg[4:3]; // external module needs more than 1 page
......
util_modules/pulse_cross_clock.v 0 → 100644
View file @ 7a0fa46b
/*******************************************************************************
* Module: pulse_cross_clock
* Date:2015-04-27
* Author: andrey
* Description: Propagate a single pulse through clock domain boundary
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* pulse_cross_clock.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pulse_cross_clock.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module pulse_cross_clock(
input rst,
input src_clk,
input dst_clk,
input in_pulse, // single-cycle positive pulse
output out_pulse,
output busy
);
reg in_reg;
reg [2:0] out_reg;
assign out_pulse=out_reg[2];
assign busy=in_reg;
always @(posedge src_clk or posedge rst) begin
if (rst) in_reg <= 0;
else in_reg <= in_pulse || (in_reg && !out_reg[1]);
end
always @(posedge dst_clk or posedge rst) begin
if (rst) out_reg <= 0;
else out_reg <= {out_reg[0] & ~out_reg[1],out_reg[0],in_reg};
end
endmodule
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