Commit 7a0fa46b authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Working on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp

parent caf85bde

.project

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@@ -62,77 +62,77 @@ 
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axi/membridge.v

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axi_hp_clk.v

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/*******************************************************************************

 * Module: axi_hp_clk

 * Date:2015-04-27  

 * Author: andrey     

 * Description: Generate global clock for axi_hp

 *

 * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .

 * axi_hp_clk.v is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 *  axi_hp_clk.v is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *******************************************************************************/

`timescale 1ns/1ps



module  axi_hp_clk#(

    parameter CLKIN_PERIOD =        20, //ns >1.25, 600<Fvco<1200

    parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE

    parameter CLKFBOUT_DIV_AXIHP =  6   // To get 150MHz for the reference clock

    )(

    input   rst,

    input   clk_in,

    output  clk_axihp,

    output  locked_axihp

);

    wire  clkfb_axihp, clk_axihp_pre; 

    BUFG clk_axihp_i (.O(clk_axihp), .I(clk_axihp_pre));

    pll_base #(

        .CLKIN_PERIOD(CLKIN_PERIOD), // 20

        .BANDWIDTH("OPTIMIZED"),

        .CLKFBOUT_MULT(CLKFBOUT_MULT_AXIHP), // 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE

        .CLKOUT0_DIVIDE(CLKFBOUT_DIV_AXIHP), // 6, // To get 300MHz for the reference clock

        .REF_JITTER1(0.010),

        .STARTUP_WAIT("FALSE")

    ) pll_base_i (

        .clkin(clk_in), // input

        .clkfbin(clkfb_axihp), // input

//        .rst(rst), // input

        .rst(rst), // input

        .pwrdwn(1'b0), // input

        .clkout0(clk_axihp_pre), // output

        .clkout1(), // output

        .clkout2(), // output

        .clkout3(), // output

        .clkout4(), // output

        .clkout5(), // output

        .clkfbout(clkfb_axihp), // output

        .locked(locked_axihp) // output

    );





endmodule

includes/x393_parameters.vh

+15 −1
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@@ -163,7 +163,7 @@ 
    parameter NUM_CYCLES_05 =       6, // 6-cycle 140.017f

    parameter NUM_CYCLES_06 =       4, // 4-cycle 180.01bf

    parameter NUM_CYCLES_07 =       4, // 4-cycle 1c0.01ff

    parameter NUM_CYCLES_08 =       6, //

    parameter NUM_CYCLES_08 =       6, // 6-cycle 200.023f

    parameter NUM_CYCLES_09 =       6, //

    parameter NUM_CYCLES_10 =       6, //

    parameter NUM_CYCLES_11 =       6, //
@@ -245,6 +245,20 @@ 
    parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d,  // status/readback register for channel 3

    parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e,  // status/readback register for channel 4

    parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f,  // status/readback register for channel 4

    

// membridge module parameters    

    parameter MEMBRIDGE_ADDR=                     'h200,

    parameter MEMBRIDGE_MASK=                     'h3f0,

    parameter MEMBRIDGE_CTRL=                     'h0,

    parameter MEMBRIDGE_STATUS_CNTRL=             'h1,

    parameter MEMBRIDGE_RD_LOADDR64=              'h2,

    parameter MEMBRIDGE_RD_RUNADDR64=             'h3,

    parameter MEMBRIDGE_RD_LEN64=                 'h5,

    parameter MEMBRIDGE_WR_LOADDR64=              'h2,

    parameter MEMBRIDGE_WR_RUNADDR64=             'h3,

    parameter MEMBRIDGE_WR_LEN64=                 'h5,

    parameter MEMBRIDGE_STATUS_REG=               'h3b,

    

    parameter RSEL=                               1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)

    parameter WSEL=                               1'b0  // late/early WRITE commands (to adjust timing by 1 SDCLK period)

    
 No newline at end of file

memctrl/mcntrl393.v

+4 −2
Original line number Diff line number Diff line
@@ -962,7 +962,8 @@ module mcntrl393 #( 
        .xfer_partial     (lin_rw_chn1_partial), // output

        .xfer_done        (seq_done1), // input : sequence over

        .xfer_page_rst_wr (xfer_reset_page1_wr), // output

        .xfer_page_rst_rd (xfer_reset_page1_rd) // output

        .xfer_page_rst_rd (xfer_reset_page1_rd), // output

        .cmd_wrmem        () // output

    );



    mcntrl_linear_rw #(
@@ -1009,7 +1010,8 @@ module mcntrl393 #( 
        .xfer_partial     (lin_rw_chn3_partial), // output

        .xfer_done        (seq_done3), // input : sequence over

        .xfer_page_rst_wr (xfer_reset_page3_wr), // output

        .xfer_page_rst_rd (xfer_reset_page3_rd) // output

        .xfer_page_rst_rd (xfer_reset_page3_rd), // output

        .cmd_wrmem        () // output

    );

    

       mcntrl_tiled_rw #(