working on sensor channel

memctrl/phy/phy_top.v

@@ -295,7 +295,6 @@ BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) );
 //BUFH clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
 BUFG clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
 BUFG mclk_i (.O(mclk),.I(mclk_pre) );
-    /* Instance template for module mmcm_phase_cntr */
     mmcm_phase_cntr #(
         .PHASE_WIDTH         (PHASE_WIDTH),
         .CLKIN_PERIOD        (CLKIN_PERIOD),
@@ -333,7 +332,9 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
         .SS_MOD_PERIOD       (SS_MOD_PERIOD),
         .STARTUP_WAIT             ("FALSE")
     ) mmcm_phase_cntr_i (
-        .clkin               (clk_in), // input
+        .clkin1              (clk_in), // input
+        .clkin2              (1'b0), // input
+        .clkinsel            (1'b0), // input
         .clkfbin             (clk_fb), // input
 //        .rst                 (rst), // input
         .rst                 (rst_in), // input

sensor/pxd_clock.v

+/*******************************************************************************
+ * Module: pxd_clock
+ * Date:2015-05-16  
+ * Author: andrey     
+ * Description: pixel clock line input
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * pxd_clock.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  pxd_clock.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  pxd_clock #(
+    parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
+    parameter integer IDELAY_VALUE = 0,
+    parameter integer PXD_DRIVE = 12,
+    parameter PXD_IBUF_LOW_PWR = "TRUE",
+    parameter PXD_IOSTANDARD = "DEFAULT",
+    parameter PXD_SLEW = "SLOW",
+    parameter real REFCLK_FREQUENCY = 300.0,
+    parameter HIGH_PERFORMANCE_MODE = "FALSE"
+
+) (
+    inout        pxclk,          // I/O pad
+    input        pxclk_out,      // data to be sent out through the pad (normally not used)
+    input        pxclk_en,       // enable data output (normally not used)
+    output       pxclk_in,       // data output - delayed pad data
+    input        rst,            // reset
+    input        mclk,           // clock for setting delay values
+    input  [7:0] dly_data,       // delay value (3 LSB - fine delay) - @posedge mclk
+    input        set_idelay,     // mclk synchronous load idelay value
+    input        ld_idelay       // mclk synchronous set idealy value
+);
+    wire pxclk_iobuf;
+
+    iobuf #(
+        .DRIVE        (PXD_DRIVE),
+        .IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
+        .IOSTANDARD   (PXD_IOSTANDARD),
+        .SLEW         (PXD_SLEW)
+    ) iobuf_pxclk_i (
+        .O     (pxclk_iobuf), // output
+        .IO    (pxclk), // inout
+        .I     (pxclk_out), // input
+        .T     (!pxclk_en) // input
+    );
+
+    idelay_fine_pipe # (
+        .IODELAY_GRP           (IODELAY_GRP),
+        .DELAY_VALUE           (IDELAY_VALUE),
+        .REFCLK_FREQUENCY      (REFCLK_FREQUENCY),
+        .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
+    ) pxclk_dly_i(
+        .clk          (mclk),
+        .rst          (rst),
+        .set          (set_idelay),
+        .ld           (ld_idelay),
+        .delay        (dly_data[7:0]),
+        .data_in      (pxclk_iobuf),
+        .data_out     (pxclk_in)
+    );
+
+
+endmodule
+

sensor/pxd_single.v

+/*******************************************************************************
+ * Module: pxd_single
+ * Date:2015-05-15  
+ * Author: andrey     
+ * Description: pixel data line input
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * pxd_single.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  pxd_single.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  pxd_single#(
+    parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
+    parameter integer IDELAY_VALUE = 0,
+    parameter integer PXD_DRIVE = 12,
+    parameter PXD_IBUF_LOW_PWR = "TRUE",
+    parameter PXD_IOSTANDARD = "DEFAULT",
+    parameter PXD_SLEW = "SLOW",
+    parameter real REFCLK_FREQUENCY = 300.0,
+    parameter HIGH_PERFORMANCE_MODE = "FALSE"
+
+)(
+    inout        pxd,          // I/O pad
+    input        pxd_out,      // data to be sent out through the pad (normally not used)
+    input        pxd_en,       // enable data output (normally not used)
+    output       pxd_async,    // direct ouptut from the pad (maybe change to delayed?), does not depend on clocks - use for TDI
+    output       pxd_in,       // data output (@posedge ipclk?)
+    input        ipclk,        // restored clock from the sensor, phase-shifted
+    input        ipclk2x,      // restored clock from the sensor, phase-shifted, twice frequency
+    input        rst,          // reset
+    input        mclk,         // clock for setting delay values
+    input  [7:0] dly_data,     // delay value (3 LSB - fine delay) - @posedge mclk
+    input        set_idelay,   // mclk synchronous load idelay value
+    input        ld_idelay,    // mclk synchronous set idealy value
+    input  [1:0] quadrant       // select one of 4 90-degree shifts for the data (MT9P0xx) have VACT, HACT shifted from PXD
+);
+    wire pxd_iobuf;
+    wire pxd_delayed;
+    wire [3:0] dout;
+    reg        pxd_r;
+    
+    assign pxd_in=pxd_r;
+    assign pxd_async = pxd_iobuf;
+    always @ (posedge rst or posedge mclk) begin
+        if (rst) pxd_r <= 0;
+        else     pxd_r <= quadrant[1]?(quadrant[0]? dout[3]: dout[2]) : (quadrant[0]? dout[1]: dout[0]);
+    end
+    
+    iobuf #(
+        .DRIVE        (PXD_DRIVE),
+        .IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
+        .IOSTANDARD   (PXD_IOSTANDARD),
+        .SLEW         (PXD_SLEW)
+    ) iobuf_pxd_i (
+        .O     (pxd_iobuf), // output
+        .IO    (pxd), // inout
+        .I     (pxd_out), // input
+        .T     (!pxd_en) // input
+    );
+
+    idelay_fine_pipe # (
+        .IODELAY_GRP           (IODELAY_GRP),
+        .DELAY_VALUE           (IDELAY_VALUE),
+        .REFCLK_FREQUENCY      (REFCLK_FREQUENCY),
+        .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
+    ) pxd_dly_i(
+        .clk          (mclk),
+        .rst          (rst),
+        .set          (set_idelay),
+        .ld           (ld_idelay),
+        .delay        (dly_data[7:0]),
+        .data_in      (pxd_iobuf),
+        .data_out     (pxd_delayed)
+    );
+    
+    iserdes_mem #(
+        .DYN_CLKDIV_INV_EN("FALSE")
+    ) iserdes_pxd_i (
+        .iclk(ipclk2x),           // source-synchronous clock
+        .oclk(ipclk2x),           // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
+        .oclk_div(ipclk),         // oclk divided by 2, front aligned
+        .inv_clk_div(1'b0),       // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
+        .rst(rst),                // reset
+        .d_direct(1'b0),          // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
+        .ddly(pxd_delayed),       // serial input from idelay 
+        .dout(dout[3:0])          // parallel data out
+    );
+
+endmodule
+

sensor/sensor_i2c.v

@@ -218,7 +218,7 @@ module  sensor_i2c#(
     status_generate #(
         .STATUS_REG_ADDR(SENSI2C_STATUS_REG),
         .PAYLOAD_BITS(7) // STATUS_PAYLOAD_BITS)
-    ) status_generate_i (
+    ) status_generate_sens_i2c_i (
         .rst        (rst), // input
         .clk        (mclk), // input
         .we         (set_status_w), // input

sensor/sensor_i2c_io.v

@@ -101,6 +101,8 @@ module  sensor_i2c_io#(
         .I     (sda_out), // input
         .T     (!sda_en) // input
     );
+    mpullup i_scl_pullup(scl);
+    mpullup i_sda_pullup(sda);
 
 endmodule
 

wrap/mmcm_phase_cntr.v

@@ -71,7 +71,9 @@ module  mmcm_phase_cntr#(
     parameter STARTUP_WAIT  =         "FALSE"       // Delays "DONE" signal until MMCM is locked
 )
 (
-    input clkin,   // General clock input
+    input clkin1,   // General clock input
+    input clkin2,   // Alternative clock input
+    input clkinsel, // Clock input select
     input clkfbin,  // Feedback clock input
     input rst,      // asynchronous reset input
     input pwrdwn,   // power down input    
@@ -205,9 +207,9 @@ module  mmcm_phase_cntr#(
         .LOCKED         (locked), // output
         .PSDONE         (psdone), // output
         .CLKFBIN        (clkfbin), // input
-        .CLKIN1         (clkin), // input
-        .CLKIN2            (1'b0), // input
-        .CLKINSEL          (1'b1), // input Select CLKIN1
+        .CLKIN1         (clkin1), // input
+        .CLKIN2         (clkin2), // input
+        .CLKINSEL       (clkinsel), // input Select CLKIN1
         .DADDR             (7'b0), // Dynamic reconfiguration address (input[6:0])
         .DCLK              (1'b0), // Dynamic reconfiguration clock input
         .DEN               (1'b0), // Dynamic reconfiguration enable input

wrap/mpullup.v

+/*******************************************************************************
+ * Module: mpullup
+ * Date:2015-05-15  
+ * Author: andrey     
+ * Description: wrapper for PULLUP primitive
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * mpullup.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  mpullup.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  mpullup(
+	output O
+);
+    /* Instance template for module PULLUP */
+    PULLUP PULLUP_i (
+        .O(O) // output 
+    );
+
+
+endmodule
+

wrap/oddr_ds.v

@@ -38,7 +38,6 @@ module  oddr_ds # (
     output ndq
 );
     wire idq;
-    /* Instance template for module ODDR */
     ODDR #(
         .DDR_CLK_EDGE(DDR_CLK_EDGE),
         .INIT(INIT),
@@ -53,19 +52,6 @@ module  oddr_ds # (
         .S(set) // input 
     );
 
-    /* Instance template for module OBUFDS */
-/*    
-    OBUFDS #(
-        .CAPACITANCE(CAPACITANCE),
-        .IOSTANDARD(IOSTANDARD),
-        .SLEW(SLEW)
-    ) OBUFDS_i (
-        .O(dq), // output 
-        .OB(ndq), // output 
-        .I(idq) // input 
-    );
-*/
-    /* Instance template for module OBUFTDS */
     OBUFTDS #(
         .CAPACITANCE (CAPACITANCE),
         .IOSTANDARD  (IOSTANDARD),
@@ -74,7 +60,6 @@ module  oddr_ds # (
         .O  (dq), // output 
         .OB (ndq), // output 
         .I  (idq), // input 
-//        .T  (tin || rst) // input 
         .T  (tin) // input 
     );
 

wrap/oddr_ss.v

+/*******************************************************************************
+ * Module: oddr_ss
+ * Date:2015-05-16  
+ * Author: andrey     
+ * Description: Wrapper for ODDR+OBUFT
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * oddr_ss.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  oddr_ss.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  oddr_ss #(
+    parameter IOSTANDARD = "DEFAULT",
+    parameter SLEW = "SLOW",
+    parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
+    parameter INIT         = 1'b0,
+    parameter SRTYPE =       "SYNC"
+)(
+    input  clk,
+    input  ce,
+    input  rst,
+    input  set,
+    input [1:0] din,
+    input  tin, // tristate control
+    output dq
+);
+    wire idq;
+    ODDR #(
+        .DDR_CLK_EDGE(DDR_CLK_EDGE),
+        .INIT(INIT),
+        .SRTYPE(SRTYPE)
+    ) ODDR_i (
+        .Q(idq), // output 
+        .C(clk), // input 
+        .CE(ce), // input 
+        .D1(din[0]), // input 
+        .D2(din[1]), // input 
+        .R(rst), // input 
+        .S(set) // input 
+    );
+OBUFT #(
+    .IOSTANDARD(IOSTANDARD),
+    .SLEW(SLEW)
+) iobufs_i (
+    .O(dq),
+    .I(idq),
+    .T(tin));
+endmodule
+