Commit 93e8aa42 authored by Andrey Filippov's avatar Andrey Filippov

Fixed teplate error in the headers

parent 428053b8
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Writes comressor data from up to 4 channels to system memory over AXI_HP
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_afi_mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Maintain 4-channel chunk pointers (before AXI)
* Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_afi_mux_ptr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Maintain 4-channel chunk pointers for wrirte response
* Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_afi_mux_ptr_wresp.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -8,7 +8,7 @@
* and the same for the write response channel (confirmed written to the system
* memory
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_afi_mux_status.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: bi-directional bridge between system and video memory over axi_hp
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* membridge.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Generate global clock for axi_hp
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* axi_hp_clk.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Command multiplexer between AXI and frame-based command sequencer
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Store control register data and readback
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_readback.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -6,7 +6,7 @@
* during write, then subtracts them during read and provides to
* the after DCT to restore DC
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_buf_average.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Decode compressor command/modes, reclock some signals
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_cmd_decode.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Synchronizes memory channels (sensor and compressor)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_frame_sync.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -6,7 +6,7 @@
* stream matching selected color mode, accommodates for the buffer latency,
* acts as a pacemaker for the whole compressor (next stages are able to keep up).
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_macroblock_buf_iface.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Compressor output FIFO
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_out_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -6,7 +6,7 @@
* stream matching selected color mode, accommodates for the buffer latency,
* acts as a pacemaker for the whole compressor (next stages are able to keep up).
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_pixel_buf_iface.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Generate compressor status word
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_status.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Decode mode parameters, registered at pre-start of the macroblock
* data to color conversion module
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_tile_mode2_decode.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Decode tile/macroblocks parameters from compressor type
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmprs_tile_mode_decode.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Color processor for JPEG 4:2:0/JP4
* Updating from the earlier 2002-2010 version
*
* Copyright (c) 2002-2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2002-2015 Elphel, Inc.
* color_proc393.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Color space convert: combine differnt color modes
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* csconvert.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Color conversion for JP4 mode
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* csconvert_jp4.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Color conversion for JP4 differential
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* csconvert_jp4diff.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Convert JPEG monochrome
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* csconvert_mono.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -6,7 +6,7 @@
* Syncronizes dcc data with dma1 output, adds 16..31 16-bit zero words for Axis DMA
* Was not used in late NC353 camera (DMA channel used fro IMU logger)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* dcc_sync393.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Top module of JPEG/JP4 compressor channel
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* jp_channel.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Memory controller parameters that need adjustment during training
* Target ,pde
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_cur_params_target.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Local parameters for simulation of the x393
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_localparams.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Functions used to encode memory controller sequences
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_mcontr_encode_cmd.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Parameters for the x393 (simulation and implementation)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_parameters.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Simulation-specific parameters for the x393
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_simulation_parameters.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Simulation tasks for the x393 (low level)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks01.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Simulation tasks for the AXI_HP (AFI)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_afi.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Simulation tasks for software reading/writing (with test patterns)
* of the block buffers.
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_mcntrl_buffers.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Simulation tasks for software reading/writing (with test patterns)
* of the block buffers.
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_mcntrl_en_dis_priority.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Simulation tasks for programming I/O delays and other timing
* parameters in the memory controller
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_mcntrl_timing.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Simulation tasks for programming memory transaction
* sequences (controlles by PS)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_pio_sequences.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Simulation tasks for mcntrl_ps_pio module (launching software
* - programmed memory transaction sequences)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_ps_pio.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Simulation tasks for the x393 related to status
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* x393_status.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: 4-to-1 mux to cmbine memory sequences sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_4mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -6,7 +6,7 @@
* linear command encoders (cmd_encod_linear_rd and cmd_encod_linear_wr)
* Latency 1 clcok cycle
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_linear_mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Command sequencer generator for reading a sequential up to 1KB page
* single page access, bank and row will not be changed
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_linear_rd.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Combining 2 modules:cmd_encod_linear_rd and cmd_encod_linear_wr
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_linear_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Command sequencer generator for writing a sequential up to 1KB page
* single page access, bank and row will not be changed
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_linear_wr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -10,7 +10,7 @@
* just reading 32 bytes per row instead of the 16 - that eases timing
* Start burst should be even (LSB is ignored)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_tiled_32_rd.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Combines cmd_encod_tiled_32_rd and cmd_encod_tiled_32_wr modules
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_tiled_32_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -10,7 +10,7 @@
* just writing 32 bytes per row instead of the 16 - that eases timing
* Start burst should be even (LSB is ignored)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_tiled_32_wr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -6,7 +6,7 @@
* tiled command encoders (cmd_encod_tiled_rd and cmd_encod_tiled_wr)
* Latency 1 clcok cycle
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_tiled_mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -12,7 +12,7 @@
* if number of rows >=8, that port is ignored. If number of rows is less than
* 5 (less for slower clock) without keep_open_in tRTP may be not matched.
* Seems that actual tile heigt mod 8 should be only 0, 6 or7
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_tiled_rd.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Combines cmd_encod_tiled_rd and cmd_encod_tiled_wr modules
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_tiled_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -12,7 +12,7 @@
* if number of rows >=8, that port is ignored. If number of rows is less than
* 5 (less for slower clock) without keep_open_in tRTP may be not matched.
* Seems that actual tile heigt mod 8 should be only 0, 6 or7
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_encod_tiled_wr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Top level memory controller for 393 camera, includes channel buffers
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcntrl393.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Temporary module to interface mcntrl393 control signals
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcntrl393_test01.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Paged buffer for ddr3 controller read channel
* with address autoincrement. 32 bit external data.
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcntrl_1kx32r.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Paged buffer for ddr3 controller write channel
* with address autoincrement. 32 bit external data. Extends rd to regen
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcntrl_1kx32w.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Paged buffer for ddr3 controller read channel
* with address autoincrement. Variable width external data
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcntrl_buf_rd.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Paged buffer for ddr3 controller write channel
* with address autoincrement. 32 bit external data. Extends rd to regen
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcntrl_buf_wr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Organize paged R/W from DDR3 memory in scan-line order
* with window support
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcntrl_linear_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Read/write channels to DDR3 memory with software-programmable
* command sequence
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcntrl_ps_pio.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -7,7 +7,7 @@
* Tiles spreading over two different frames is not yet supported (needed for
* line-scan mode in JPEG (JP4 - OK)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcntrl_tiled_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: 16-channel memory controller
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* memctrl16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: 16-channel programmable DDR memory access scheduler
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* scheduler16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Histograms transfer to the system memory over S_AXI
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* histogram_saxi.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: pixel clock line input
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* pxd_clock.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: pixel data line input
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* pxd_single.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: table based piecewise-linear conversion of 16 -> 8 bit data
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* sens_gamma.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Calculates per-color histogram over the specified rectangular region
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* sens_histogram.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Readout multiplexer for 4 histogram modules
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* sens_histogram_mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Sensor interface with 12-bit for parallel bus
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* sens_parallel12.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Top module for a sensor channel
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* sensor_channel.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Cross clock boundary for sensor data, synchronize to HACT
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* sensor_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: i2c write-only sequencer to control image sensor
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* sensor_i2c.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: sensor_i2c with I/O pad elements
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* sensor_i2c_io.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Simplified model of AXI_HP read channel (64-bit only)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* simul_axi_hp_rd.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Simplified model of AXI_HP write channel (64-bit only)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* simul_axi_hp_wr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -12,7 +12,7 @@
* sequence number to use just 2-byte packets?
* TODO: add interrupt capabilities
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* status_read.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -6,7 +6,7 @@
* timestamps. Provides seconds (32 bit) and microseconds (20 bits),
* allows 24-bit accummulator-based fine adjustment
*
* Copyright (c) 2005-2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2005-2015 Elphel, Inc.
* rtc393.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -8,7 +8,7 @@
* Write, advance registers and readout events are supposed to have suffitient
* pauses between them
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* timestamp_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Take timestamp snapshot and send the ts message over the 8-bit bus
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* timestamp_snapshot.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: convert byte-parallel timestamp message to parallel sec, usec
* compatible to the x353 code (for NC353 camera)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* timestamp_to_parallel.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: convert legacy parallel timestamp data to a byte-parallel message
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* timestamp_to_serial.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: timestamp realrted functionality, extrenal synchronization
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* timing393.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: move data between clk and clk2x (nominally posedge aligned)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* clk_to_clk2x.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Expand command address/data from a byte-wide
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_deser.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Store/dispatch commands on per-frame basis
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_frame_sequencer.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Command multiplexer from 4 channels of frame-based command
* sequencers.
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* cmd_seq_mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -5,7 +5,7 @@
* Description: Simple two-register FIFO, no over/under check,
* behaves correctly only for correct inputs
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* fifo_2regs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Find index of the maximal of 16 values (masked), 4 cycle latency
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* index_max_16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Finds maximal of two masked values, registers result
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* masked_max_reg.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Registering data from channel buffer to memory controller
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcont_common_chnbuf_reg.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Registering data from channel buffer to memory controller
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcont_from_chnbuf_reg.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Registering data from memory controller to channel buffer
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* mcont_to_chnbuf_reg.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -8,7 +8,7 @@
* Lowering Fsrc reduces duty cycle proportianally as counter is in src_clk
* domain.
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* multipulse_cross_clock.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Priority select one of 16 inputs
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* pri1hot16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -6,7 +6,7 @@
* For same frequencies input pulses can have 1:3 duty cycle EXTRA_DLY=0
* and 1:5 for EXTRA_DLY=1
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* pulse_cross_clock.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: generate byte-serial status data
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* status_generate.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Routes status data from 16 sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* status_router16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: 2:1 status data router/mux
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* status_router2.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Routes status data from 4 sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* status_router4.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Routes status data from 8 sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* status_router8.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Receive tabble address/data sent by table_ad_transmit
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* table_ad_receive.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
......@@ -6,7 +6,7 @@
* In 32-bit mode we duty cycle is >= 6, so there will always be gaps in
* chn_stb[i] active
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* table_ad_transmit.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
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