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Commit 0cfebd24 authored by Andrey Filippov's avatar Andrey Filippov
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More editing, trying to run Xilinx tools

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.project
View file @ 0cfebd24
......@@ -62,77 +62,77 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150720133322322.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150722003723406.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150720133322322.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150722003207037.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150720133322322.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150722003723406.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150720133322322.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150722003207037.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150720133322322.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150722003207037.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150720133322322.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150722003723406.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150720130350146.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150722002329036.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150720133322322.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150722003723406.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150720130350146.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150722002329036.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150720133322322.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150722003723406.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150720130350146.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150722002329036.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150720133322322.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150722003723406.dcp</location>
</link>
<link>
<name>vivado_state/x393-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150720133322322.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150722003207037.dcp</location>
</link>
<link>
<name>vivado_state/x393-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150720133322322.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150722003723406.dcp</location>
</link>
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150720130350146.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150722002329036.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 0cfebd24
......@@ -4,6 +4,6 @@ VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=true
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
eclipse.preferences.version=1
axi/cmprs_afi_mux.v
View file @ 0cfebd24
......@@ -455,8 +455,8 @@ module cmprs_afi_mux#(
.chunk_ptr_ra (chunk_ptr_ra), // output[3:0] reg
.chunk_ptr_rd (chunk_ptr_rd[CMPRS_AFIMUX_WIDTH-1:0]) // input[25:0]
);
pulse_cross_clock sa_len_we_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_sa_len_w), .out_pulse(sa_len_we),.busy());
pulse_cross_clock en_we_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_en_w), .out_pulse(en_we), .busy());
pulse_cross_clock en_rst_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_rst_w), .out_pulse(en_rst),.busy());
pulse_cross_clock sa_len_we_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_sa_len_w), .out_pulse(sa_len_we),.busy());
pulse_cross_clock en_we_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_en_w), .out_pulse(en_we), .busy());
pulse_cross_clock en_rst_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_rst_w), .out_pulse(en_rst),.busy());
endmodule
axi/histogram_saxi.v
View file @ 0cfebd24
......@@ -421,7 +421,6 @@ module histogram_saxi#(
) fifo_same_clock_i (
.rst (1'b0), // input
.clk (aclk), // input
.sync_rst (arst), // input
.sync_rst (!en_aclk), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
......
compressor_jp/color_proc393.v deleted 100644 → 0
View file @ 210ed954
This diff is collapsed.
memctrl/cmd_encod_linear_rd.v
View file @ 0cfebd24
......@@ -180,5 +180,5 @@ module cmd_encod_linear_rd #(
// move to include?
`include "includes/x393_mcontr_encode_cmd.vh"
/endmodule
endmodule
memctrl/cmd_encod_tiled_wr.v
View file @ 0cfebd24
......@@ -298,7 +298,7 @@ module cmd_encod_tiled_wr #(
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
.mrst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input
......
memctrl/phy/byte_lane.v
View file @ 0cfebd24
......@@ -79,7 +79,8 @@ wire [9:0] decode_sel={
(dly_addr[3:0]==1)?1'b1:1'b0,
(dly_addr[3:0]==0)?1'b1:1'b0};
always @ (posedge clk_div or posedge rst) begin
//always @ (posedge clk_div or posedge rst) begin
always @ (posedge clk_div) begin
if (rst) begin
din_r <= 32'b0; din_dm_r<=0; din_dqs_r<=0; tin_dq_r<=4'hf; tin_dqs_r<=4'hf;
dly_data_r<=8'b0;set_r<=1'b0;
......@@ -114,11 +115,8 @@ generate
.dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
.dly_data(dly_data_r), // delay value (3 LSB - fine delay)
.din({din_r[i+24],din_r[i+16],din_r[i+8],din_r[i]}) , // parallel data to be sent out
// .din(din_r[4*i+3:4*i]) , // parallel data to be sent out
// .din(din_r[4*i+3-:4]) , // parallel data to be sent out
.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
.dout({dout[i+24],dout[i+16],dout[i+8],dout[i]}), // parallel data received from DDR3 memory
// .dout(dout[4*i+3:4*i]), // parallel data received from DDR3 memory
.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
.ld_odelay(ld_odly[i]), // clk_div synchronous set odealy value from loaded
.set_idelay(set_r), // clk_div synchronous load idelay value from dly_data
......
memctrl/phy/cmd_addr.v
View file @ 0cfebd24
......@@ -80,11 +80,11 @@ assign decode_addr24={
(dly_addr[4:3] == 2'h2)?decode_sel[7:0]:8'h0,
(dly_addr[4:3] == 2'h1)?decode_sel[7:0]:8'h0,
(dly_addr[4:3] == 2'h0)?decode_sel[7:0]:8'h0};
always @ (posedge clk_div or posedge rst) begin
//always @ (posedge clk_div or posedge rst) begin
always @ (posedge clk_div) begin
if (rst) begin
in_a_r <= 0; in_ba_r <= 6'b0;
in_we_r <= 2'h3; in_ras_r <= 2'h3; in_cas_r <= 2'h3; in_cke_r <= 2'h3; in_odt_r <= 2'h0;
// in_tri_r <= 2'h0; // or tri-state on reset?
in_tri_r <= 1'b1; // or tri-state on reset?
dly_data_r<=8'b0;set_r<=1'b0;
ld_dly_cmd <= 8'b0; ld_dly_addr <= 0;
......
memctrl/phy/ddrc_sequencer.v deleted 100644 → 0
View file @ 210ed954
This diff is collapsed.
memctrl/phy/phy_top.v
View file @ 0cfebd24
......@@ -125,7 +125,8 @@ module phy_top #(
// else rst <= 1'b0;
// end
always @(negedge clk_div) begin // Why is it @ negedge clk_div?
// always @(negedge clk_div) begin // Why is it @ negedge clk_div?
always @(posedge clk_div) begin // Why is it @ negedge clk_div?
if (mrst) rst <= 1'b1;
else rst <= 1'b0;
end
......
system_defines.vh
View file @ 0cfebd24
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
// will not use simultaneous reset in shift registers, just and input data with ~rst
`define SHREG_SEQUENTIAL_RESET 1
//`define MEMBRIDGE_DEBUG_READ 1
`define use200Mhz 1
`define USE_CMD_ENCOD_TILED_32_RD 1
......
timing/camsync393.v
View file @ 0cfebd24
......@@ -458,12 +458,12 @@ module camsync393 #(
end
`ifdef GENERATE_TRIG_OVERDUE
always @ (posedge rst or posedge mclk) begin
if (rst) trigger_r <= 0;
always @ (posedge mclk) begin
if (mrst) trigger_r <= 0;
else if (!triggered_mode) trigger_r <= 0;
else trigger_r <= ~frame_sync & (trig_r_mclk ^ trigger_r);
if (rst) overdue <= 0;
if (mrst) overdue <= 0;
else if (!triggered_mode) overdue <= 0;
else overdue <= ((overdue ^ trigger_r) & trig_r_mclk) ^ overdue;
......
util_modules/dly01_16.v
View file @ 0cfebd24
......@@ -28,11 +28,17 @@ module dly01_16(
output reg dout
);
reg [15:0] sr=0;
always @ (posedge rst or posedge clk) begin
`ifdef SHREG_SEQUENTIAL_RESET
always @ (posedge clk) begin
sr <= {sr[14:0], din & ~rst};
end
`else
// always @ (posedge rst or posedge clk) begin
always @ (posedge clk) begin
if (rst) sr <=0;
else sr <= {sr[14:0],din};
end
`endif
always @ (sr or dly) case (dly)
4'h0: dout <= sr[ 0];
4'h1: dout <= sr[ 1];
......
util_modules/gpio393.v
View file @ 0cfebd24
......@@ -87,8 +87,8 @@ module gpio393 #(
input [GPIO_N-1:0] dc, // port A data
input [GPIO_N-1:0] dc_en); // port A data enable
wire [GPIO_N-1:0] ds = 0; // "software" data (programmed by lower 24 bits)
wire [GPIO_N-1:0] ds_en = 0; // "software" data enable (programmed by lower 24 bits)
wire [GPIO_N-1:0] ds; // "software" data (programmed by lower 24 bits)
wire [GPIO_N-1:0] ds_en; // "software" data enable (programmed by lower 24 bits)
reg [3:0] ch_en = 0; // channel enable
wire [31:0] cmd_data;
......@@ -119,6 +119,7 @@ module gpio393 #(
(da_en_m & da) |
(ds_en_m & ds);
assign io_t = ~(dc_en_m | db_en_m | da_en_m | ds_en_m);
// 0 0 0 - no change -
// 0 1 1 1 0
// 1 0 2 1 1
......
util_modules/mcont_from_chnbuf_reg.v
View file @ 0cfebd24
......@@ -29,41 +29,31 @@ module mcont_from_chnbuf_reg #(
input ext_buf_rd,
input [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
input ext_buf_rrefresh,
// input ext_buf_rrun,
input ext_buf_rpage_nxt,
output reg [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
output reg buf_rd_chn,
// output reg buf_run,
output reg rpage_nxt,
input [63:0] buf_rdata_chn
);
reg [63:0] buf_rdata_chn_r; /// *** temporary register to delay buffer read data - may be used to implement multi-clock mux to ease timing
reg buf_chn_sel;
reg [CHN_LATENCY:0] latency_reg=0;
always @ (posedge rst or posedge clk) begin
// always @ (posedge rst or posedge clk) begin
always @ (posedge clk) begin
if (rst) buf_chn_sel <= 0;
else buf_chn_sel <= (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh;
if (rst) buf_rd_chn <= 0;
else buf_rd_chn <= buf_chn_sel && ext_buf_rd;
// if (rst) buf_run <= 0;
// else buf_run <= (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh && ext_buf_rrun;
if (rst) latency_reg<= 0;
// else latency_reg <= buf_rd_chn | (latency_reg << 1);
else latency_reg <= {latency_reg[CHN_LATENCY-1:0], buf_rd_chn};
// if (rst) buf_done <= 0;
// else buf_done <= buf_chn_sel && seq_done;
end
// always @ (posedge clk) buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
// always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
// always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;
always @ (posedge clk) buf_rdata_chn_r <= buf_rdata_chn; // THIS WILL BE REPLACED BY MULTI-CYCLE MUX
always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn_r;
always @ (posedge clk) rpage_nxt <= ext_buf_rpage_nxt && (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh;
//buf_rdata_chn_r
endmodule
wrap/idelay_fine_pipe.v
View file @ 0cfebd24
......@@ -37,9 +37,10 @@ module idelay_fine_pipe
);
reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];
always @ (posedge clk or posedge rst) begin
always @ (posedge clk) begin
if (rst) fdly_pre <= DELAY_VALUE[2:0];
else if (ld) fdly_pre <= delay[2:0];
if (rst) fdly <= DELAY_VALUE[2:0];
else if (set) fdly <= fdly_pre;
end
......
wrap/mmcm_phase_cntr.v
View file @ 0cfebd24
......@@ -116,7 +116,7 @@ module mmcm_phase_cntr#(
// made a difference, so it doesn't seem Vivado extends bits of operands "+", "-"
wire [PHASE_WIDTH:0] diff= {ps_target[PHASE_WIDTH-1],ps_target}-{ps_dout_r[PHASE_WIDTH-1],ps_dout_r};
assign ps_dout = ps_dout_r;
always @ (posedge psclk or posedge rst) begin
always @ (posedge psclk) begin
if (rst) ps_start0 <= 0;
else ps_start0 <= ps_we && ps_ready;
......
wrap/odelay_fine_pipe.v
View file @ 0cfebd24
......@@ -36,9 +36,10 @@ module odelay_fine_pipe
output data_out
);
reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];
always @ (posedge clk or posedge rst) begin
always @ (posedge clk) begin
if (rst) fdly_pre <= DELAY_VALUE[2:0];
else if (ld) fdly_pre <= delay[2:0];
if (rst) fdly <= DELAY_VALUE[2:0];
else if (set) fdly <= fdly_pre;
end
......
x393.v
View file @ 0cfebd24
......@@ -2080,7 +2080,7 @@ assign axi_grst = axi_rst_pre;
.WIDTH(7),
.REGISTER(4)
) sync_resets_i (
.arst(), // input
.arst (axi_rst_pre), // input
.locked ({locked_hclk, 1'b1, locked_sync_clk, locked_sync_clk, locked_xclk, locked_pclk, mcntrl_locked}), // input
.clk ({hclk, axi_aclk, logger_clk, camsync_clk, xclk, pclk, mclk}), // input[6:0]
.rst ({hrst, arst, lrst, crst, xrst, prst, mrst}) // output[6:0]
......
x393.xdc
View file @ 0cfebd24
......@@ -21,6 +21,16 @@
#http://forums.xilinx.com/t5/7-Series-FPGAs/MMCM-reference-clock-muxing/td-p/550622
set_property is_enabled false [get_drc_checks REQP-119]
#Input Buffer Connections .. has no loads. An input buffer must drive an internal load.
set_property is_enabled false [get_drc_checks BUFC-1]
#DSP Buffering:
set_property is_enabled false [get_drc_checks DPIP-1]
set_property is_enabled false [get_drc_checks DPOP-1]
#MMCME2_ADV connectivity violation
set_property is_enabled false [get_drc_checks REQP-1577]
#Synchronous clocking for BRAM (mult_saxi_wr_inbuf_i/ram_var_w_var_r_i/ram_i/RAMB36E1_i) in SDP mode ...
set_property is_enabled false [get_drc_checks REQP-165]
# output SDRST, // output SDRST, active low
......
x393_timing.xdc
View file @ 0cfebd24
......@@ -76,10 +76,36 @@ create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
create_generated_clock -name pclk2x [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
#Sensor-synchronous clocks
create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
#set_clock_groups -name ps_async_clock_axihp -asynchronous -group {clk_axihp_pre}
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x}
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
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