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Commit a500d197 authored by Andrey Filippov's avatar Andrey Filippov
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Finished simulation/testing of a single-channel... 

Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
parent df351507
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.project
View file @ a500d197
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
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<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150723191855730.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150818191452916.log</location>
</link>
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<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150723191855730.log</location>
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<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150723191855730.log</location>
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<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150723191855730.log</location>
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<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150723191855730.log</location>
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<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
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<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
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<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......@@ -107,32 +107,32 @@
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<name>vivado_logs/VivadoTimingReportImplemented.log</name>
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<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150723191855730.log</location>
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<location>/home/andrey/git/x393/vivado_state/x393-route-20150818191452916.dcp</location>
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</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ a500d197
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
VivadoSynthesis_95_ShowInfo=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->
eclipse.preferences.version=1
compressor_jp/focus_sharp393.v
View file @ a500d197
......@@ -25,6 +25,7 @@
** -----------------------------------------------------------------------------**
**
*/
`include "system_defines.vh"
`timescale 1ns/1ps
//TODO: Modify to work with other modes (now only on color)
module focus_sharp393(
......
compressor_jp/huffman393.v
View file @ a500d197
......@@ -24,6 +24,7 @@
** -----------------------------------------------------------------------------**
**
*/
`include "system_defines.vh"
// 01/22/2004 - extended flush until ready (modified stuffer.v too)
module huffman393 (
input xclk, // pixel clock, sync to incoming data
......
compressor_jp/quantizer393.v
View file @ a500d197
......@@ -24,7 +24,7 @@
** -----------------------------------------------------------------------------**
**
*/
`include "system_defines.vh"
`timescale 1ns/1ps
// will add extracted DC (8 bits) to data from DCT here that will make data 12 bits (signed) long.
......
includes/ram18_declare_init.vh
View file @ a500d197
This diff is collapsed.
includes/ram36_declare_init.vh
View file @ a500d197
This diff is collapsed.
memctrl/phy/byte_lane.v
View file @ a500d197
......@@ -26,6 +26,7 @@ module byte_lane #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD_DQ = "SSTL15_T_DCI",
parameter IOSTANDARD_DM = "SSTL15",
parameter IOSTANDARD_DQS = "DIFF_SSTL15_T_DCI",
parameter SLEW_DQ = "SLOW",
parameter SLEW_DQS = "SLOW",
......@@ -139,7 +140,7 @@ endgenerate
dm_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.IOSTANDARD(IOSTANDARD_DQ),
.IOSTANDARD(IOSTANDARD_DM),
.SLEW(SLEW_DQ),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
......
memctrl/phy/dm_single.v
View file @ a500d197
......@@ -27,7 +27,7 @@ module dm_single #(
// parameter integer IDELAY_VALUE = 0,
parameter integer ODELAY_VALUE = 0,
parameter IBUF_LOW_PWR ="TRUE", //SuppressThisWarning VEditor not used in OBUF_DCIEN
parameter IOSTANDARD = "SSTL15_T_DCI",
parameter IOSTANDARD = "SSTL15",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
......
memctrl/phy/phy_cmd.v
View file @ a500d197
......@@ -359,6 +359,7 @@ module phy_cmd#(
phy_top #(
.IOSTANDARD_DQ ("SSTL15_T_DCI"),
.IOSTANDARD_DM ("SSTL15"),
.IOSTANDARD_DQS ("DIFF_SSTL15_T_DCI"),
.IOSTANDARD_CMDA ("SSTL15"),
.IOSTANDARD_CLK ("DIFF_SSTL15"),
......
memctrl/phy/phy_top.v
View file @ a500d197
......@@ -22,6 +22,7 @@
module phy_top #(
parameter IOSTANDARD_DQ = "SSTL15_T_DCI",
parameter IOSTANDARD_DM = "SSTL15",
parameter IOSTANDARD_DQS = "DIFF_SSTL15_T_DCI",
parameter IOSTANDARD_CMDA = "SSTL15",
parameter IOSTANDARD_CLK = "DIFF_SSTL15",
......@@ -226,6 +227,7 @@ module phy_top #(
.IODELAY_GRP (IODELAY_GRP),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.IOSTANDARD_DQ (IOSTANDARD_DQ),
.IOSTANDARD_DM (IOSTANDARD_DM),
.IOSTANDARD_DQS (IOSTANDARD_DQS),
.SLEW_DQ (SLEW_DQ),
.SLEW_DQS (SLEW_DQS),
......@@ -258,6 +260,7 @@ module phy_top #(
.IODELAY_GRP (IODELAY_GRP),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.IOSTANDARD_DQ (IOSTANDARD_DQ),
.IOSTANDARD_DM (IOSTANDARD_DM),
.IOSTANDARD_DQS (IOSTANDARD_DQS),
.SLEW_DQ (SLEW_DQ),
.SLEW_DQS (SLEW_DQS),
......
sensor/sens_gamma.v
View file @ a500d197
......@@ -19,6 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
// TODO - Add registers to MPY
module sens_gamma #(
parameter SENS_NUM_SUBCHN = 3, // number of subchannels for his sensor ports (1..4)
......
wrap/ram18_var_w_var_r.v
View file @ a500d197
......@@ -19,6 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
/*
Address/data widths
......@@ -81,6 +82,11 @@ module ram18_var_w_var_r
parameter integer LOG2WIDTH_WR = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter integer LOG2WIDTH_RD = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter DUMMY = 0
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -96,9 +102,6 @@ module ram18_var_w_var_r
input [ 3:0] web, // write byte enable
input [(1 << LOG2WIDTH_WR)-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
generate
if (DUMMY)
ram18_dummy #(
......@@ -190,6 +193,11 @@ endmodule
module ram18_32w_32r
#(
parameter integer REGISTERS = 0 // 1 - registered output
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -204,9 +212,6 @@ module ram18_32w_32r
input [ 3:0] web, // write byte enable
input [31:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR=36;
localparam PWIDTH_RD=36;
......@@ -267,6 +272,10 @@ module ram18_lt32w_lt32r
parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 4, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 4 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -281,9 +290,6 @@ module ram18_lt32w_lt32r
input [ 3:0] web, // write byte enable
input [(1 << LOG2WIDTH_WR)-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
......@@ -350,6 +356,10 @@ module ram18_lt32w_32r
#(
parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 4 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -364,9 +374,6 @@ module ram18_lt32w_32r
input [ 3:0] web, // write byte enable
input [(1 << LOG2WIDTH_WR)-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = 36;
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
......@@ -430,6 +437,10 @@ module ram18_32w_lt32r
parameter integer REGISTERS = 0, // 1 - registered output
// parameter integer LOG2WIDTH_WR = 4, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 4 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -444,9 +455,6 @@ module ram18_32w_lt32r
input [ 3:0] web, // write byte enable
input [31:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = 36;
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_RD = 1 << LOG2WIDTH_RD;
......
wrap/ram18p_var_w_var_r.v
View file @ a500d197
......@@ -16,6 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*******************************************************************************/
`include "system_defines.vh"
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
......@@ -77,6 +78,10 @@ module ram18p_var_w_var_r
parameter integer LOG2WIDTH_WR = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter integer LOG2WIDTH_RD = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter DUMMY = 0
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -92,9 +97,6 @@ module ram18p_var_w_var_r
input [ 3:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
generate
if (DUMMY)
ram18p_dummy #(
......@@ -186,6 +188,10 @@ endmodule
module ram18p_32w_32r
#(
parameter integer REGISTERS = 0 // 1 - registered output
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -200,9 +206,6 @@ module ram18p_32w_32r
input [ 3:0] web, // write byte enable
input [35:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR=72;
localparam PWIDTH_RD=72;
......@@ -263,6 +266,10 @@ module ram18p_lt32w_lt32r
parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 4, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 4 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -277,9 +284,6 @@ module ram18p_lt32w_lt32r
input [ 3:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
......@@ -351,6 +355,10 @@ module ram18p_lt32w_32r
#(
parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 4 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -365,9 +373,6 @@ module ram18p_lt32w_32r
input [ 3:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = 36;
......@@ -436,6 +441,10 @@ module ram18p_32w_lt32r
parameter integer REGISTERS = 0, // 1 - registered output
// parameter integer LOG2WIDTH_WR = 4, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 4 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -450,9 +459,6 @@ module ram18p_32w_lt32r
input [ 3:0] web, // write byte enable
input [35:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram18_declare_init.vh"
`endif
localparam PWIDTH_WR = 72;
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_RD = 1 << LOG2WIDTH_RD;
......
wrap/ramp_var_w_var_r.v
View file @ a500d197
......@@ -16,6 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*******************************************************************************/
`include "system_defines.vh"
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
......@@ -77,6 +78,10 @@ module ramp_var_w_var_r
parameter integer LOG2WIDTH_WR = 6, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter integer LOG2WIDTH_RD = 6, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter DUMMY = 0
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -92,10 +97,6 @@ module ramp_var_w_var_r
input [ 7:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
generate
if (DUMMY)
ramp_dummy #(
......@@ -186,6 +187,10 @@ endmodule
module ramp_64w_64r
#(
parameter integer REGISTERS = 0 // 1 - registered output
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -200,9 +205,6 @@ module ramp_64w_64r
input [ 7:0] web, // write byte enable
input [71:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_WR=72;
localparam PWIDTH_RD=72;
......@@ -280,6 +282,10 @@ module ramp_lt64w_lt64r
parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 5, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 5 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -295,9 +301,6 @@ module ramp_lt64w_lt64r
input [ 7:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
......@@ -402,6 +405,10 @@ module ramp_lt64w_64r
#(
parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 5 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -417,9 +424,6 @@ module ramp_lt64w_64r
input [ 7:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = 72;
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
......@@ -504,6 +508,10 @@ module ramp_64w_lt64r
parameter integer REGISTERS = 0, // 1 - registered output
// parameter integer LOG2WIDTH_WR = 5, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 5 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
......@@ -518,9 +526,6 @@ module ramp_64w_lt64r
input [ 7:0] web, // write byte enable
input [71:0] data_in // data out
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_WR = 72;
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_RD = 1 << LOG2WIDTH_RD;
......
wrap/ramt_var_w_var_r.v
View file @ a500d197
......@@ -21,6 +21,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
......@@ -85,6 +86,10 @@ module ramt_var_w_var_r
parameter integer LOG2WIDTH_B = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter WRITE_MODE_A = "NO_CHANGE", //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
parameter WRITE_MODE_B = "NO_CHANGE" //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
)(
input clk_a, // clock for port A
input [14-LOG2WIDTH_A:0] addr_a, // address port A
......@@ -102,9 +107,6 @@ module ramt_var_w_var_r
output [(1 << LOG2WIDTH_B)-1:0] data_out_b,// data out port B
input [(1 << LOG2WIDTH_B)-1:0] data_in_b // data in port B
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
localparam PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
localparam WIDTH_A = 1 << LOG2WIDTH_A;
......
wrap/ramtp_var_w_var_r.v
View file @ a500d197
......@@ -21,6 +21,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
......@@ -85,6 +86,10 @@ module ramtp_var_w_var_r
parameter integer LOG2WIDTH_B = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter WRITE_MODE_A = "NO_CHANGE", //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
parameter WRITE_MODE_B = "NO_CHANGE" //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
)(
input clk_a, // clock for port A
input [14-LOG2WIDTH_A:0] addr_a, // address port A
......@@ -102,9 +107,6 @@ module ramtp_var_w_var_r
output [(9 << (LOG2WIDTH_B-3))-1:0] data_out_b,// data out port B
input [(9 << (LOG2WIDTH_B-3))-1:0] data_in_b // data in port B
);
`ifdef PRELOAD_BRAMS
`include "includes/ram36_declare_init.vh"
`endif
localparam PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
localparam PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
localparam WIDTH_A = 1 << LOG2WIDTH_A;
......
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