Fixed some errors in old memory controller modules (ccbfbf84) · Commits · Elphel / x393

.project

+8 −8

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		@@ -62,42 +62,42 @@
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.settings/com.elphel.vdt.iverilog.prefs

+3 −2

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		com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->
		com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->
		eclipse.preferences.version=1
		iverilog_100_TopModulesOther=glbl<-@\#\#@->
		iverilog_101_TopModulesOther=glbl<-@\#\#@->
		@@ -12,8 +12,9 @@ iverilog_105_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_proje
		iverilog_109_ShowNoProblem=true
		iverilog_110_ShowNoProblem=true
		iverilog_110_ShowWarnings=false
		iverilog_113_SaveLogsPreprocessor=true
		iverilog_113_SaveLogsPreprocessor=false
		iverilog_113_SaveLogsSimulator=true
		iverilog_114_SaveLogsSimulator=true
		iverilog_121_GrepFindErrWarn=error\|warning\|sorry
		iverilog_77_Param_Exe=/usr/local/bin/iverilog
		iverilog_78_VVP_Exe=/usr/local/bin/vvp

axi/cmprs_afi_mux.v

+22 −8

Original line number	Diff line number	Diff line
		@@ -212,7 +212,16 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
		// reg [1:0] wlen32; // 2 high bits of burst len (LSB are always 2'b11)

		reg [3:0] wleft; // number of 64-bit words left to be sent - also used as awlen (valid @ awvalid)
		reg [2:0] chunk_inc; // how much to increment chunk pointer (1..4)
		// reg [2:0] chunk_inc; // how much to increment chunk pointer (1..4)

		// wire [2:0] pre_chunk_inc = (\|counts_corr2[7:2])? // Would like to increment, if not roll-over
		// 3'h4 :
		// ({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);

		wire [1:0] pre_chunk_inc_m1 = (\|counts_corr2[7:2])? // Would like to increment, if not roll-over
		2'h3 :
		left_to_eof[winner2 * 8 +: 2];


		reg [ 3:0] reset_pointers; // per-channel - after chunk_start_hclk or chunk_len_hclk were written or explicit fifo_rst*

		@@ -234,7 +243,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),

		reg [5:0] afi_awid_r;


		wire [2:0] max_wlen; // 0,1,2,3,7 (7 - not limited by rollover) - calculated by cmprs_afi_mux_ptr
		wire [1:0] want_wleft32 = (\|items_left[7:2])? 2'b11 : items_left[1:0]; // want to set wleft[3:2] if not roll-over

		assign cmd_we_status_w = cmd_we && ((cmd_a & 'hc) == CMPRS_AFIMUX_STATUS_CNTRL);
		assign cmd_we_mode_w = cmd_we && (cmd_a == CMPRS_AFIMUX_MODE);
		@@ -416,7 +426,9 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
		//pend_last

		if (!en) wleft <= 0;
		else if (pre_busy_w) wleft <= {(\|items_left[7:2])? 2'b11 : items_left[1:0], 2'b11};
		/// else if (pre_busy_w) wleft <= {(\|items_left[7:2])? 2'b11 : items_left[1:0], 2'b11}; // @@@******* different for roll over
		/// else if (pre_busy_w) wleft <= {(max_wlen[2] \|\| (max_wlen[1:0] > want_wleft32))? want_wleft32 : max_wlen[1:0], 2'b11};
		else if (pre_busy_w) wleft <= {(max_wlen[1:0] > want_wleft32) ? want_wleft32 : max_wlen[1:0], 2'b11};
		else if (wleft != 0) wleft <= wleft - 1;
		/*
		counts_corr2[8]
		@@ -456,9 +468,9 @@ items_left
		// wdata register mux
		if (wdata_en) wdata <= wdata_sel[1]?(wdata_sel[0]?fifo_rdata3:fifo_rdata2):(wdata_sel[0]?fifo_rdata1:fifo_rdata0);

		if (pre_busy_w) chunk_inc <= (\|counts_corr2[7:2])?
		3'h4 :
		({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);
		// if (pre_busy_w) chunk_inc <= (\|counts_corr2[7:2])? // Would like to increment, if not roll-over
		// 3'h4 :
		// ({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);

		if (awvalid[0]) afi_awid_r <={1'b0,wleft[3:2],last_burst_in_frame,cur_chn};

		@@ -517,13 +529,15 @@ items_left
		.pre_busy_w (pre_busy_w), // input
		.winner_channel (winner2), // input[1:0]
		.need_to_bother (need_to_bother), // input
		.chunk_inc (chunk_inc), // input[2:0]
		// .chunk_inc (chunk_inc), // input[2:0]
		.chunk_inc_want_m1 (pre_chunk_inc_m1), // input[1:0] Want to increment by this (0..3) + 1, if not roll over
		.last_burst_in_frame (last_burst_in_frame), // input
		.busy (busy), // input[3:0]
		.ptr_resetting (ptr_resetting), // output
		.chunk_addr (chunk_addr), // output[26:0] reg
		.chunk_ptr_ra (chunk_ptr_ra[2:0]), // input[2:0]
		.chunk_ptr_rd (chunk_ptr_rd01[0 * 27 +: 27]) // output[26:0]
		.chunk_ptr_rd (chunk_ptr_rd01[0 * 27 +: 27]), // output[26:0]
		.max_wlen (max_wlen) // output[2:0]: msb - no rollover (>3)
		);
		assign chunk_ptr_rd=chunk_ptr_ra[3]?chunk_ptr_rd01[1 * 27 +: 27]:chunk_ptr_rd01[0 * 27 +: 27];
		cmprs_afi_mux_ptr_wresp cmprs_afi_mux_ptr_wresp_i (

axi/cmprs_afi_mux_ptr.v

+49 −8

Original line number	Diff line number	Diff line
		@@ -33,14 +33,17 @@ module cmprs_afi_mux_ptr(
		input pre_busy_w, // combinatorial signal - one before busy[0] (depends on ptr_resetting)
		input [ 1:0] winner_channel, // channel that won arbitration for AXI access, valid @ pre_busy_w
		input need_to_bother, // whants to start access if address and data FIFO permit
		input [2:0] chunk_inc, // how much to increment chunk pointer (1..4) - valid witrh busy[0]
		input [1:0] chunk_inc_want_m1, // how much to increment chunk pointer (0..3) +1 - valid with busy[0] (w/o rollover)

		input last_burst_in_frame, // valid with busy[0] (last_burst_in_frame<=last_chunk_w[winner2])
		input [ 3:0] busy, // one cycle less than sending 1-4 bursts, [1] - delayed by 1, [2] - by 2
		output ptr_resetting, // pointers will be reset next cycle (2-cycle-long pulse)
		output reg [26:0] chunk_addr, // chunk absolute address, valid with busy[1]
		input [ 2:0] chunk_ptr_ra, // chunk pointer read address {eof, chn[1:0]}
		output [26:0] chunk_ptr_rd // chunk pointer read data (non-registered
		output [26:0] chunk_ptr_rd, // chunk pointer read data (non-registered
		// output [ 2:0] max_inc // maximal increment to rollover (limited by 4)
		output [ 2:0] max_wlen // maximal wlen[3:2], MSB - limited by rollover

		);
		reg [3:0] reset_rq; // request to reset pointers when ready
		reg [3:0] reset_rq_pri; // one-hot reset rq
		@@ -53,21 +56,45 @@ module cmprs_afi_mux_ptr(
		wire [26:0] ptr_ram_di; // data to be written to ptr_ram
		reg [26:0] sa_len_ram[0:7]; // start chunk/num cunks in a buffer (write port @mclk)
		reg [26:0] chunk_ptr_inc; // incremented by 1..4 chunk pointer
		reg [27:0] chunk_ptr_rovr; // incremented chunk pointer, decremented by length (MSB - sign)
		// reg [27:0] rollover_r; // incremented chunk pointer, decremented by length (MSB - sign)
		reg en_d; //enable delayed by 1 cycle
		wire [ 2:0] sa_len_ra; // start/len read address (0..3 - start addresses, 4..7 - lengths)

		reg [ 2:0] max_inc_ram[0:3]; // maximal increment to rollover (limited by 4)
		wire [ 1:0] pre_chunk_inc_m1;
		reg [ 2:0] chunk_inc;
		wire [26:0] chunks_to_rollover;

		reg [3:0] chunks_to_rollover_r; // [3] >=8
		wire [3:0] chunks_to_rollover_m1;
		reg max_inc_ram_we;
		reg [1:0] max_inc_ram_wa;
		wire rollover_w; // this cycle causes rollover - valid at pre_busy_w
		reg rollover_r; // this cycle causes rollover - valid at busy[0] and late

		wire ptr_ram_wa = ptr_ram[ptr_wa]; // SuppressThisWarning VEditor debug - just to view

		assign ptr_resetting = resetting[0];
		assign sa_len_ra= {busy[1],ptr_wa[1:0]};

		assign reset_rq_enc = {reset_rq_pri[3] \| reset_rq_pri[2],
		reset_rq_pri[3] \| reset_rq_pri[1]};
		assign ptr_ram_di= resetting[1] ? 27'b0 : (chunk_ptr_rovr[27] ? chunk_ptr_inc : chunk_ptr_rovr[26:0]);
		// assign ptr_ram_di= resetting[1] ? 27'b0 : (chunk_ptr_rovr[27] ? chunk_ptr_inc : chunk_ptr_rovr[26:0]);
		assign ptr_ram_di= (resetting[1] \|\|rollover_r) ? 27'b0 : chunk_ptr_inc ;

		assign chunk_ptr_rd = ptr_ram[chunk_ptr_ra];
		assign start_resetting_w = en && !busy[0] && !resetting[0] && (\|reset_rq) && !need_to_bother;

		// assign max_inc = max_inc_ram[winner_channel];
		assign max_wlen = max_inc_ram[winner_channel]; // valid @pre_busy_w

		//chunk_inc_want_m1
		assign pre_chunk_inc_m1 = (max_wlen[1:0] >= chunk_inc_want_m1)? chunk_inc_want_m1 : max_wlen[1:0];
		assign rollover_w = !max_wlen[2] && (max_wlen[1:0] <= chunk_inc_want_m1);

		assign chunks_to_rollover = sa_len_ram[sa_len_ra] - ptr_ram_di;
		assign chunks_to_rollover_m1 = chunks_to_rollover_r -1;

		always @ (posedge hclk) begin
		en_d <= en;
		// ===== calculate and rollover channel addresses ====
		@@ -103,11 +130,25 @@ module cmprs_afi_mux_ptr(
		chunk_addr <= ptr_ram[ptr_wa] + sa_len_ram[sa_len_ra];
		chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc;
		end
		if (busy[1] && !busy[2]) begin // first clock of busy
		chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,sa_len_ram[sa_len_ra]}; // sa_len_ra now points at length
		end
		// if (busy[1] && !busy[2]) begin // first clock of busy
		// chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,sa_len_ram[sa_len_ra]}; // sa_len_ra now points at length
		// end
		// write to ptr_ram (1 or 2 locations - if eof)
		if (ptr_we) ptr_ram[ptr_wa] <= ptr_ram_di;

		if (pre_busy_w) chunk_inc <= {1'b0, pre_chunk_inc_m1} + 1;

		if (pre_busy_w) rollover_r <= rollover_w;

		// wire [26:0] chunks_to_rollover;

		// reg [3:0] chunks_to_rollover_r; // [3] >=8
		if (ptr_we) chunks_to_rollover_r <= {\|chunks_to_rollover[26:3],chunks_to_rollover[2:0]};

		max_inc_ram_we <= ptr_we & ~ptr_wa[2];
		max_inc_ram_wa <= ptr_wa[1:0];

		if (max_inc_ram_we) max_inc_ram[max_inc_ram_wa] <= (\|chunks_to_rollover_m1[3:2])?3'h7:{1'b0,chunks_to_rollover_m1[1:0]};
		end
		endmodule

axi/cmprs_afi_mux_ptr_wresp.v

+27 −17

Original line number	Diff line number	Diff line
		@@ -54,10 +54,11 @@ module cmprs_afi_mux_ptr_wresp(
		reg [26:0] len_ram[0:3]; // start chunk/num cunks in a buffer (write port @mclk)
		reg [26:0] chunk_ptr_inc; // incremented by 1..4 chunk pointer
		reg [27:0] chunk_ptr_rovr; // incremented chunk pointer, decremented by length (MSB - sign)
		reg [ 3:0] busy; // one-hot busy stages (usually end with [3]
		// reg [ 5:0] id_r; // registered ID data
		/// reg [ 3:0] busy; // one-hot busy stages (usually end with [3]
		reg [ 4:0] busy; // one-hot busy stages (usually end with [4]

		reg [ 4:0] id_r; // registered ID data - MSB is unused
		reg [1:0] chn; // selected channel
		reg [1:0] chn; // selected channel valid @busy[2]
		reg eof; // eof register being written
		reg last_burst_in_frame; // this response is for eof
		reg [2:0] chunk_inc;
		@@ -71,14 +72,19 @@ module cmprs_afi_mux_ptr_wresp(
		reset_rq_pri[3] \| reset_rq_pri[1]};
		assign ptr_ram_di= resetting[1] ? 27'b0 : (chunk_ptr_rovr[27] ? chunk_ptr_inc : chunk_ptr_rovr[26:0]);

		assign ptr_wa = {eof,chn};
		assign ptr_wa = {eof,chn}; // valid @busy[2]
		assign afi_bready = afi_bready_r;

		/// assign pre_we= resetting[0] \|\| // a pair of cycles to reset chunk pointer and frame chunk pointer
		/// busy[2] \|\| // always update chunk pointer
		/// (busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
		assign pre_we= resetting[0] \|\| // a pair of cycles to reset chunk pointer and frame chunk pointer
		busy[2] \|\| // always update chunk pointer
		(busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
		assign pre_busy= afi_bvalid_r && en && !(\|busy[1:0]) && !pre_we;
		assign start_resetting_w = !afi_bvalid_r && en && !(\|busy[1:0]) && !pre_we && (\|reset_rq);
		busy[3] \|\| // always update chunk pointer
		(busy[4] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
		/// assign pre_busy= afi_bvalid_r && en && !(\|busy[1:0]) && !pre_we;
		/// assign start_resetting_w = !afi_bvalid_r && en && !(\|busy[1:0]) && !pre_we && (\|reset_rq);
		assign pre_busy= afi_bvalid_r && en && !(\|busy[2:0]) && !pre_we;
		assign start_resetting_w = !afi_bvalid_r && en && !(\|busy[2:0]) && !pre_we && (\|reset_rq);

		assign chunk_ptr_rd = ptr_ram[chunk_ptr_ra];

		@@ -89,10 +95,11 @@ module cmprs_afi_mux_ptr_wresp(
		afi_bvalid_r <= afi_bvalid;

		afi_bready_r <= !en \|\| pre_busy; // (!busy[0] && !pre_busy && !resetting[0] && !start_resetting_w);
		busy <= {busy[2:0], pre_busy}; // adjust bits
		// busy <= {busy[2:0], pre_busy}; // adjust bits
		busy <= {busy[3:0], pre_busy}; // adjust bits

		// id_r <= afi_bid;
		id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
		// id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
		if (afi_bready && afi_bvalid) id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved

		if (start_resetting_w) reset_rq_pri <= {reset_rq[3] & ~(\|reset_rq[2:0]),
		reset_rq[2] & ~(\|reset_rq[1:0]),
		@@ -106,9 +113,11 @@ module cmprs_afi_mux_ptr_wresp(
		else resetting <= {resetting[0], start_resetting_w \| (resetting[0] & ~resetting[1])};

		if (resetting == 2'b01) chn <= reset_rq_enc;
		else if (busy[0]) chn <= id_r[0 +: 2];
		/// else if (busy[0]) chn <= id_r[0 +: 2];
		else if (busy[1]) chn <= id_r[0 +: 2];

		if (busy[0]) begin // first busy cycle
		/// if (busy[0]) begin // first busy cycle
		if (busy[1]) begin // first busy cycle
		last_burst_in_frame <= id_r[2];
		chunk_inc <= {1'b0,id_r[3 +:2]} + 1;
		end
		@@ -118,10 +127,11 @@ module cmprs_afi_mux_ptr_wresp(
		if ((resetting == 2'b01) \|\| busy[0]) eof <= 0;
		else if (ptr_we) eof <= 1; // always second write cycle


		if (busy[1]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy

		if (busy[2]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy
		// @@@ delay by 1 clk
		/// if (busy[1]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy
		/// if (busy[2]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy
		if (busy[2]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy
		if (busy[3]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy

		// write to ptr_ram (1 or 2 locations - if eof)
		if (ptr_we) ptr_ram[ptr_wa] <= ptr_ram_di;

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