Commit bf7c096d authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Trying synthesis, fixing revealed bugs

parent 16513305

.project

+1 −1
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ 
		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150702180615691.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150718125232570.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

axi/cmprs_afi_mux.v

+3 −3
Original line number Diff line number Diff line
@@ -216,7 +216,7 @@ module cmprs_afi_mux#( 
    assign afi_awvalid = awvalid[1];

    assign afi_awlen = {wleft[3:2],2'b11};

    assign afi_wdata = wdata;

    assign afi_bready = 1'b1; // always ready

//    assign afi_bready = 1'b1; // always ready

    

// other fixed-value AFI signals

    assign afi_awlock =        2'h0;
@@ -325,7 +325,7 @@ module cmprs_afi_mux#( 
        else if (done_burst_w) busy <= 0; // {busy[2:0],1'b0};

        

        if      (!en)        wleft <= 0;

        else if (pre_busy_w) wleft <= {(|counts_corr2[7:2])? 2'b11 : left_to_eof[winner2 * 8 +: 8][1:0], 2'b11};

        else if (pre_busy_w) wleft <= {(|counts_corr2[7:2])? 2'b11 : left_to_eof[winner2 * 8 +: 2], 2'b11};

        else if (wleft != 0) wleft <= wleft - 1;
@@ -354,7 +354,7 @@ module cmprs_afi_mux#( 


        if (pre_busy_w) chunk_inc <= (|counts_corr2[7:2])?

                                       3'h4 :

                                       ({1'b0,left_to_eof[winner2 * 8 +: 8][1:0]} + 3'h1);

                                       ({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);

        

    end

axi/mult_saxi_wr.v

+1 −1
Original line number Diff line number Diff line
@@ -445,7 +445,7 @@ module mult_saxi_wr #( 
                .wclk      (mclk), // input

                .waddr     (buf_wa[8:0]), // input[9:0] 

                .we        (buf_we), // input

                .web       (4'hff), // input[7:0] 

                .web       (4'hf), // input[7:0] 

                .data_in   (buf_wd) // input[31:0] 

            );

        else

axi/mult_saxi_wr_inbuf.v

+1 −1
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ module mult_saxi_wr_inbuf#( 
                .wclk      (iclk), // input

                .waddr     (waddr[13-MULT_SAXI_WLOG:0]), // input[9:0] 

                .we        (valid), // input

                .web       (4'hff), // input[7:0] 

                .web       (4'hf), // input[7:0] 

                .data_in   (data_in) // input[31:0] 

            );

        else

compressor_jp/jp_channel.v

+5 −6
Original line number Diff line number Diff line
@@ -785,6 +785,11 @@ module jp_channel#( 


    // Format DC components to be output as a mini-frame. Was not used in the late NC353 as the dma1 channel was use3d for IMU instead of dcc

    wire          finish_dcc;

    wire   [15:0] stuffer_do;

    wire          stuffer_dv;

    wire          stuffer_done;

    wire          eof_written_xclk2xn;

    

    // re-sync to posedge xclk2x

    pulse_cross_clock finish_dcc_i (.rst(rst), .src_clk(~xclk2x), .dst_clk(xclk2x), .in_pulse(stuffer_done), .out_pulse(finish_dcc),.busy());
@@ -844,12 +849,6 @@ module jp_channel#( 
    );

    



    

    wire   [15:0] stuffer_do;

    wire          stuffer_dv;

    wire          stuffer_done;

    wire          eof_written_xclk2xn;



    stuffer393 stuffer393_i (

        .rst                 (rst),                    // input

        .mclk                (mclk),                   // input