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x393
Commit 225fccd0 authored by Andrey Filippov's avatar Andrey Filippov
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simulating multiple simultanerous sesnor/compressor channels

parent a500d197
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Showing with 559 additions and 140 deletions
axi/cmprs_afi_mux.v
View file @ 225fccd0
......@@ -117,7 +117,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
output [ 1:0] afi_awlock,
output [ 3:0] afi_awcache,
output [ 2:0] afi_awprot,
output [ 3:0] afi_awlen,
output reg [ 3:0] afi_awlen,
output [ 1:0] afi_awsize,
output [ 1:0] afi_awburst,
output [ 3:0] afi_awqos,
......@@ -220,6 +220,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
wire [ 3:0] chunk_ptr_ra;
wire [ 7:0] items_left = counts_corr2[8] ? left_to_eof[(winner2 * 8) +: 8] : counts_corr2[7:0];
reg [5:0] afi_awid_r;
......@@ -246,9 +247,9 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
assign {fifo_ren3, fifo_ren2, fifo_ren1, fifo_ren0} = fifo_ren;
assign afi_awaddr = {chunk_addr,5'b0};
assign afi_awid = {1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
assign afi_awid = afi_awid_r; // {1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
assign afi_awvalid = awvalid[1];
assign afi_awlen = {wleft[3:2],2'b11};
// assign afi_awlen = {wleft[3:2],2'b11};
assign afi_wdata = wdata;
// assign afi_bready = 1'b1; // always ready
......@@ -426,28 +427,33 @@ items_left
if (pre_busy_w) chunk_inc <= (|counts_corr2[7:2])?
3'h4 :
({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);
if (awvalid[0]) afi_awid_r <={1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
if (awvalid[0]) afi_awlen <= {wleft[3:2],2'b11};
end
// delay write channel controls signal to match data latency. wid bits will be optimized (6 -> 3)
dly_16 #(
.WIDTH(8)
.WIDTH(2) // 8)
) afi_wx_i (
.clk (hclk), // input
.rst (!en), // input
.dly (AFI_MUX_BUF_LATENCY), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
.din ({ wvalid, wlast, afi_awid}), // input[0:0]
.dout ({afi_wvalid, afi_wlast, afi_wid}) // output[0:0]
.din ({ wvalid, wlast}), // , afi_awid_r}), // afi_awid}), // input[0:0]
.dout ({afi_wvalid, afi_wlast}) //, afi_wid}) // output[0:0]
);
localparam [3:0] AFI_MUX_BUF_LATENCYM1 = AFI_MUX_BUF_LATENCY - 1;
dly_16 #(
.WIDTH(3)
.WIDTH(9) // 3)
) afi_wdata_i (
.clk (hclk), // input
.rst (!en), // input
.dly (AFI_MUX_BUF_LATENCYM1), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
.din ({wvalid, cur_chn}), // input[0:0]
.dout ({wdata_en,wdata_sel}) // output[0:0]
.din ({wvalid, cur_chn, afi_awid_r}), //}), // input[0:0]
.dout ({wdata_en, wdata_sel, afi_wid}) // }) // output[0:0]
);
cmd_deser #(
......@@ -467,7 +473,7 @@ items_left
.we (cmd_we) // output
);
wire [53:0] chunk_ptr_rd01; // [0:1];
wire [53:0] chunk_ptr_rd01; // [0:1]; // combines 2 pointers - write one and write responce one
cmprs_afi_mux_ptr cmprs_afi_mux_ptr_i (
.hclk (hclk), // input
......
includes/tasks_tests_memory.vh
View file @ 225fccd0
......@@ -133,8 +133,9 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
......@@ -145,6 +146,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
start64, lo_addr64, size64, $time);
mode= func_encode_mode_scanline(
disable_need,
repetitive,
single,
reset_frame,
......@@ -213,8 +215,9 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
......@@ -243,6 +246,7 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
disable_need,
repetitive,
single,
reset_frame,
......@@ -351,8 +355,10 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
......@@ -381,6 +387,7 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
disable_need,
repetitive,
single,
reset_frame,
......@@ -460,8 +467,9 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
......@@ -493,6 +501,7 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
disable_need,
repetitive,
single,
reset_frame,
......@@ -590,8 +599,9 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
......@@ -623,6 +633,7 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
disable_need,
repetitive,
single,
reset_frame,
......
includes/x393_parameters.vh
View file @ 225fccd0
......@@ -50,7 +50,7 @@
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
......@@ -200,7 +200,7 @@
// parameter CMD0_ADDR = 'h0800, // AXI write to command sequence memory
// parameter CMD0_ADDR_MASK = 'h1800, // AXI read address mask for the command sequence memory
parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
parameter MCNTRL_PS_MASK= 'h7e0, // both channels 0 and 1
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
parameter MCNTRL_PS_EN_RST= 'h0,
parameter MCNTRL_PS_CMD= 'h1,
......@@ -271,7 +271,9 @@
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h7f0,
......@@ -522,7 +524,7 @@
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter CMPRS_NUM_AFI_CHN = 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
parameter CMPRS_AFIMUX_RADDR0= 'h40, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
......@@ -658,7 +660,7 @@
// Command sequencers parameters
parameter CMDFRAMESEQ_ADDR_BASE= 'h780,
parameter CMDFRAMESEQ_ADDR_INC= 'h20,
parameter CMDFRAMESEQ_MASK= 'h3e0,
parameter CMDFRAMESEQ_MASK= 'h7e0,
parameter CMDFRAMESEQ_DEPTH = 64, // 32/64/128
parameter CMDFRAMESEQ_ABS = 0,
parameter CMDFRAMESEQ_REL = 16,
......
includes/x393_tasks_status.vh
View file @ 225fccd0
......@@ -113,6 +113,7 @@ endtask
task read_all_status;
begin
$display (" read_all_status @%t",$time);
read_status (MCONTR_PHY_STATUS_REG_ADDR);
read_status (MCONTR_TOP_STATUS_REG_ADDR);
read_status (MCNTRL_PS_STATUS_REG_ADDR);
......
memctrl/mcntrl393.v
View file @ 225fccd0
......@@ -50,7 +50,7 @@ module mcntrl393 #(
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
......@@ -166,7 +166,7 @@ module mcntrl393 #(
parameter CMD_DONE_BIT= 10,
//
parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
parameter MCNTRL_PS_MASK= 'h7e0, // both channels 0 and 1
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
parameter MCNTRL_PS_EN_RST= 'h0,
parameter MCNTRL_PS_CMD= 'h1,
......@@ -240,7 +240,8 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10 // read/write pages until disabled
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
) (
input rst_in,
......@@ -1057,7 +1058,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_linear_wr_sensor_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1121,7 +1123,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_tiled_rd_compressor_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1192,7 +1195,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_linear_rw_chn1_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1252,7 +1256,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_linear_rw_chn3_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1315,7 +1320,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_tiled_rw_chn2_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1382,7 +1388,9 @@ module mcntrl393 #(
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT)
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_tiled_rw_chn4_i (
.mrst (mrst), // input
.mclk (mclk), // input
......
memctrl/mcntrl_linear_rw.v
View file @ 225fccd0
......@@ -56,7 +56,8 @@ module mcntrl_linear_rw #(
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10 // read/write pages until disabled
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
)(
input mrst,
input mclk,
......@@ -149,7 +150,7 @@ module mcntrl_linear_rw #(
// wire cmd_wrmem; //=MCNTRL_SCANLINE_WRITE_MODE; // 0: read from memory, 1:write to memory
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
wire disable_need; // do not assert need, only want
wire repeat_frames; // mode bit
wire single_frame_w; // pulse
wire rst_frame_num_w;
......@@ -190,7 +191,7 @@ module mcntrl_linear_rw #(
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
reg [10:0] mode_reg;//mode register: {repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [11:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
......@@ -232,7 +233,7 @@ module mcntrl_linear_rw #(
// Set parameter registers
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[10:0]; // 4:0]; // [4:0];
else if (set_mode_w) mode_reg <= cmd_data[11:0]; // 4:0]; // [4:0];
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
......@@ -335,6 +336,7 @@ module mcntrl_linear_rw #(
assign cmd_wrmem = mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory
assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we;
......@@ -449,7 +451,7 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem;
if (mrst) need_r <= 0;
if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
......
memctrl/mcntrl_tiled_rw.v
View file @ 225fccd0
......@@ -63,7 +63,9 @@ module mcntrl_tiled_rw#(
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10 // read/write pages until disabled
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
)(
input mrst,
input mclk,
......@@ -161,7 +163,7 @@ module mcntrl_tiled_rw#(
wire cmd_wrmem; //= MCNTRL_TILED_WRITE_MODE; // 0: read from memory, 1:write to memory (change to parameter?)
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
wire byte32; // use 32-byte wide colums in each tile (0 - use 16-byte ones)
wire disable_need; // do not assert need, only want
wire repeat_frames; // mode bit
wire single_frame_w; // pulse
wire rst_frame_num_w;
......@@ -211,7 +213,7 @@ module mcntrl_tiled_rw#(
// reg [5:0] mode_reg;//mode register: {write_mode,keep_open,extra_pages[1:0],enable,!reset}
// reg [6:0] mode_reg;//mode register: {byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [10:0] mode_reg;//mode register: {repet,single,rst_frame,na,byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [11:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na,byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [LAST_FRAME_BITS-1:0] last_frame_number;
......@@ -266,7 +268,7 @@ module mcntrl_tiled_rw#(
// Set parameter registers
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[10:0]; // [5:0];
else if (set_mode_w) mode_reg <= cmd_data[11:0]; // [5:0];
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
......@@ -382,7 +384,7 @@ module mcntrl_tiled_rw#(
assign keep_open= mode_reg[MCONTR_LINTILE_KEEP_OPEN]; // keep banks open (will be used only if number of rows <= 8
assign byte32= mode_reg[MCONTR_LINTILE_BYTE32]; // use 32-byte wide columns in each tile (false - 16-byte)
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign status_data= {frame_finished_r, busy_r};
assign pgm_param_w= cmd_we;
assign rowcol_inc= frame_full_width;
......@@ -487,16 +489,16 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (mrst) xfer_start32_wr_r <= 0;
else xfer_start32_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && byte32;
if (mrst) continued_tile <= 1'b0;
if (mrst) continued_tile <= 1'b0;
else if (chn_rst) continued_tile <= 1'b0;
else if (frame_start_r[0]) continued_tile <= 1'b0;
else if (xfer_start_r[0]) continued_tile <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change
if (mrst) need_r <= 0;
if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
if (mrst) want_r <= 0;
if (mrst) want_r <= 0;
else if (chn_rst || xfer_grant) want_r <= 0;
else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
......
memctrl/memctrl16.v
View file @ 225fccd0
......@@ -25,7 +25,7 @@
module memctrl16 #(
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
......
memctrl/phy/mcontr_sequencer.v
View file @ 225fccd0
......@@ -24,7 +24,7 @@ module mcontr_sequencer #(
//command interface parameters
//0x1080..10ff - 8- bit data - to set various delay values
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
// 0x1080..109f - set delay for SDD0-SDD7
// 0x10a0..10bf - set delay for SDD8-SDD15
// 0x10c0..10df - set delay for SD_CMDA
......
simulation_modules/simul_axi_hp_wr.v
View file @ 225fccd0
......@@ -111,6 +111,7 @@ Alex
wire enough_data; // enough data to start a new burst
wire [11:3] next_wr_address; // bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit)
reg [31:0] write_address;
reg [5:0] awid_r; // awid registered with write_address
wire fifo_wd_rd; // read data fifo
wire last_confirmed_write;
......@@ -131,6 +132,7 @@ Alex
reg [ 1:0] wburst; // registered burst type
reg [ 3:0] wlen; // registered awlen type (for wrapped over transfers)
wire start_write_burst_w;
reg start_write_burst_r; // next after start_write_burst_w
wire write_in_progress_w; // should go inactive last confirmed upstream cycle
reg write_in_progress;
reg [ 7:0] num_full_data = 0; // Number of full data bursts in FIFO
......@@ -229,29 +231,31 @@ Alex
assign sim_wr_stb=wstrb_out;
always @ (posedge aclk) begin
if (start_write_burst_w) begin
if (awid_out != wid_out) begin
$display ("%m: at time %t ERROR: awid=%h, awid=%h",$time,awid_out,wid_out);
// $stop;
start_write_burst_r <= start_write_burst_w;
if (start_write_burst_r) begin
if (awid_r != wid_out) begin
$display ("%m: at time %t ERROR: awid=%h, wid=%h",$time,awid_out,wid_out);
$stop;
end
end
if (start_write_burst_w) begin
if (awsize_out != 2'h3) begin
$display ("%m: at time %t ERROR: awsize_out=%h, currently only 'h3 (8 bytes) is valid",$time,awsize_out);
// $stop;
$stop;
end
end
if (awvalid && awready) begin
if (((awlock ^ VALID_AWLOCK) & VALID_AWLOCK_MASK) != 0) begin
$display ("%m: at time %t ERROR: awlock = %h, valid %h with mask %h",$time, awlock, VALID_AWLOCK, VALID_AWLOCK_MASK);
// $stop;
$stop;
end
if (((awcache ^ VALID_AWCACHE) & VALID_AWCACHE_MASK) != 0) begin
$display ("%m: at time %t ERROR: awcache = %h, valid %h with mask %h",$time, awcache, VALID_AWCACHE, VALID_AWCACHE_MASK);
// $stop;
$stop;
end
if (((awprot ^ VALID_AWPROT) & VALID_AWPROT_MASK) != 0) begin
$display ("%m: at time %t ERROR: awprot = %h, valid %h with mask %h",$time, awprot, VALID_AWPROT, VALID_AWPROT_MASK);
// $stop;
$stop;
end
end
end
......@@ -276,6 +280,9 @@ Alex
else if (start_write_burst_w) write_address <= awaddr_out; // precedence over inc
else if (fifo_wd_rd) write_address <= {write_address[31:12],next_wr_address[11:3],write_address[2:0]};
if (rst) awid_r <= 6'bx;
else if (start_write_burst_w) awid_r <= awid_out; // precedence over inc
end
......@@ -304,7 +311,7 @@ fifo_same_clock_fill #( .DATA_WIDTH(79),.DATA_DEPTH(7))
.sync_rst (1'b0),
.we(wvalid && wready),
.re(fifo_wd_rd), //start_write_burst_w), // wrong
.data_in({wlast, wid[5:0], wstrb[7:0], wdata[63:0]}),
.data_in({wlast, wid[5:0], wstrb[7:0], wdata[63:0]}),
.data_out({wlast_out,wid_out[5:0], wstrb_out[7:0], wdata_out[63:0]}),
.nempty(w_nempty),
.half_full(), //w_half_full),
......
simulation_modules/simul_saxi_gp_wr.v
View file @ 225fccd0
......@@ -191,7 +191,7 @@ Alex
always @ (posedge aclk) begin
if (start_write_burst_w) begin
if (awid_out != wid_out) begin
$display ("%m: at time %t ERROR: awid=%h, awid=%h",$time,awid_out,wid_out);
$display ("%m: at time %t ERROR: awid=%h, wid=%h",$time,awid_out,wid_out);
$stop;
end
......
timing/camsync393.v
View file @ 225fccd0
......@@ -550,10 +550,10 @@ module camsync393 #(
else dly_cntr_chn3[31:0] <= input_dly_chn3[31:0];
/// bypass delay to trig_r in internal trigger mode
trig_r[0] <= (input_use_intern && (master_chn ==0)) ? (start_late && start_en):(dly_cntr_run_d[0] && !dly_cntr_run[0]);
trig_r[1] <= (input_use_intern && (master_chn ==1)) ? (start_late && start_en):(dly_cntr_run_d[1] && !dly_cntr_run[1]);
trig_r[2] <= (input_use_intern && (master_chn ==2)) ? (start_late && start_en):(dly_cntr_run_d[2] && !dly_cntr_run[2]);
trig_r[3] <= (input_use_intern && (master_chn ==3)) ? (start_late && start_en):(dly_cntr_run_d[3] && !dly_cntr_run[3]);
trig_r[0] <= (input_use_intern && (master_chn ==0)) ? (start_late && start_en): dly_cntr_end[0];
trig_r[1] <= (input_use_intern && (master_chn ==1)) ? (start_late && start_en): dly_cntr_end[1];
trig_r[2] <= (input_use_intern && (master_chn ==2)) ? (start_late && start_en): dly_cntr_end[2];
trig_r[3] <= (input_use_intern && (master_chn ==3)) ? (start_late && start_en): dly_cntr_end[3];
/// 64-bit serial receiver (52 bit payload, 6 pre magic and 6 bits post magic for error checking
if (!rcv_run_or_deaf) bit_rcv_duration[7:0] <= bit_length_short[7:0]; // 3/4 bit length-1
......
util_modules/cmd_frame_sequencer.v
View file @ 225fccd0
......@@ -43,7 +43,7 @@
module cmd_frame_sequencer#(
parameter CMDFRAMESEQ_ADDR= 'h780,
parameter CMDFRAMESEQ_MASK= 'h3e0,
parameter CMDFRAMESEQ_MASK= 'h7e0,
parameter AXI_WR_ADDR_BITS = 14,
parameter CMDFRAMESEQ_DEPTH = 64, // 32/64/128
parameter CMDFRAMESEQ_ABS = 0,
......
wrap/idelay_fine_pipe.v
View file @ 225fccd0
......@@ -45,8 +45,13 @@ module idelay_fine_pipe
else if (set) fdly <= fdly_pre;
end
`ifdef SIMULATION
reg [7:0] delay_r;
always @ (posedge clk) begin
if (rst) delay_r <= DELAY_VALUE;
else if (ld) delay_r <= delay;
end
always @ (fdly_pre) begin
if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);
if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d (0x%x) @ %t", delay_r, fdly_pre,$time);
end
`endif // SIMULATION
`ifndef IGNORE_ATTR
......
wrap/odelay_fine_pipe.v
View file @ 225fccd0
......@@ -44,8 +44,13 @@ module odelay_fine_pipe
else if (set) fdly <= fdly_pre;
end
`ifdef SIMULATION
reg [7:0] delay_r;
always @ (posedge clk) begin
if (rst) delay_r <= DELAY_VALUE;
else if (ld) delay_r <= delay;
end
always @ (fdly_pre) begin
if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);
if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d (0x%x) @ %t", fdly_pre, delay_r,$time);
end
`endif //SIMULATION
......
x393.v
View file @ 225fccd0
......@@ -1064,6 +1064,7 @@ assign axi_grst = axi_rst_pre;
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.BUFFER_DEPTH32 (BUFFER_DEPTH32),
.RSEL (RSEL),
.WSEL (WSEL)
......@@ -1964,7 +1965,7 @@ assign axi_grst = axi_rst_pre;
.data_out_stb (logger_stb), // output @mclk
.debug_state() // output[31:0]
);
/* Instance template for module mult_saxi_wr_inbuf */
mult_saxi_wr_inbuf #(
.MULT_SAXI_HALF_BRAM_IN (MULT_SAXI_HALF_BRAM_IN),
.MULT_SAXI_BSLOG (MULT_SAXI_BSLOG0),
......
x393_testbench02.tf
View file @ 225fccd0
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