outputcmprs_en_extend,// @mclk keep compressor enabled for graceful shutdown
inputcmprs_run,// @mclk enable propagation of vsync_late to frame_start_dst in bonded(sync to src) mode
inputcmprs_standalone,// @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode.
// cmprs_run should be off
inputsigle_frame_buf,// memory controller uses a single frame buffer (frame_number_* == 0), use other sync
inputvsync_late,// @xclk delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands
// that should arrive before it
inputframe_started,// @xclk started first macroblock (checking for broken frames)
outputframe_start_dst,// @mclk - trigger receive (tiled) memory channel (it will take care of single/repetitive
// this output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory)
input[FRAME_HEIGHT_BITS-1:0]line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
input[LAST_FRAME_BITS-1:0]frame_number_src,// current frame number (for multi-frame ranges) in the source (sensor) channel
inputframe_done_src,// single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// frame_done_src is later than line_unfinished_src/ frame_number_src changes
// Used withe a single-frame buffers
input[FRAME_HEIGHT_BITS-1:0]line_unfinished,// number of the current (unfinished ) line in this (compressor) channel
input[LAST_FRAME_BITS-1:0]frame_number,// current frame number (for multi-frame ranges) in this (compressor channel
inputframe_done,// input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
outputregsuspend,// suspend reading data for this channel - waiting for the source data
outputregbroken_frame// next frame start came before previous frame was read to compressor
);
wirevsync_late_mclk;// single mclk cycle, reclocked from vsync_late
wireframe_started_mclk;
regbonded_mode;
regframe_start_dst_r;
regframes_differ;// src and dest point to different frames (single-frame buffer mode), disregard line_unfinished_*
regframes_numbers_differ;// src and dest point to different frames (multi-frame buffer mode), disregard line_unfinished_*
regline_numbers_sync;// src unfinished line number is > this unfinished line number
regreading_frame;// compressor is reading frame data (make sure input is done before starting next frame, otherwise make it a broken frame
// s ynthesis attribute use_sync_set of stuffer is no;
// s ynthesis attribute use_sync_reset of stuffer is no;
// s ynthesis attribute use_clock_enable of stuffer is no;
// TODO:
// 1: Add FIFO buffer - with hclk on the read side
// 2: Get rid of imgptr - read addresses from the AFI module
// 3 Add multi-word status transmitter or just status transmit module for each compressor channel (29 bits are OK to read in multiple of 32-byte blocks
// Or make FIFO outside of the stuffer?
modulestuffer393(
inputclk,// 2x pixel clock
inputen,// enable, 0- reset
inputclk,// 2x pixel clock
inputen,// enable, 0- reset
inputreset_data_counters,// reset data transfer counters (only when DMA and compressor are disabled)
inputflush,// flush output data (fill byte with 0, long word with 0
inputstb,// input data strobe
input[3:0]dl,// [3:0] number of bits to send (0 - 16) ??
input[15:0]d,// [15:0] input data to shift (only lower bits are valid)
inputflush,// flush output data (fill byte with 0, long word with 0
inputstb,// input data strobe
input[3:0]dl,// [3:0] number of bits to send (0 - 16) ??
input[15:0]d,// [15:0] input data to shift (only lower bits are valid)
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current froma, but before the next one
// and before the data is needed for output
inputcolor_first,//
input[31:0]sec,// [31:0] number of seconds
input[19:0]usec,// [19:0] number of microseconds
outputrdy,// enable huffman encoder to proceed. Used as CE for many huffman encoder registers
outputreg[15:0]q,// [15:0] output data
outputregqv,// output data valid
outputdone,// reset by !en, goes high after some delay after flushing
outputreg[23:0]imgptr,// [23:0]image pointer in 32-byte chunks
input[31:0]sec,// [31:0] number of seconds
input[19:0]usec,// [19:0] number of microseconds
outputrdy,// enable huffman encoder to proceed. Used as CE for many huffman encoder registers
// outputs @ negedge clk
outputreg[15:0]q,// [15:0] output data
outputregqv,// output data valid
outputdone,// reset by !en, goes high after some delay after flushing
outputreg[23:0]imgptr,// [23:0]image pointer in 32-byte chunks
outputregflushing
`ifdefdebug_stuffer
,outputreg[3:0]etrax_dma_r,// [3:0] just for testing
...
...
@@ -68,7 +73,7 @@ module stuffer393 (
`endif
reg[23:1]stage1;// stage 1 register (after right-shifting input data by 0..7 - actually left by 7..0)
wire[2:0]shift1;// shift amount for stage 1
wire[2:0]shift1;// shift amount for stage 1
reg[4:0]stage1_bits;// number of topmost invalid bits in stage1 register - 2 MSBs, use lower 3 stage2_bits
reg[4:0]stage1_length;// number of bits (1..16) in stage 1 register
