making previous simulation tasks run on the full x393 code

.settings/com.elphel.vdt.iverilog.prefs

-com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->
+com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->
 eclipse.preferences.version=1
+iverilog_100_TopModulesOther=glbl<-@\#\#@->
+iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
+iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
 iverilog_77_Param_Exe=/usr/local/bin/iverilog
 iverilog_78_VVP_Exe=/usr/local/bin/vvp
 iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave

axi/cmprs_afi_mux.v

@@ -32,7 +32,7 @@ module  cmprs_afi_mux#(
     parameter CMPRS_AFIMUX_STATUS_REG_ADDR=     'h20,  //Uses 4 locations TODO: assign valid address
     parameter CMPRS_AFIMUX_WIDTH =              26, // maximal for status: currently only works with 26)
     parameter CMPRS_AFIMUX_CYCBITS =            3,
-    parameter AFI_MUX_BUF_LATENCY =             2  // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
+    parameter AFI_MUX_BUF_LATENCY =             4'd2  // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
 )(
 //    input                         rst,
     input                         mclk, // for command/status
@@ -370,13 +370,13 @@ module  cmprs_afi_mux#(
         .din       ({    wvalid,     wlast, afi_awid}), // input[0:0] 
         .dout      ({afi_wvalid, afi_wlast, afi_wid}) // output[0:0] 
     );
-
+    localparam [3:0] AFI_MUX_BUF_LATENCYM1 = AFI_MUX_BUF_LATENCY - 1;
     dly_16 #(
         .WIDTH(3)
     ) afi_wdata_i (
         .clk       (hclk), // input
         .rst       (!en),  // input
-        .dly       (AFI_MUX_BUF_LATENCY-1), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3) 
+        .dly       (AFI_MUX_BUF_LATENCYM1), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3) 
         .din       ({wvalid, cur_chn}), // input[0:0] 
         .dout      ({wdata_en,wdata_sel}) // output[0:0] 
     );

compressor_jp/cmprs_buf_average.v

@@ -295,10 +295,10 @@ module  cmprs_buf_average#(
     end    
     
     // delay from the start of data output from color converter to copy subtract_dc to be valid when average values are set
-    dly_16 #(.WIDTH(1)) i_cs_first_out_late (.clk(xclk),.rst(1'b0), .dly(15), .din(cs_first_out), .dout(cs_first_out_late));
-    dly_16 #(.WIDTH(1)) i_color_enable_d    (.clk(xclk),.rst(1'b0), .dly( 1), .din(color_enable), .dout(color_enable_d));
-    dly_16 #(.WIDTH(1)) i_dv                (.clk(xclk),.rst(1'b0), .dly( 2), .din(dv_pre3),      .dout(dv));
-    dly_16 #(.WIDTH(1)) i_ds                (.clk(xclk),.rst(1'b0), .dly( 2), .din(ds_pre3),      .dout(ds));
+    dly_16 #(.WIDTH(1)) i_cs_first_out_late (.clk(xclk),.rst(1'b0), .dly(4'd15), .din(cs_first_out), .dout(cs_first_out_late));
+    dly_16 #(.WIDTH(1)) i_color_enable_d    (.clk(xclk),.rst(1'b0), .dly( 4'd1), .din(color_enable), .dout(color_enable_d));
+    dly_16 #(.WIDTH(1)) i_dv                (.clk(xclk),.rst(1'b0), .dly( 4'd2), .din(dv_pre3),      .dout(dv));
+    dly_16 #(.WIDTH(1)) i_ds                (.clk(xclk),.rst(1'b0), .dly( 4'd2), .din(ds_pre3),      .dout(ds));
 
     cmprs_tile_mode2_decode #(
         .CMPRS_COLOR18   (CMPRS_COLOR18),

compressor_jp/compressor393.v

@@ -110,7 +110,7 @@ module  compressor393 # (
     
         parameter CMPRS_AFIMUX_WIDTH =         26, // maximal for status: currently only works with 26)
         parameter CMPRS_AFIMUX_CYCBITS =        3,
-        parameter AFI_MUX_BUF_LATENCY =         2  // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
+        parameter AFI_MUX_BUF_LATENCY =      4'd2  // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
 
 )(
 //    input                         rst,    // global reset
@@ -275,12 +275,12 @@ module  compressor393 # (
         .rq_in5      (status_rq_mux[5]),        // input
         .start_in5   (status_start_mux[5]),     // output
         
-        .db_in6      (0),                       // input[7:0] 
-        .rq_in6      (0),                       // input
+        .db_in6      (8'b0),                    // input[7:0] 
+        .rq_in6      (1'b0),                    // input
         .start_in6   (),                        // output
         
-        .db_in7      (0),                       // input[7:0] 
-        .rq_in7      (0),                       // input
+        .db_in7      (8'b0),                    // input[7:0] 
+        .rq_in7      (1'b0),                    // input
         .start_in7   (),                        // output
         
         .db_out      (status_ad),               // output[7:0] 
@@ -451,16 +451,16 @@ module  compressor393 # (
                 .fifo_count1      (fifo_count[8 +: 8]),     // input[7:0] 
                 .fifo_rst2        (),                       // output
                 .fifo_ren2        (),                       // output
-                .fifo_rdata2      (0),                      // input[63:0] 
+                .fifo_rdata2      (64'b0),                  // input[63:0] 
                 .eof_written2     (),                       // output
-                .fifo_flush2      (0),                      // input
-                .fifo_count2      (0),                      // input[7:0] 
+                .fifo_flush2      (1'b0),                   // input
+                .fifo_count2      (8'b0),                   // input[7:0] 
                 .fifo_rst3        (),                       // output
                 .fifo_ren3        (),                       // output
-                .fifo_rdata3      (0),                      // input[63:0] 
+                .fifo_rdata3      (64'b0),                  // input[63:0] 
                 .eof_written3     (),                       // output
-                .fifo_flush3      (0),                      // input
-                .fifo_count3      (0),                      // input[7:0] 
+                .fifo_flush3      (1'b0),                   // input
+                .fifo_count3      (8'b0),                   // input[7:0] 
                 .afi_awaddr       (afi0_awaddr),            // output[31:0] 
                 .afi_awvalid      (afi0_awvalid),           // output
                 .afi_awready      (afi0_awready),           // input
@@ -524,16 +524,16 @@ module  compressor393 # (
                 .fifo_count1      (fifo_count[24 +: 8]),     // input[7:0] 
                 .fifo_rst2        (),                       // output
                 .fifo_ren2        (),                       // output
-                .fifo_rdata2      (0),                      // input[63:0] 
+                .fifo_rdata2      (64'b0),                  // input[63:0] 
                 .eof_written2     (),                       // output
-                .fifo_flush2      (0),                      // input
-                .fifo_count2      (0),                      // input[7:0] 
+                .fifo_flush2      (1'b0),                   // input
+                .fifo_count2      (8'b0),                   // input[7:0] 
                 .fifo_rst3        (),                       // output
                 .fifo_ren3        (),                       // output
-                .fifo_rdata3      (0),                      // input[63:0] 
+                .fifo_rdata3      (64'b0),                  // input[63:0] 
                 .eof_written3     (),                       // output
-                .fifo_flush3      (0),                      // input
-                .fifo_count3      (0),                      // input[7:0] 
+                .fifo_flush3      (1'b0),                   // input
+                .fifo_count3      (8'b0),                   // input[7:0] 
                 .afi_awaddr       (afi1_awaddr),            // output[31:0] 
                 .afi_awvalid      (afi1_awvalid),           // output
                 .afi_awready      (afi1_awready),           // input

compressor_jp/csconvert18a.v

@@ -272,15 +272,15 @@ module csconvert18a(
   assign caddr =    caddr_r;
   assign cwe =      cwe_r;
   
-    dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(15), .din(pre_first_in), .dout(strt_dly[0]));
-    dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(15), .din(strt_dly[0]),  .dout(strt_dly[1]));
-    dly_16 #(.WIDTH(1)) i_strt      (.clk(CLK),.rst(1'b0), .dly( 4), .din(strt_dly[1]),  .dout(strt));
+    dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(pre_first_in), .dout(strt_dly[0]));
+    dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(strt_dly[0]),  .dout(strt_dly[1]));
+    dly_16 #(.WIDTH(1)) i_strt      (.clk(CLK),.rst(1'b0), .dly( 4'd4), .din(strt_dly[1]),  .dout(strt));
   
 //  SRL16 i_strt_dly0  (.Q(strt_dly[0]),  .D(pre_first_in),                                  .CLK(CLK),   .A0(1'b1),  .A1(1'b1), .A2(1'b1), .A3(1'b1)); // dly=15+1
 //  SRL16 i_strt_dly1  (.Q(strt_dly[1]),  .D(strt_dly[0]),                                   .CLK(CLK),   .A0(1'b1),  .A1(1'b1), .A2(1'b1), .A3(1'b1)); // dly=15+1
 //  SRL16 i_strt       (.Q(strt),         .D(strt_dly[1]),                                   .CLK(CLK),   .A0(1'b0),  .A1(1'b0), .A2(1'b1), .A3(1'b0)); // dly=4+1
-    dly_16 #(.WIDTH(1)) i_ystrt   (.clk(CLK),.rst(1'b0), .dly(5), .din(strt), .dout(ystrt));
-    dly_16 #(.WIDTH(1)) i_nxtline (.clk(CLK),.rst(1'b0), .dly(1), .din(!RST && ywe_r && (yaddr_r[3:0]==4'hf) && (yaddr_r[7:4]!=4'hf)), .dout(nxtline));
+    dly_16 #(.WIDTH(1)) i_ystrt   (.clk(CLK),.rst(1'b0), .dly(4'd5), .din(strt), .dout(ystrt));
+    dly_16 #(.WIDTH(1)) i_nxtline (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(!RST && ywe_r && (yaddr_r[3:0]==4'hf) && (yaddr_r[7:4]!=4'hf)), .dout(nxtline));
 
 //  SRL16 i_ystrt  (.Q(ystrt),  .D(strt),                                                    .CLK(CLK),   .A0(1'b1),  .A1(1'b0), .A2(1'b1), .A3(1'b0));	// dly=5+1
 //  SRL16 i_nxtline(.Q(nxtline),.D(!RST && ywe_r && (yaddr_r[3:0]==4'hf) && (yaddr_r[7:4]!=4'hf)), .CLK(CLK),   .A0(1'b1),  .A1(1'b0), .A2(1'b0), .A3(1'b0));	// dly=1+1
@@ -595,7 +595,7 @@ end
 // new, q is signed char
   assign q[8:0]=  ((cbcr[10]==cbcr[9]) && (!limit_diff || (cbcr[10]==cbcr[8])))? cbcr[9:1]: {cbcr[10],limit_diff?cbcr[10]:(~cbcr[10]),{7{~cbcr[10]}}};
 
-dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(1), .din(ywe_r), .dout(cwe0));
+dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(ywe_r), .dout(cwe0));
 //SRL16 i_cwe0    (.D(ywe_r ),  .Q(cwe0), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLK)); // dly=2=1+1
 
 always @ (posedge CLK) begin

compressor_jp/focus_sharp393.v

@@ -218,8 +218,8 @@ module focus_sharp393(
 
 //    SRL16 i_out_mono   (.Q(out_mono),   .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(started_luma)); // timing not critical
 //    SRL16 i_out_window (.Q(out_window), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(in_woi)); // timing not critical
-    dly_16 #(.WIDTH(1)) i_out_mono(.clk(clk),  .rst(1'b0), .dly(15), .din(started_luma), .dout(out_mono));    // timing not critical
-    dly_16 #(.WIDTH(1)) i_out_window(.clk(clk),.rst(1'b0), .dly(15), .din(in_woi),       .dout(out_window));    // timing not critical
+    dly_16 #(.WIDTH(1)) i_out_mono(.clk(clk),  .rst(1'b0), .dly(4'd15), .din(started_luma), .dout(out_mono));    // timing not critical
+    dly_16 #(.WIDTH(1)) i_out_window(.clk(clk),.rst(1'b0), .dly(4'd15), .din(in_woi),       .dout(out_window));    // timing not critical
     
     always @ (posedge clk) begin
         if (start) started_luma <= !tn[2];

compressor_jp/jp_channel.v

@@ -702,7 +702,7 @@ module  jp_channel#(
         .d_out              (dct_out)              // output[12:0] 
     );
     wire          quant_start;
-    dly_16 #(.WIDTH(1)) i_quant_start (.clk(xclk),.rst(1'b0), .dly(0), .din(dct_pre_first_out), .dout(quant_start));    // dly=0+1
+    dly_16 #(.WIDTH(1)) i_quant_start (.clk(xclk),.rst(1'b0), .dly(4'd0), .din(dct_pre_first_out), .dout(quant_start));    // dly=0+1
  
     
     always @ (posedge xclk) begin

compressor_jp/quantizer393.v

@@ -253,7 +253,7 @@ module quantizer393(
     dly_16 #(.WIDTH(1)) i_hfc_en (
         .clk(clk),
         .rst(1'b0),
-        .dly(1),
+        .dly(4'd1),
         .din(((tba[2:0]>hfc_sel[2:0]) || (tba[5:3]>hfc_sel[2:0])) && dcc_run && !ctype_prev[0]),
         .dout(hfc_en));   // dly=1+1
 

compressor_jp/stuffer393.v

@@ -412,7 +412,7 @@ end
     assign start_time_out= qv && trailer && (etrax_dma[3:0]== 4'h8) && !size_out_over;
     assign start_sizeout= time_out && (etrax_dma[3:0]== 4'hc);
 // SRL16_1 i_pre_flush_end_delayed (.D(size_out[1]),.Q(pre_flush_end_delayed), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk)); // dly=3+1    // rather arbitrary?
-    dly_16 #(.WIDTH(1)) i_pre_flush_end_delayed(.clk(~clk),.rst(1'b0), .dly(14), .din(size_out[1]), .dout(pre_flush_end_delayed));    // dly=14+1 // rather arbitrary?
+    dly_16 #(.WIDTH(1)) i_pre_flush_end_delayed(.clk(~clk),.rst(1'b0), .dly(4'd14), .din(size_out[1]), .dout(pre_flush_end_delayed));    // dly=14+1 // rather arbitrary?
     assign done = flush_end_delayed;
 
     // extract strart of frame run from different clock, re-clock from the source

compressor_jp/xdct393.v

@@ -236,14 +236,14 @@ This value divided by 2raised to 8 is equivalent to ignoring the 8 lsb bits of t
     wire          sxregs_d8;
     reg           enable_toggle;
 //  SRL16_1 i_sxregs_d8   (.Q(sxregs_d8), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk),.D(sxregs));    // dly=7+1
-    dly_16 #(.WIDTH(1)) i_sxregs_d8(.clk(nclk),.rst(1'b0), .dly(7), .din(sxregs), .dout(sxregs_d8));   // dly=7+1
+    dly_16 #(.WIDTH(1)) i_sxregs_d8(.clk(nclk),.rst(1'b0), .dly(4'd7), .din(sxregs), .dout(sxregs_d8));   // dly=7+1
     
     
 // SRL16_1 i_pre_sxregs (.Q(pre_sxregs), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk), .D(start));    // dly=6+1
-    dly_16 #(.WIDTH(1)) i_pre_sxregs(.clk(nclk),.rst(1'b0), .dly(6), .din(start), .dout(pre_sxregs));    // dly=6+1
+    dly_16 #(.WIDTH(1)) i_pre_sxregs(.clk(nclk),.rst(1'b0), .dly(4'd6), .din(start), .dout(pre_sxregs));    // dly=6+1
     
 // SRL16_1 i_enwe       (.Q(enwe), .A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(clk), .D(pre_sxregs));    // dly=5+1
-    dly_16 #(.WIDTH(1)) i_enwe(.clk(nclk),.rst(1'b0), .dly(5), .din(pre_sxregs), .dout(enwe));    // dly=5+1
+    dly_16 #(.WIDTH(1)) i_enwe(.clk(nclk),.rst(1'b0), .dly(4'd5), .din(pre_sxregs), .dout(enwe));    // dly=5+1
   
     always @ (posedge nclk) begin
         enable_toggle <= en && (sxregs || (enable_toggle && !sxregs_d8));
@@ -463,16 +463,16 @@ module dct393_stage2 (
     
 
 // SRL16 i_endv       (.Q(endv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(start));    // dly=14+1
-    dly_16 #(.WIDTH(1)) i_endv(.clk(clk),.rst(1'b0), .dly(14), .din(start), .dout(endv));    // dly=14+1
+    dly_16 #(.WIDTH(1)) i_endv(.clk(clk),.rst(1'b0), .dly(4'd14), .din(start), .dout(endv));    // dly=14+1
  
 // SRL16 i_disdv      (.Q(disdv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(rd_cntr[5:0]==6'h3f));    // dly=14+1
-    dly_16 #(.WIDTH(1)) i_disdv(.clk(clk),.rst(1'b0), .dly(14), .din(rd_cntr[5:0]==6'h3f), .dout(disdv));    // dly=14+1
+    dly_16 #(.WIDTH(1)) i_disdv(.clk(clk),.rst(1'b0), .dly(4'd14), .din(rd_cntr[5:0]==6'h3f), .dout(disdv));    // dly=14+1
 
 // SRL16 i_sxregs      (.Q(sxregs),    .A0(1'b0), .A1(1'b0), .A2(1'b0), .A3(1'b1), .CLK(clk),.D((rd_cntr[5:3]==3'h0) && en_started));    // dly=8+1
-    dly_16 #(.WIDTH(1)) i_sxregs(.clk(clk),.rst(1'b0), .dly(8), .din((rd_cntr[5:3]==3'h0) && en_started), .dout(sxregs));    // dly=8+1
+    dly_16 #(.WIDTH(1)) i_sxregs(.clk(clk),.rst(1'b0), .dly(4'd8), .din((rd_cntr[5:3]==3'h0) && en_started), .dout(sxregs));    // dly=8+1
 
 // SRL16 i_sxregs_d8   (.Q(sxregs_d8), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk),.D(sxregs && en_started));    // dly=7+1
-    dly_16 #(.WIDTH(1)) i_sxregs_d8(.clk(clk),.rst(1'b0), .dly(7), .din(sxregs && en_started), .dout(sxregs_d8));    // dly=7+1
+    dly_16 #(.WIDTH(1)) i_sxregs_d8(.clk(clk),.rst(1'b0), .dly(4'd7), .din(sxregs && en_started), .dout(sxregs_d8));    // dly=7+1
 
     always @ (posedge clk) begin 
         enable_toggle <= en && (sxregs || (enable_toggle && !sxregs_d8));

includes/x393_parameters.vh

@@ -256,6 +256,17 @@
     parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
     parameter BUFFER_DEPTH32=                10,   // Block rum buffer depth on a 32-bit port
 
+    // bits in mode control word
+    parameter MCONTR_LINTILE_NRESET =              0, // reset if 0
+    parameter MCONTR_LINTILE_EN =                  1, // enable requests 
+    parameter MCONTR_LINTILE_WRITE =               2, // write to memory mode
+    parameter MCONTR_LINTILE_EXTRAPG =             3, // extra pages (over 1) needed by the client simultaneously
+    parameter MCONTR_LINTILE_EXTRAPG_BITS =        2, // number of bits to use for extra pages
+    parameter MCONTR_LINTILE_KEEP_OPEN =           5, // keep banks open (will be used only if number of rows <= 8)
+    parameter MCONTR_LINTILE_BYTE32 =              6, // use 32-byte wide columns in each tile (false - 16-byte) 
+    parameter MCONTR_LINTILE_RST_FRAME =           8, // reset frame number 
+    parameter MCONTR_LINTILE_SINGLE =              9, // read/write a single page 
+    parameter MCONTR_LINTILE_REPEAT =             10,  // read/write pages until disabled 
 // Channel test module parameters
     parameter MCNTRL_TEST01_ADDR=                 'h0f0,
     parameter MCNTRL_TEST01_MASK=                 'h7f0,
@@ -389,7 +400,7 @@
     //sensor_fifo parameters
     parameter SENSOR_DATA_WIDTH =        12,
     parameter SENSOR_FIFO_2DEPTH =       4,
-    parameter SENSOR_FIFO_DELAY =        7,
+    parameter SENSOR_FIFO_DELAY =        4'd7,
     // other parameters for histogram_saxi module
     parameter HIST_SAXI_ADDR_MASK =      'h7f0,
       parameter HIST_SAXI_MODE_WIDTH =   8,
@@ -542,9 +553,9 @@
 
     parameter CMPRS_AFIMUX_WIDTH =         26, // maximal for status: currently only works with 26)
     parameter CMPRS_AFIMUX_CYCBITS =        3,
-    parameter AFI_MUX_BUF_LATENCY =         2,  // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
+    parameter AFI_MUX_BUF_LATENCY =      4'd2,  // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
     // GPIO control : 'h700..'h701, status: 'h30
-    parameter integer GPIO_DRIVE =        12,
+    parameter integer GPIO_DRIVE =         12,
     parameter GPIO_ADDR =                 'h700, // .701
     parameter GPIO_MASK =                 'h7fe,
     parameter GPIO_STATUS_REG_ADDR =      'h30,  // address where status can be read out (10 GPIO inputs)

includes/x393_simulation_parameters.vh

@@ -25,4 +25,9 @@
     parameter integer AXI_TASK_HOLD=1.0,
     
 //    parameter [1:0] DEFAULT_STATUS_MODE=3,
-    parameter       SIMUL_AXI_READ_WIDTH=16
\ No newline at end of file
+    parameter       SIMUL_AXI_READ_WIDTH=16,
+    
+    parameter       MEMCLK_PERIOD = 5.0,
+    parameter       FCLK0_PERIOD = 10.417,
+    parameter       FCLK1_PERIOD =  0.0
+    
\ No newline at end of file

includes/x393_tasks_mcntrl_buffers.vh

@@ -69,7 +69,7 @@ task write_block_incremtal;
                     i,        // id
                     start_value+i+j,
                     4'hf, // wstrb
-                    (j == 15) ? 1 : 0 // last
+                    (j == 15) ? 1'b1 : 1'b0 // last
                     );
                 $display(" Write block incremental (addr:data): 0x%08x:0x%x @%t", (i + j), start_value+i+j, $time);
             end
@@ -122,7 +122,7 @@ task write_block_buf;
                     i,        // id
                     (i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24),
                     4'hf, // wstrb
-                    (j == 15) ? 1 : 0 // last
+                    (j == 15) ? 1'b1 : 1'b0 // last
                     );
                 $display(" Write block data (addr:data): 0x%08x:0x%x @%t", (i + j),
                     (i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24), $time);

input_data/focus_filt.dat

+   0000  0111  0444  0888  0fff  0fff  0888  0000
+   0111  0111  0444  0888  0fff  0fff  0888  0000
+   0444  0444  0888  0fff  0fff  0888  0444  0000
+   0888  0888  0fff  0fff  0888  0444  0222  0000
+   0fff  0fff  0fff  0888  0444  0222  0111  0000
+   0fff  0fff  0888  0444  0222  0111  0000  0000
+   0888  0888  0444  0222  0111  0000  0000  0000
+   0000  0000  0000  0000  0000  0000  0000  0000
+
+   0000  1111  4444  8888  ffff  ffff  8888  0000
+   1111  1111  4444  8888  ffff  ffff  8888  0000
+   4444  4444  8888  ffff  ffff  8888  4444  0000
+   8888  8888  ffff  ffff  8888  4444  2222  0000
+   ffff  ffff  ffff  8888  4444  2222  1111  0000
+   ffff  ffff  8888  4444  2222  1111  0000  0000
+   8888  8888  4444  2222  1111  0000  0000  0000
+   0000  0000  0000  0000  0000  0000  0000  0000

input_data/gps_data.dat

+$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45
+$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B
+$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
+$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
+$GPRMC,042931.2,A,4043.39929,N,11155.92705,W,000.01,283.8,250411,013.2,E*45
+$GPGGA,042931.2,4043.39929,N,11155.92705,W,1,09,0.8,1280.5,M,-13.8,M,,*5A
+$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
+$GPVTG,283.8,T,270.5,M,000.01,N,0000.01,K*7F
+$GPRMC,042931.4,A,4043.39929,N,11155.92705,W,000.01,283.8,250411,013.2,E*43
+$GPGGA,042931.4,4043.39929,N,11155.92705,W,1,09,0.8,1280.5,M,-13.8,M,,*5C
+$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
+$GPVTG,283.8,T,270.5,M,000.01,N,0000.02,K*7C
+$GPRMC,042931.6,A,4043.39929,N,11155.92705,W,000.00,283.8,250411,013.2,E*40
+$GPGGA,042931.6,4043.39929,N,11155.92705,W,1,09,0.8,1280.5,M,-13.8,M,,*5E
+$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
+$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
+$GPRMC,042931.8,A,4043.39929,N,11155.92705,W,000.01,283.8,250411,013.2,E*4F
+$GPGGA,042931.8,4043.39929,N,11155.92705,W,1,09,0.8,1280.5,M,-13.8,M,,*50
+$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
+$GPVTG,283.8,T,270.5,M,000.01,N,0000.01,K*7F
+ 

input_data/huffman.dat

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+

input_data/linear1028rgb.dat

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\ No newline at end of file

input_data/motor.dat

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input_data/quantization_100.dat

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+
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+   2ab0   2000   1550   19a0   1550   1550   1740   19a0
+   1740   1740   13b0   1250    e40   1000   13b0   1250
+    f10   1250   1740   1740   1000    ba0   1000    f10
+    d80    cd0    c30    c30    c30   1550   1110    b20
+    ab0    ba0    cd0    ab0    e40    cd0    c30    cd0
+
+   5550   4000   4000   3330   4000   3330   1c70   3330
+   3330   1c70    cd0   13b0   1740   13b0    cd0    cd0
+    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
+    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
+    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
+    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
+    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
+    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
+

memctrl/mcntrl393.v

@@ -224,7 +224,19 @@ module  mcntrl393 #(
     parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)                                                     
     parameter BUFFER_DEPTH32=                10,    // Block RAM buffer depth on a 32-bit port
     parameter RSEL=                          1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
-    parameter WSEL=                          1'b0  // late/early WRITE commands (to adjust timing by 1 SDCLK period)
+    parameter WSEL=                          1'b0,  // late/early WRITE commands (to adjust timing by 1 SDCLK period)
+    // bits in mode control word
+    parameter MCONTR_LINTILE_NRESET =        0, // reset if 0
+    parameter MCONTR_LINTILE_EN =            1, // enable requests 
+    parameter MCONTR_LINTILE_WRITE =         2, // write to memory mode
+    parameter MCONTR_LINTILE_EXTRAPG =       3, // extra pages (over 1) needed by the client simultaneously
+    parameter MCONTR_LINTILE_EXTRAPG_BITS =  2, // number of bits to use for extra pages
+    parameter MCONTR_LINTILE_KEEP_OPEN =     5, // keep banks open (will be used only if number of rows <= 8)
+    parameter MCONTR_LINTILE_BYTE32 =        6, // use 32-byte wide columns in each tile (false - 16-byte) 
+    parameter MCONTR_LINTILE_RST_FRAME =     8, // reset frame number 
+    parameter MCONTR_LINTILE_SINGLE =        9, // read/write a single page 
+    parameter MCONTR_LINTILE_REPEAT =       10  // read/write pages until disabled 
+    
     ) (
     input                        rst_in,
     input                        clk_in,
@@ -1030,7 +1042,15 @@ module  mcntrl393 #(
                 .MCNTRL_SCANLINE_WINDOW_STARTXY    (MCNTRL_SCANLINE_WINDOW_STARTXY),
                 .MCNTRL_SCANLINE_STATUS_REG_ADDR   (MCONTR_SENS_STATUS_BASE + MCONTR_SENS_STATUS_INC * i),
                 .MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
-                .MCNTRL_SCANLINE_FRAME_PAGE_RESET  (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
+                .MCNTRL_SCANLINE_FRAME_PAGE_RESET  (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
+                .MCONTR_LINTILE_NRESET             (MCONTR_LINTILE_NRESET),
+                .MCONTR_LINTILE_EN                 (MCONTR_LINTILE_EN),
+                .MCONTR_LINTILE_WRITE              (MCONTR_LINTILE_WRITE),
+                .MCONTR_LINTILE_EXTRAPG            (MCONTR_LINTILE_EXTRAPG),
+                .MCONTR_LINTILE_EXTRAPG_BITS       (MCONTR_LINTILE_EXTRAPG_BITS),
+                .MCONTR_LINTILE_RST_FRAME          (MCONTR_LINTILE_RST_FRAME),
+                .MCONTR_LINTILE_SINGLE             (MCONTR_LINTILE_SINGLE),
+                .MCONTR_LINTILE_REPEAT             (MCONTR_LINTILE_REPEAT)
             ) mcntrl_linear_wr_sensor_i (
                 .mrst             (mrst),                       // input
                 .mclk             (mclk),                       // input
@@ -1082,7 +1102,17 @@ module  mcntrl393 #(
                 .MCNTRL_TILED_TILE_WHS         (MCNTRL_TILED_TILE_WHS),
                 .MCNTRL_TILED_STATUS_REG_ADDR  (MCONTR_CMPRS_STATUS_BASE + MCONTR_CMPRS_STATUS_INC * i),
                 .MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
-                .MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
+                .MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
+                .MCONTR_LINTILE_NRESET         (MCONTR_LINTILE_NRESET),
+                .MCONTR_LINTILE_EN             (MCONTR_LINTILE_EN),
+                .MCONTR_LINTILE_WRITE          (MCONTR_LINTILE_WRITE),
+                .MCONTR_LINTILE_EXTRAPG        (MCONTR_LINTILE_EXTRAPG),
+                .MCONTR_LINTILE_EXTRAPG_BITS   (MCONTR_LINTILE_EXTRAPG_BITS),
+                .MCONTR_LINTILE_KEEP_OPEN      (MCONTR_LINTILE_KEEP_OPEN),
+                .MCONTR_LINTILE_BYTE32         (MCONTR_LINTILE_BYTE32),
+                .MCONTR_LINTILE_RST_FRAME      (MCONTR_LINTILE_RST_FRAME),
+                .MCONTR_LINTILE_SINGLE         (MCONTR_LINTILE_SINGLE),
+                .MCONTR_LINTILE_REPEAT         (MCONTR_LINTILE_REPEAT)
             ) mcntrl_tiled_rd_compressor_i ( 
                 .mrst                 (mrst),                         // input
                 .mclk                 (mclk),                        // input
@@ -1143,7 +1173,15 @@ module  mcntrl393 #(
         .MCNTRL_SCANLINE_WINDOW_STARTXY    (MCNTRL_SCANLINE_WINDOW_STARTXY),
         .MCNTRL_SCANLINE_STATUS_REG_ADDR   (MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR),
         .MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
-        .MCNTRL_SCANLINE_FRAME_PAGE_RESET  (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
+        .MCNTRL_SCANLINE_FRAME_PAGE_RESET  (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
+        .MCONTR_LINTILE_NRESET             (MCONTR_LINTILE_NRESET),
+        .MCONTR_LINTILE_EN                 (MCONTR_LINTILE_EN),
+        .MCONTR_LINTILE_WRITE              (MCONTR_LINTILE_WRITE),
+        .MCONTR_LINTILE_EXTRAPG            (MCONTR_LINTILE_EXTRAPG),
+        .MCONTR_LINTILE_EXTRAPG_BITS       (MCONTR_LINTILE_EXTRAPG_BITS),
+        .MCONTR_LINTILE_RST_FRAME          (MCONTR_LINTILE_RST_FRAME),
+        .MCONTR_LINTILE_SINGLE             (MCONTR_LINTILE_SINGLE),
+        .MCONTR_LINTILE_REPEAT             (MCONTR_LINTILE_REPEAT)
     ) mcntrl_linear_rw_chn1_i (
         .mrst             (mrst), // input
         .mclk             (mclk), // input
@@ -1193,7 +1231,15 @@ module  mcntrl393 #(
         .MCNTRL_SCANLINE_WINDOW_STARTXY    (MCNTRL_SCANLINE_WINDOW_STARTXY),
         .MCNTRL_SCANLINE_STATUS_REG_ADDR   (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),
         .MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
-        .MCNTRL_SCANLINE_FRAME_PAGE_RESET  (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
+        .MCNTRL_SCANLINE_FRAME_PAGE_RESET  (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
+        .MCONTR_LINTILE_NRESET             (MCONTR_LINTILE_NRESET),
+        .MCONTR_LINTILE_EN                 (MCONTR_LINTILE_EN),
+        .MCONTR_LINTILE_WRITE              (MCONTR_LINTILE_WRITE),
+        .MCONTR_LINTILE_EXTRAPG            (MCONTR_LINTILE_EXTRAPG),
+        .MCONTR_LINTILE_EXTRAPG_BITS       (MCONTR_LINTILE_EXTRAPG_BITS),
+        .MCONTR_LINTILE_RST_FRAME          (MCONTR_LINTILE_RST_FRAME),
+        .MCONTR_LINTILE_SINGLE             (MCONTR_LINTILE_SINGLE),
+        .MCONTR_LINTILE_REPEAT             (MCONTR_LINTILE_REPEAT)
     ) mcntrl_linear_rw_chn3_i (
         .mrst             (mrst), // input
         .mclk             (mclk), // input
@@ -1245,7 +1291,16 @@ module  mcntrl393 #(
         .MCNTRL_TILED_TILE_WHS         (MCNTRL_TILED_TILE_WHS),
         .MCNTRL_TILED_STATUS_REG_ADDR  (MCNTRL_TILED_STATUS_REG_CHN2_ADDR),
         .MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
-        .MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
+        .MCONTR_LINTILE_NRESET         (MCONTR_LINTILE_NRESET),
+        .MCONTR_LINTILE_EN             (MCONTR_LINTILE_EN),
+        .MCONTR_LINTILE_WRITE          (MCONTR_LINTILE_WRITE),
+        .MCONTR_LINTILE_EXTRAPG        (MCONTR_LINTILE_EXTRAPG),
+        .MCONTR_LINTILE_EXTRAPG_BITS   (MCONTR_LINTILE_EXTRAPG_BITS),
+        .MCONTR_LINTILE_KEEP_OPEN      (MCONTR_LINTILE_KEEP_OPEN),
+        .MCONTR_LINTILE_BYTE32         (MCONTR_LINTILE_BYTE32),
+        .MCONTR_LINTILE_RST_FRAME      (MCONTR_LINTILE_RST_FRAME),
+        .MCONTR_LINTILE_SINGLE         (MCONTR_LINTILE_SINGLE),
+        .MCONTR_LINTILE_REPEAT         (MCONTR_LINTILE_REPEAT)
     ) mcntrl_tiled_rw_chn2_i ( 
         .mrst                 (mrst),                       // input
         .mclk                 (mclk),                       // input
@@ -1301,7 +1356,16 @@ module  mcntrl393 #(
         .MCNTRL_TILED_TILE_WHS         (MCNTRL_TILED_TILE_WHS),
         .MCNTRL_TILED_STATUS_REG_ADDR  (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
         .MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
-        .MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
+        .MCONTR_LINTILE_NRESET         (MCONTR_LINTILE_NRESET),
+        .MCONTR_LINTILE_EN             (MCONTR_LINTILE_EN),
+        .MCONTR_LINTILE_WRITE          (MCONTR_LINTILE_WRITE),
+        .MCONTR_LINTILE_EXTRAPG        (MCONTR_LINTILE_EXTRAPG),
+        .MCONTR_LINTILE_EXTRAPG_BITS   (MCONTR_LINTILE_EXTRAPG_BITS),
+        .MCONTR_LINTILE_KEEP_OPEN      (MCONTR_LINTILE_KEEP_OPEN),
+        .MCONTR_LINTILE_BYTE32         (MCONTR_LINTILE_BYTE32),
+        .MCONTR_LINTILE_RST_FRAME      (MCONTR_LINTILE_RST_FRAME),
+        .MCONTR_LINTILE_SINGLE         (MCONTR_LINTILE_SINGLE),
+        .MCONTR_LINTILE_REPEAT         (MCONTR_LINTILE_REPEAT)
     ) mcntrl_tiled_rw_chn4_i ( 
         .mrst                 (mrst),                       // input
         .mclk                 (mclk),                       // input

memctrl/mcntrl_linear_rw.v

@@ -47,8 +47,16 @@ module  mcntrl_linear_rw #(
                                                       // if memory controller will allow programming several sequences in advance to
                                                       // spread long-programming (tiled) over fast-programming (linear) requests.
                                                       // But that should not be too big to maintain 2-level priorities
-    parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)                                                     
-//    parameter MCNTRL_SCANLINE_WRITE_MODE =    1'b0    // module is configured to write tiles to external memory (false - read tiles)                                                                                                           
+    parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
+    // bits in mode control word
+    parameter MCONTR_LINTILE_NRESET =           0, // reset if 0
+    parameter MCONTR_LINTILE_EN =               1, // enable requests 
+    parameter MCONTR_LINTILE_WRITE =            2, // write to memory mode
+    parameter MCONTR_LINTILE_EXTRAPG =          3, // extra pages (over 1) needed by the client simultaneously
+    parameter MCONTR_LINTILE_EXTRAPG_BITS =     2, // number of bits to use for extra pages
+    parameter MCONTR_LINTILE_RST_FRAME =        8, // reset frame number 
+    parameter MCONTR_LINTILE_SINGLE =           9, // read/write a single page 
+    parameter MCONTR_LINTILE_REPEAT =          10  // read/write pages until disabled 
 )(
     input                          mrst,
     input                          mclk,
@@ -214,8 +222,8 @@ module  mcntrl_linear_rw #(
     assign set_window_x0y0_w =  cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_X0Y0);
     assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_STARTXY);
     
-    assign single_frame_w =  cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[9];
-    assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[8];
+    assign single_frame_w =  cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_SINGLE];
+    assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
     
     // Set parameter registers
     always @(posedge mclk) begin
@@ -318,11 +326,11 @@ module  mcntrl_linear_rw #(
     assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ;      // memory row
     assign xfer_col= row_col_r[COLADDR_NUMBER-4:0];    // start memory column in 8-bursts
     assign line_unfinished=line_unfinished_r[1];
-    assign chn_en =         &mode_reg[1:0];   // enable requests by channel (continue ones in progress)
-    assign chn_rst =        ~mode_reg[0]; // resets command, including fifo;
-    assign cmd_wrmem =       mode_reg[2];// 0: read from memory, 1:write to memory
-    assign cmd_extra_pages = mode_reg[4:3]; // external module needs more than 1 page
-    assign repeat_frames=    mode_reg[10];
+    assign chn_en =         mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN];   // enable requests by channel (continue ones in progress)
+    assign chn_rst =        ~mode_reg[MCONTR_LINTILE_NRESET]; // resets command, including fifo;
+    assign cmd_wrmem =       mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory
+    assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
+    assign repeat_frames=    mode_reg[MCONTR_LINTILE_REPEAT];
     
     assign status_data= {frame_finished_r, busy_r};     // TODO: Add second bit?
     assign pgm_param_w=      cmd_we;

memctrl/mcntrl_tiled_rw.v

@@ -52,8 +52,18 @@ module  mcntrl_tiled_rw#(
                                                    // if memory controller will allow programming several sequences in advance to
                                                    // spread long-programming (tiled) over fast-programming (linear) requests.
                                                    // But that should not be too big to maintain 2-level priorities
-    parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)                                                     
-//    parameter MCNTRL_TILED_WRITE_MODE =      1'b0  // module is configured to write tiles to external memory (false - read tiles)                                                     
+    parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)                                                     
+    // bits in mode control word
+    parameter MCONTR_LINTILE_NRESET =        0, // reset if 0
+    parameter MCONTR_LINTILE_EN =            1, // enable requests 
+    parameter MCONTR_LINTILE_WRITE =         2, // write to memory mode
+    parameter MCONTR_LINTILE_EXTRAPG =       3, // extra pages (over 1) needed by the client simultaneously
+    parameter MCONTR_LINTILE_EXTRAPG_BITS =  2, // number of bits to use for extra pages
+    parameter MCONTR_LINTILE_KEEP_OPEN =     5, // keep banks open (will be used only if number of rows <= 8)
+    parameter MCONTR_LINTILE_BYTE32 =        6, // use 32-byte wide columns in each tile (false - 16-byte) 
+    parameter MCONTR_LINTILE_RST_FRAME =     8, // reset frame number 
+    parameter MCONTR_LINTILE_SINGLE =        9, // read/write a single page 
+    parameter MCONTR_LINTILE_REPEAT =       10  // read/write pages until disabled 
 )(
     input                          mrst,
     input                          mclk,
@@ -244,8 +254,8 @@ module  mcntrl_tiled_rw#(
     assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_STARTXY);
     assign set_tile_whs_w =     cmd_we && (cmd_a== MCNTRL_TILED_TILE_WHS);
     
-    assign single_frame_w =  cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[9];
-    assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[8];
+    assign single_frame_w =  cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_SINGLE];
+    assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
 
 
     //
@@ -359,14 +369,14 @@ module  mcntrl_tiled_rw#(
     assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ;      // memory row
     assign xfer_col= row_col_r[COLADDR_NUMBER-4:0];    // start memory column in 8-bursts
     assign line_unfinished=line_unfinished_r[1];
-    assign chn_en =         &mode_reg[1:0];   // enable requests by channel (continue ones in progress)
-    assign chn_rst =        ~mode_reg[0]; // resets command, including fifo;
-    assign cmd_wrmem =       mode_reg[2];// 0: read from memory, 1:write to memory
-    assign cmd_extra_pages = mode_reg[4:3]; // external module needs more than 1 page
-    assign keep_open=        mode_reg[5]; // keep banks open (will be used only if number of rows <= 8
-    assign byte32=           mode_reg[6]; // use 32-byte wide columns in each tile (false - 16-byte) 
-    assign repeat_frames=    mode_reg[10];
-    
+
+    assign chn_en =         mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN];   // enable requests by channel (continue ones in progress)
+    assign chn_rst =        ~mode_reg[MCONTR_LINTILE_NRESET]; // resets command, including fifo;
+    assign cmd_wrmem =       mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory
+    assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
+    assign keep_open=        mode_reg[MCONTR_LINTILE_KEEP_OPEN]; // keep banks open (will be used only if number of rows <= 8
+    assign byte32=           mode_reg[MCONTR_LINTILE_BYTE32]; // use 32-byte wide columns in each tile (false - 16-byte) 
+    assign repeat_frames=    mode_reg[MCONTR_LINTILE_REPEAT];
     
     assign status_data=      {frame_finished_r, busy_r}; 
     assign pgm_param_w=      cmd_we;

sensor/sens_gamma.v

@@ -295,7 +295,7 @@ module  sens_gamma #(
     ) dly_16_pxd_i (
         .clk (pclk),        // input
         .rst (prst),        // input
-        .dly (3),           // input[3:0] 
+        .dly (4'd3),           // input[3:0] 
         .din (pxd_in[7:0]), // input[0:0] 
         .dout(pxd_in_d3)    // output[0:0] 
     );
@@ -305,7 +305,7 @@ module  sens_gamma #(
     ) dly_16_sof_eof_i (
         .clk (pclk),        // input
         .rst (prst),         // input
-        .dly (4),           // input[3:0] 
+        .dly (4'd4),           // input[3:0] 
         .din ({eof_in, sof_masked}), // input[0:0] 
         .dout({eof_out,sof_out})    // output[0:0] 
     );

simulation_modules/simul_axi_hp_rd.v

@@ -36,7 +36,7 @@ module  simul_axi_hp_rd #(
     input  [ 3:0] arcache,
     input  [ 2:0] arprot,
     input  [ 3:0] arlen,
-    input  [ 2:0] arsize,
+    input  [ 1:0] arsize,
     input  [ 1:0] arburst,
     input  [ 3:0] arqos,
     // read data
@@ -104,7 +104,7 @@ module  simul_axi_hp_rd #(
 
     wire  [5:0] arid_out; // verify it matches wid_out when outputting data
     wire  [1:0] arburst_out;
-    wire  [2:0] arsize_out; // verify it is 3'h3
+    wire  [1:0] arsize_out; // verify it is 3'h3
     wire  [3:0] arlen_out;
     wire [31:0] araddr_out;
     wire        ar_nempty;
@@ -197,7 +197,7 @@ module  simul_axi_hp_rd #(
     
     always @ (posedge  aclk) begin
         if (start_read_burst_w) begin
-            if (arsize_out != 3'h3) begin
+            if (arsize_out != 2'h3) begin
                 $display ("%m: at time %t ERROR: arsize_out=%h, currently only 'h3 (8 bytes) is valid",$time,arsize_out);
                 $stop;
             end
@@ -254,15 +254,15 @@ module  simul_axi_hp_rd #(
     end
 
 
-fifo_same_clock_fill   #( .DATA_WIDTH(51),.DATA_DEPTH(2)) // read - 4, write - 32?
+fifo_same_clock_fill   #( .DATA_WIDTH(50),.DATA_DEPTH(2)) // read - 4, write - 32?
     raddr_i (
         .rst       (rst),
         .clk       (aclk),
         .sync_rst  (1'b0),
         .we        (arvalid && arready),
         .re        (start_read_burst_w),
-        .data_in   ({arid[5:0],     arburst[1:0],    arsize[2:0],    arlen[3:0],    araddr[31:0],     rd_qos_in[3:0]}),
-        .data_out  ({arid_out[5:0], arburst_out[1:0],arsize_out[2:0],arlen_out[3:0],araddr_out[31:0], rd_qos_out[3:0]}),
+        .data_in   ({arid[5:0],     arburst[1:0],    arsize[1:0],    arlen[3:0],    araddr[31:0],     rd_qos_in[3:0]}),
+        .data_out  ({arid_out[5:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[31:0], rd_qos_out[3:0]}),
         .nempty    (ar_nempty),
         .half_full (), //aw_half_full),
         .under      (), //waddr_under), // output reg 

simulation_modules/simul_axi_hp_wr.v

@@ -36,7 +36,7 @@ module  simul_axi_hp_wr#(
     input  [ 3:0] awcache,  // verify the corerct values are here
     input  [ 2:0] awprot,   // verify the corerct values are here
     input  [ 3:0] awlen,
-    input  [ 2:0] awsize,
+    input  [ 1:0] awsize,
     input  [ 1:0] awburst,
     input  [ 3:0] awqos,    // verify the correct values are here
     // write data
@@ -117,7 +117,7 @@ Alex
 
     wire  [5:0] awid_out; // verify it matches wid_out when outputting data
     wire  [1:0] awburst_out;
-    wire  [2:0] awsize_out; // verify it is 3'h3
+    wire  [1:0] awsize_out; // verify it is 3'h3
     wire  [3:0] awlen_out;
     wire [31:0] awaddr_out;
     wire  [5:0] wid_out;
@@ -235,7 +235,7 @@ Alex
                 $stop;
             end
     
-            if (awsize_out != 3'h3) begin
+            if (awsize_out != 2'h3) begin
                 $display ("%m: at time %t ERROR: awsize_out=%h, currently only 'h3 (8 bytes) is valid",$time,awsize_out);
                 $stop;
             end
@@ -280,15 +280,15 @@ Alex
         
        
 
-fifo_same_clock_fill   #( .DATA_WIDTH(51),.DATA_DEPTH(5)) // read - 4, write - 32?
+fifo_same_clock_fill   #( .DATA_WIDTH(50),.DATA_DEPTH(5)) // read - 4, write - 32?
     waddr_i (
         .rst       (rst),
         .clk       (aclk),
         .sync_rst  (1'b0),
         .we        (awvalid && awready),
         .re        (start_write_burst_w),
-        .data_in   ({awid[5:0],     awburst[1:0],    awsize[2:0],    awlen[3:0],    awaddr[31:0],     wr_qos_in[3:0]}),
-        .data_out  ({awid_out[5:0], awburst_out[1:0],awsize_out[2:0],awlen_out[3:0],awaddr_out[31:0], wr_qos_out[3:0]}),
+        .data_in   ({awid[5:0],     awburst[1:0],    awsize[1:0],    awlen[3:0],    awaddr[31:0],     wr_qos_in[3:0]}),
+        .data_out  ({awid_out[5:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[31:0], wr_qos_out[3:0]}),
         .nempty    (aw_nempty),
         .half_full (), //aw_half_full),
         .under      (), //waddr_under), // output reg 

simulation_modules/simul_clk.v

+/*******************************************************************************
+ * Module: simul_clk
+ * Date:2015-07-29  
+ * Author: andrey     
+ * Description: Generate clocks for simulation
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * simul_clk.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_clk.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_clk#(
+    parameter       CLKIN_PERIOD =  5.0,
+    parameter       MEMCLK_PERIOD = 5.0,
+    parameter       FCLK0_PERIOD = 10.417,
+    parameter       FCLK1_PERIOD =  0.0
+)(
+    input        rst,
+    output       clk,
+    output       memclk,
+    output [1:0] ffclk0,
+    output [1:0] ffclk1
+);
+    
+    wire ffclk0_w;
+    wire ffclk1_w;
+    assign ffclk0 = {~ffclk0_w,ffclk0_w};
+    assign ffclk1 = {~ffclk1_w,ffclk1_w};
+    generate
+        if (CLKIN_PERIOD > 0.0)
+            simul_clk_single #(.PERIOD(CLKIN_PERIOD)) simul_clk_i    (.rst(rst), .clk(clk));
+        else
+            assign clk = 0;
+    endgenerate
+
+    generate
+        if (MEMCLK_PERIOD > 0.0)
+            simul_clk_single #(.PERIOD(MEMCLK_PERIOD)) simul_memclk_i (.rst(rst), .clk(memclk));
+        else
+            assign memclk = 0;
+    endgenerate
+
+    generate
+        if (FCLK0_PERIOD > 0.0)
+            simul_clk_single #(.PERIOD(FCLK0_PERIOD)) simul_ffclk0_i (.rst(rst), .clk(ffclk0_w));
+        else
+            assign ffclk0_w = 0;
+    endgenerate
+
+    generate
+        if (FCLK1_PERIOD > 0.0)
+            simul_clk_single #(.PERIOD(FCLK1_PERIOD)) simul_ffclk1_i (.rst(rst), .clk(ffclk1_w));
+        else
+            assign ffclk1_w = 0;
+    endgenerate
+
+endmodule
+
+module simul_clk_single #(
+        parameter PERIOD = 1000.0
+    ) (
+        input rst,
+        output clk
+    );
+    reg clk_r = 0;
+    assign clk = clk_r;
+    always #(PERIOD/2) clk_r <= rst ? 1'b0:  ~clk_r;
+endmodule

simulation_modules/simul_sensor12bits.v

+/*******************************************************************************
+ * Module: simul_sensor12bits
+ * Date:2015-07-29  
+ * Author: Andrey Filippov     
+ * Description: Generate sensor data
+ *
+ * Copyright (c) 2002-2015 Elphel, Inc.
+ * simul_sensor12bits.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_sensor12bits.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+
+module   simul_sensor12bits # (
+    parameter lline   =   192,   //   1664;//   line duration in clocks
+    parameter ncols   =    66,   //58; //56; // 129; //128;   //1288;
+    parameter nrows   =    18,   // 16;   //   1032;
+    parameter nrowb =       1,   // number of "blank rows" from vact to 1-st hact
+    parameter nrowa   =     1,   // number of "blank rows" from last hact to end of vact
+//    parameter nAV   =      24,   //240;   // clocks from ARO to VACT (actually from en_dclkd)
+    parameter nbpf   =     20,   //16; // bpf length
+    parameter ngp1   =      8,   // bpf to hact
+    parameter nVLO   =      1,   // VACT=0 in video mode (clocks)
+    //parameter tMD   =   14;    //
+    //parameter tDDO   =   10;   //   some confusion here - let's assume that it is from DCLK to Data out
+    parameter tMD   =       4,   //
+    parameter tDDO   =      2,   //   some confusion here - let's assume that it is from DCLK to Data out
+    parameter tDDO1 =       5,   //
+    parameter trigdly =     8,   // delay between trigger input and start of output (VACT) in lines
+    parameter ramp  =       1    // 1 - ramp, 0 - random (now - sensor.dat)
+    
+) (
+    input         MCLK,   // Master clock
+    input         MRST,   // Master Reset - active low
+    input         ARO,   // Array read Out.
+    input         ARST,   // Array Reset. Active low
+    input         OE,   // output Elphel, Inc.ock
+    input         SCL,   // I2C data // SuppressThisWarning VEditor - not used
+    inout         SDA,   // I2C data// SuppressThisWarning VEditor - not used/assigned
+    input         OFST,   // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
+    output [11:0] D,      // [11:0] data output
+    output        DCLK,   // Data output clock
+    output        BPF,   // Black Pixel Flag
+    output        HACT,   // Horizontal Active
+    output        VACT, // Vertical Active
+    output        VACT1);
+
+    
+    localparam   s_stop=      0;
+    localparam   s_preVACT=   1;
+    localparam   s_firstline= 2;
+    localparam   s_BPF=       3;
+    localparam   s_preHACT=   4;
+    localparam   s_HACT=      5;
+    localparam   s_afterHACT= 6;
+    localparam   s_lastline=  7;
+    localparam   s_frame_done=8;
+    
+    localparam   t_preVACT=  lline* trigdly;
+    localparam   t_firstline=nrowb*lline+1;   // 1664
+    localparam   t_BPF=      nbpf;         // 16
+    localparam   t_preHACT=   ngp1;         // 8
+    localparam   t_HACT=      ncols;         // 1288
+    localparam   t_afterHACT=lline-nbpf-ngp1-ncols;   // 352
+    localparam   t_lastline=   nrowa*lline+1;   // 1664
+
+reg   [15:0]   sensor_data[0:4095]; // up to 64 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
+//    $readmemh("sensor.dat",sensor_data);
+
+
+
+reg         c;      // internal data out clock
+//reg      [9:0]   id;      // internal pixel data (sync do DCLK)
+//wire   [9:0]   nxt_d;   // will be calculated later - next pixel data
+reg            stopped;
+wire   #1      stoppedd=stopped;
+reg            ibpf, ihact, ivact, ivact1;
+reg            arst1;   //
+reg      [11:0]   col;   // current row
+reg      [11:0]   row;   // current column;
+reg      [3:0]   state;
+reg      [15:0]   cntr;
+wire   [11:0]   cold;
+wire   [11:0]   rowd;
+wire   [3:0]   stated;
+wire   [15:0]   cntrd;
+wire         NMRST=!MRST;
+
+parameter new_bayer=0; // 0 - old (16x16), 1 - new (18x18)
+
+wire   [5:0] row_index=row[5:0]-new_bayer;
+wire   [5:0] col_index=col[5:0]-new_bayer;
+
+
+// random
+integer       seed;
+integer         r;
+reg            c_rand;
+reg      [11:0]   d_rand;
+
+
+
+assign      #1   cold=   col;
+assign      #1   rowd=   row;
+assign      #1   stated=   state;
+assign      #1   cntrd=   cntr;
+
+
+
+//assign   #tDDO   D   =  OE?   {10{1'bz}}:   ((ihact || ibpf)?   ((ramp)?(col[9:0] + row[9:0]):(d_rand)): 10'b0); // just test pattern
+//assign   #tDDO   D   =  OE?   {10{1'bz}}:   ((ihact || ibpf)?   ((ramp)?(col[9:0] + row[9:0]):(sensor_data[{row_index[5:0],col_index[5:0]}])): 10'b0); // just test pattern
+//assign   #tDDO   D   =  OE?   {12{1'bz}}:   ((ihact || ibpf)?   ((ramp)?(col[11:0] + row[11:0]):(sensor_data[{row_index[5:0],col_index[5:0]}])): 12'b0); // just test pattern
+assign   #tDDO   D   =  OE?   {12{1'bz}}:   ((ihact || ibpf)?   ((ramp)?({row[11:8],8'h0} + col[11:0]):(sensor_data[{row_index[5:0],col_index[5:0]}])): 12'b0); // just test pattern
+//assign   #tDDO   BPF   = ibpf;
+//assign   #tDDO   HACT= ihact;
+//assign   #tDDO   VACT= ivact;
+assign   #tDDO1   BPF   = ibpf;
+assign   #tDDO1   HACT= ihact;
+assign   #tDDO1   VACT= ivact;
+assign   #tDDO1   VACT1= ivact && !ivact1;
+assign         DCLK= c;
+
+initial begin
+//parameter ramp   =   1;   // 0 - ramp, 1 - random
+//parameter lline   =   192; //   1664;//   line duration in clocks
+//parameter ncols   =   58; //56; // 129; //128;   //1288;
+//parameter nrows   =   16;   //   1032;
+
+   $display ("sensor parameters");
+   $display ("    -- ramp  = %d (0 - random, 1 - ramp)",ramp);
+   $display ("    -- lline = %d (line duration in clocks)",lline);
+   $display ("    -- ncols = %d (numer of clocks in HACT)",ncols);
+   $display ("    -- nrows = %d (number of rows)",nrows);
+   $display ("    -- t_afterHACT = %d ",t_afterHACT);
+   $display ("    -- t_preHACT = %d ",t_preHACT);
+   $display ("    -- new_bayer = %d ",new_bayer);
+
+//  reg   [15:0]   sensor_data[0:4095]; // up to 64 x 64 pixels
+    $readmemh("input_data/sensor.dat",sensor_data);
+   c=0;
+//   {ibpf,ihact,ivact}=0;
+   stopped=1;
+   arst1=   0;
+   seed=   1;
+   d_rand=   0;
+//   row=0;
+//   col=0;
+
+end
+always @ (NMRST) begin
+   c=0;
+//   {ibpf,ihact,ivact}=0;
+   stopped=1;
+   arst1=0;
+//   row=0;
+//   col=0;
+end
+
+always begin
+   @ (posedge MCLK) begin
+      #tMD   c = !stoppedd;
+      end
+   @ (negedge MCLK) begin
+      #tMD   c = 1'b0;
+   end
+end
+
+always @ (posedge MCLK) begin
+//   #1   stopped= !arst1 || (stoppedd  && !ARO) ;
+   #1   stopped= !arst1 || ((stoppedd || (state== s_frame_done)) && ARO) ; /// ARO tow TRIGGER, ective low
+   #1   arst1=ARST;
+end
+
+always @ (posedge c) ivact1 = ivact;
+always @ (posedge stoppedd or posedge c) begin
+   if (stoppedd) begin
+      {ibpf,ihact,ivact}=0;
+      row=0;
+      col=0;
+//      id=0;
+      state=0;
+      cntr=0;
+   end else if (|cntrd != 0) begin
+      #1 cntr=cntrd-1;
+      if (BPF || HACT) col=cold+1;
+   end else begin
+      case (stated)
+      s_stop: begin
+            cntr=   t_preVACT-1;
+            state=   s_preVACT;
+         end
+      s_preVACT: begin
+            ivact=   1'b1;
+            cntr=   t_firstline-1;
+            state=   s_firstline;
+         end
+       s_firstline: begin
+            col=   0;
+            row=   0;
+            if (t_BPF>=1) begin
+              ibpf=   1'b1;
+              cntr=   t_BPF-1;
+              state=   s_BPF;
+            end else begin
+              ihact=   1'b1;
+              cntr=   t_HACT-1;
+              state=   s_HACT;
+            end
+         end
+      s_BPF: begin
+            ibpf=   1'b0;
+            cntr=   t_preHACT-1;
+            state=   s_preHACT;
+         end
+      s_preHACT: begin
+            ihact=   1'b1;
+            col=   0;
+            cntr=   t_HACT-1;
+            state=   s_HACT;
+         end
+      s_HACT: begin
+            ihact=   1'b0;
+            row=   rowd+1;
+            cntr=   t_afterHACT-1;
+            state=   s_afterHACT;
+         end
+      s_afterHACT:
+         if (rowd == nrows) begin
+            cntr=   t_lastline-1;
+            state=   s_lastline;
+         end else begin
+            col=   0;
+            if (t_BPF>=1) begin
+              ibpf=   1'b1;
+              cntr=   t_BPF-1;
+              state=   s_BPF;
+            end else begin
+              ihact=   1'b1;
+              cntr=   t_HACT-1;
+              state=   s_HACT;
+            end
+         end
+      s_lastline: begin
+            ivact=   1'b0;
+            state=   s_frame_done;
+            cntr=nVLO;
+         end
+      s_frame_done: if (OFST) begin
+            ivact=   1'b1;
+            cntr=   t_firstline-1;
+            state=   s_firstline;
+         end
+      endcase
+
+   end
+// random data
+   seed =   $random(seed);
+   r =      (seed & 'h7fff);
+   r=       (r * r) >> 20; // 10 bits
+   c_rand = seed[16]; // >>16; // sign
+   d_rand=c_rand?(D+(((1023-d_rand)*r)>>10)):(d_rand-((d_rand*r)>>10));
+end
+
+
+
+endmodule

timing/camsync393.v

@@ -75,11 +75,11 @@ module camsync393       #(
                            //     256>=d - repetitive trigger
                            
                            // 4..7 - input trigger delay (in pclk periods) 
-    input                         pclk,    // pixel clock (global) - switch it to 100MHz (mclk/2)?
-    input                         prst,        // @ posedge pclk - sync reset
-    input                  [9:0]  gpio_in, // 12-bit input from GPIO pins -> 10 bit
-    output                 [9:0]  gpio_out,// 12-bit output to GPIO pins
-    output reg             [9:0]  gpio_out_en,// 12-bit output enable to GPIO pins
+    input                         pclk,           // pixel clock (global) - switch it to 100MHz (mclk/2)?
+    input                         prst,           // @ posedge pclk - sync reset
+    input                  [9:0]  gpio_in,        // 10-bit input from GPIO pins -> 10 bit
+    output                 [9:0]  gpio_out,       // 10-bit output to GPIO pins
+    output reg             [9:0]  gpio_out_en,    // 10-bit output enable to GPIO pins
 
     output                        triggered_mode, // use triggered mode (0 - sensors are free-running) @mclk
 

timing/timing393.v

@@ -66,16 +66,16 @@ module  timing393       #(
     input                         status_start, // Acknowledge of the first status packet byte (address)
 
     // connection to the general purpose I/O control    
-    input                  [9:0]  gpio_in, // 12-bit input from GPIO pins -> 10 bit
-    output                 [9:0]  gpio_out,// 12-bit output to GPIO pins
-    output                 [9:0]  gpio_out_en,// 12-bit output enable to GPIO pins
+    input                  [9:0]  gpio_in,        // 10-bit input from GPIO pins -> 10 bit
+    output                 [9:0]  gpio_out,       // 10-bit output to GPIO pins
+    output                 [9:0]  gpio_out_en,    // 10-bit output enable to GPIO pins
 
     // common for all sensors - use triggered mode (as opposed to a free-running mode)
     output                        triggered_mode, // use triggered mode (0 - sensors are free-running) @mclk - common to all sensors
 
     // per-channel frame sync inputs and trigger outputs. Both single-cycle mclk pulses
-    input                         frsync_chn0,  // @mclk trigrst,   // single-clock start of frame input (resets trigger output) posedge (@pclk)
-    output                        trig_chn0,    // @mclk 1 cycle-long trigger output
+    input                         frsync_chn0,    // @mclk trigrst,   // single-clock start of frame input (resets trigger output) posedge (@pclk)
+    output                        trig_chn0,      // @mclk 1 cycle-long trigger output
 
     input                         frsync_chn1,  // @mclk trigrst,   // single-clock start of frame input (resets trigger output) posedge (@pclk)
     output                        trig_chn1,    // 1 cycle-long trigger output

util_modules/level_cross_clocks.v

@@ -56,17 +56,18 @@ module  level_cross_clocks#(
 endmodule
 
 module  level_cross_clocks_single_bit#(
-    parameter REGISTER = 3 // number of registers (>3)
+    parameter REGISTER = 3 // number of registers (>=3)
 )(
     input   clk,
     input   d_in,
     output  d_out
 );
-    reg [REGISTER - 3 : 0] regs;
-    wire                   d_sync; // after a 2-bit synchronizer
+    reg  [REGISTER - 3 : 0] regs = 0;
+    wire                    d_sync; // after a 2-bit synchronizer
+    wire [REGISTER - 2 : 0] regs_next = {regs, d_sync};
     assign d_out = regs[REGISTER -3];
     always @ (posedge clk) begin
-        regs <= (regs << 1) + d_sync; // | d_in complains about widths mismatch
+        regs <= regs_next[REGISTER - 3 : 0]; // | d_in complains about widths mismatch
     end
     level_cross_clocks_sync_bit level_cross_clocks_sync_bit_i (
         .clk   (clk), // input

util_modules/sync_resets.v

@@ -30,13 +30,18 @@ module  sync_resets#(
     input  [WIDTH-1:0] clk,     // clk[0] - master clock generation should not depend on resets)
     output [WIDTH-1:0] rst       // resets matching input clocks
 );
+    reg                 en_locked=0; // mostly for simulation, locked[0] is 1'bx until the first clock[0] pulse
     wire    [WIDTH-1:0] rst_w;  // resets matching input clocks
     wire                rst_early_master;
     assign rst = rst_w;
     reg                mrst = 1;
     always @ (posedge arst or posedge clk[0]) begin
+    
+        if (arst) en_locked <= 0;
+        else      en_locked <= 1;
+    
         if (arst) mrst <= 1;
-        else      mrst <=  ~locked[0];
+        else      mrst <=  ~(locked[0] && en_locked);
     end
     level_cross_clocks #(
         .WIDTH      (1),

util_modules/table_ad_transmit.v

@@ -60,7 +60,7 @@ module  table_ad_transmit#(
         if (we && a_not_d_in) sel_a <= din[24+:ADDR_BITS];
         
     end
-    dly_16 #(.WIDTH(1)) i_end_burst(.clk(clk),.rst(1'b0), .dly(2), .din(we), .dout(we3)); // dly=2+1=3
+    dly_16 #(.WIDTH(1)) i_end_burst(.clk(clk),.rst(1'b0), .dly(4'd2), .din(we), .dout(we3)); // dly=2+1=3
     
     genvar i;
     generate 

wrap/oserdes_mem.v

@@ -46,7 +46,7 @@ localparam integer DATA_WIDTH_TRI=  (MODE_DDR=="TRUE")?4:1;
     seems to be OK.
 */
 
-`ifndef IVERILOG  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted ) 
+`ifndef OPEN_SOURCE_ONLY  // Not using simulator - instanciate actual ISERDESE2 (can not be simulated because of encrypted )           
            OSERDESE2 #(
                .DATA_RATE_OQ         (DATA_RATE),
                .DATA_RATE_TQ         (DATA_RATE),

x393.v

@@ -1050,6 +1050,16 @@ assign axi_grst = axi_rst_pre;
         .MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
         .MCNTRL_TILED_PENDING_CNTR_BITS    (MCNTRL_TILED_PENDING_CNTR_BITS),
         .MCNTRL_TILED_FRAME_PAGE_RESET     (MCNTRL_TILED_FRAME_PAGE_RESET),
+        .MCONTR_LINTILE_NRESET             (MCONTR_LINTILE_NRESET),
+        .MCONTR_LINTILE_EN                 (MCONTR_LINTILE_EN),
+        .MCONTR_LINTILE_WRITE              (MCONTR_LINTILE_WRITE),
+        .MCONTR_LINTILE_EXTRAPG            (MCONTR_LINTILE_EXTRAPG),
+        .MCONTR_LINTILE_EXTRAPG_BITS       (MCONTR_LINTILE_EXTRAPG_BITS),
+        .MCONTR_LINTILE_KEEP_OPEN          (MCONTR_LINTILE_KEEP_OPEN),
+        .MCONTR_LINTILE_BYTE32             (MCONTR_LINTILE_BYTE32),
+        .MCONTR_LINTILE_RST_FRAME          (MCONTR_LINTILE_RST_FRAME),
+        .MCONTR_LINTILE_SINGLE             (MCONTR_LINTILE_SINGLE),
+        .MCONTR_LINTILE_REPEAT             (MCONTR_LINTILE_REPEAT),
         .BUFFER_DEPTH32                    (BUFFER_DEPTH32),
         .RSEL                              (RSEL),
         .WSEL                              (WSEL)
@@ -1833,7 +1843,7 @@ assign axi_grst = axi_rst_pre;
         .status_rq      (status_timing_rq),      // output
         .status_start   (status_timing_start),   // input
         .gpio_in        (gpio_rd),               // input[9:0] 
-        .gpio_out       (gpio_camsync),          // output[9:0] 
+        .gpio_out       (gpio_camsync),          // output[9:0] ([6]-synco0,[7]-syncio0,[8]-synco1,[9]-syncio1)
         .gpio_out_en    (gpio_camsync_en),       // output[9:0] 
         .triggered_mode (trigger_mode),          // output
         .frsync_chn0    (sof_out_mclk[0]),       // input