Commit 48b08174 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

working on synthesis errors

parent bf7c096d

.project

+4 −4
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@@ -92,7 +92,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150718125232570.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150718203305908.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
@@ -102,7 +102,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150702180615691.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150718203305908.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
@@ -112,7 +112,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150702180615691.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150718203305908.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>

			<name>vivado_state/x393-opt-phys.dcp</name>
@@ -132,7 +132,7 @@ 
		<link>

		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150702180615691.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150718203305908.dcp</location>

		</link>

		</link>

	</linkedResources>

	</linkedResources>

</projectDescription>
 
</projectDescription>

README.md

+2 −0
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@@ -3,3 +3,5 @@ x393 




FPGA code for Elphel 393 camera, created with [VDT plugin](https://github.com/Elphel/vdt-plugin)

FPGA code for Elphel 393 camera, created with [VDT plugin](https://github.com/Elphel/vdt-plugin)





Branch ``master`` includes the code that is simulated and tested with the NC393 hardware as described in the blog post about the [multichannel memory controller](http://blog.elphel.com/2015/05/nc393-development-progress-multichannel-memory-controller-for-the-multi-sensor-camera/).

Branch ``adding_sensors`` is a current development branch that is not yet simulated, synthesized or tested. 
 No newline at end of file

axi/cmprs_afi_mux.v

+2 −2
Original line number Original line Diff line number Diff line
@@ -90,7 +90,7 @@ module cmprs_afi_mux#( 
    output                 [ 3:0] afi_awcache,

    output                 [ 3:0] afi_awcache,

    output                 [ 2:0] afi_awprot,

    output                 [ 2:0] afi_awprot,

    output                 [ 3:0] afi_awlen,

    output                 [ 3:0] afi_awlen,

    output                 [ 2:0] afi_awsize,

    output                 [ 1:0] afi_awsize,

    output                 [ 1:0] afi_awburst,

    output                 [ 1:0] afi_awburst,

    output                 [ 3:0] afi_awqos,

    output                 [ 3:0] afi_awqos,

    // write data

    // write data
@@ -222,7 +222,7 @@ module cmprs_afi_mux#( 
    assign afi_awlock =        2'h0;

    assign afi_awlock =        2'h0;

    assign afi_awcache =       4'h3;

    assign afi_awcache =       4'h3;

    assign afi_awprot =        3'h0;

    assign afi_awprot =        3'h0;

    assign afi_awsize =        3'h3;

    assign afi_awsize =        2'h3;

    assign afi_awburst =       2'h1;

    assign afi_awburst =       2'h1;

    assign afi_awqos =         4'h0;

    assign afi_awqos =         4'h0;

    assign afi_wstrb =         8'hff;

    assign afi_wstrb =         8'hff;

axi/cmprs_afi_mux_ptr_wresp.v

+4 −2
Original line number Original line Diff line number Diff line
@@ -55,7 +55,8 @@ module cmprs_afi_mux_ptr_wresp( 
    reg  [26:0] chunk_ptr_inc;          // incremented by 1..4 chunk pointer

    reg  [26:0] chunk_ptr_inc;          // incremented by 1..4 chunk pointer

    reg  [27:0] chunk_ptr_rovr;         // incremented chunk pointer, decremented by length (MSB - sign)

    reg  [27:0] chunk_ptr_rovr;         // incremented chunk pointer, decremented by length (MSB - sign)

    reg  [ 3:0] busy;                   // one-hot busy stages (usually end with [3]   

    reg  [ 3:0] busy;                   // one-hot busy stages (usually end with [3]   

    reg  [ 5:0] id_r;                   // registered ID data

//    reg  [ 5:0] id_r;                   // registered ID data

    reg  [ 4:0] id_r;                   // registered ID data - MSB is unused

    reg   [1:0] chn;                    // selected channel

    reg   [1:0] chn;                    // selected channel

    reg         eof;                    // eof register being written

    reg         eof;                    // eof register being written

    reg         last_burst_in_frame;    // this response is for eof

    reg         last_burst_in_frame;    // this response is for eof
@@ -90,7 +91,8 @@ module cmprs_afi_mux_ptr_wresp( 
        afi_bready_r <= !en || pre_busy; // (!busy[0] && !pre_busy && !resetting[0] && !start_resetting_w);

        afi_bready_r <= !en || pre_busy; // (!busy[0] && !pre_busy && !resetting[0] && !start_resetting_w);

        busy <= {busy[2:0], pre_busy}; // adjust bits

        busy <= {busy[2:0], pre_busy}; // adjust bits

        

        

        id_r <= afi_bid;

//        id_r <= afi_bid;

        id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved

        

        

        if (start_resetting_w)  reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),

        if (start_resetting_w)  reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),

                                                 reset_rq[2] & ~(|reset_rq[1:0]),

                                                 reset_rq[2] & ~(|reset_rq[1:0]),

axi/histogram_saxi.v

+1 −1
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@@ -254,7 +254,7 @@ module histogram_saxi#( 
    end

    end

    always @(posedge mclk) begin

    always @(posedge mclk) begin

        if (we_addr) hist_start_page[cmd_wa] <= cmd_data[19:0];

        if (we_addr) hist_start_page[cmd_wa] <= cmd_data[19:0];

        en_aclk <= en;

//        en_aclk <= en;

    end

    end





    // mclk (write) port of the buffer

    // mclk (write) port of the buffer