working on synthesis errors

.project

@@ -92,7 +92,7 @@
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150718125232570.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150718203305908.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
@@ -102,7 +102,7 @@
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150702180615691.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150718203305908.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
@@ -112,7 +112,7 @@
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150702180615691.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150718203305908.log</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-opt-phys.dcp</name>
@@ -132,7 +132,7 @@
 		<link>
 			<name>vivado_state/x393-synth.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150702180615691.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150718203305908.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>

README.md

@@ -3,3 +3,5 @@ x393
 
 FPGA code for Elphel 393 camera, created with [VDT plugin](https://github.com/Elphel/vdt-plugin)
 
+Branch ``master`` includes the code that is simulated and tested with the NC393 hardware as described in the blog post about the [multichannel memory controller](http://blog.elphel.com/2015/05/nc393-development-progress-multichannel-memory-controller-for-the-multi-sensor-camera/).
+Branch ``adding_sensors`` is a current development branch that is not yet simulated, synthesized or tested. 
\ No newline at end of file

axi/cmprs_afi_mux.v

@@ -90,7 +90,7 @@ module  cmprs_afi_mux#(
     output                 [ 3:0] afi_awcache,
     output                 [ 2:0] afi_awprot,
     output                 [ 3:0] afi_awlen,
-    output                 [ 2:0] afi_awsize,
+    output                 [ 1:0] afi_awsize,
     output                 [ 1:0] afi_awburst,
     output                 [ 3:0] afi_awqos,
     // write data
@@ -222,7 +222,7 @@ module  cmprs_afi_mux#(
     assign afi_awlock =        2'h0;
     assign afi_awcache =       4'h3;
     assign afi_awprot =        3'h0;
-    assign afi_awsize =        3'h3;
+    assign afi_awsize =        2'h3;
     assign afi_awburst =       2'h1;
     assign afi_awqos =         4'h0;
     assign afi_wstrb =         8'hff;

axi/cmprs_afi_mux_ptr_wresp.v

@@ -55,7 +55,8 @@ module  cmprs_afi_mux_ptr_wresp(
     reg  [26:0] chunk_ptr_inc;          // incremented by 1..4 chunk pointer
     reg  [27:0] chunk_ptr_rovr;         // incremented chunk pointer, decremented by length (MSB - sign)
     reg  [ 3:0] busy;                   // one-hot busy stages (usually end with [3]   
-    reg  [ 5:0] id_r;                   // registered ID data
+//    reg  [ 5:0] id_r;                   // registered ID data
+    reg  [ 4:0] id_r;                   // registered ID data - MSB is unused
     reg   [1:0] chn;                    // selected channel
     reg         eof;                    // eof register being written
     reg         last_burst_in_frame;    // this response is for eof
@@ -90,7 +91,8 @@ module  cmprs_afi_mux_ptr_wresp(
         afi_bready_r <= !en || pre_busy; // (!busy[0] && !pre_busy && !resetting[0] && !start_resetting_w);
         busy <= {busy[2:0], pre_busy}; // adjust bits
         
-        id_r <= afi_bid;
+//        id_r <= afi_bid;
+        id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
         
         if (start_resetting_w)  reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),
                                                  reset_rq[2] & ~(|reset_rq[1:0]),

axi/histogram_saxi.v

@@ -254,7 +254,7 @@ module  histogram_saxi#(
     end
     always @(posedge mclk) begin
         if (we_addr) hist_start_page[cmd_wa] <= cmd_data[19:0];
-        en_aclk <= en;
+//        en_aclk <= en;
     end
 
     // mclk (write) port of the buffer

axi/membridge.v

@@ -74,7 +74,7 @@ module  membridge#(
     output  [ 3:0] afi_awcache,
     output  [ 2:0] afi_awprot,
     output  [ 3:0] afi_awlen,
-    output  [ 2:0] afi_awsize,
+    output  [ 1:0] afi_awsize,
     output  [ 1:0] afi_awburst,
     output  [ 3:0] afi_awqos,
     // write data
@@ -103,7 +103,7 @@ module  membridge#(
     output  [ 3:0] afi_arcache,
     output  [ 2:0] afi_arprot,
     output  [ 3:0] afi_arlen,
-    output  [ 2:0] afi_arsize,
+    output  [ 1:0] afi_arsize,
     output  [ 1:0] afi_arburst,
     output  [ 3:0] afi_arqos,
     // read data
@@ -126,7 +126,7 @@ module  membridge#(
     assign afi_awlock =        2'h0;
 //    assign afi_awcache =       4'h3;
     assign afi_awprot =        3'h0;
-    assign afi_awsize =        3'h3;
+    assign afi_awsize =        2'h3;
     assign afi_awburst =       2'h1;
     assign afi_awqos =         4'h0;
     assign afi_wstrb =         8'hff;
@@ -135,7 +135,7 @@ module  membridge#(
     assign afi_arlock =        2'h0;
 //    assign afi_arcache =       4'h3;
     assign afi_arprot =        3'h0;
-    assign afi_arsize =        3'h3;
+    assign afi_arsize =        2'h3;
     assign afi_arburst =       2'h1;
     assign afi_arqos =         4'h0;
     assign afi_rdissuecap1en = 1'b0;

axi/mult_saxi_wr.v

@@ -95,7 +95,7 @@ module  mult_saxi_wr #(
     output              [ 3:0] saxi_wstrb,             // AXI PS Slave GP0 WSTRB[3:0], input
     // write response Not used - may add guaranteed address (as for the histogram)?
     input                      saxi_bvalid,            // AXI PS Slave GP0 BVALID, output   // @SuppressThisWarning VEditor unused
-    output                     saxi_bready,            // AXI PS Slave GP0 BREADY, input    // @SuppressThisWarning VEditor unused
+    output                     saxi_bready,            // AXI PS Slave GP0 BREADY, input 
     input               [ 5:0] saxi_bid,               // AXI PS Slave GP0 BID[5:0], output //TODO:  Update range !!!  // @SuppressThisWarning VEditor unused
     input               [ 1:0] saxi_bresp              // AXI PS Slave GP0 BRESP[1:0], output    // @SuppressThisWarning VEditor unused
 );
@@ -150,6 +150,8 @@ module  mult_saxi_wr #(
     wire                       we_ctrl;
     wire                       cmd_we_sa_len;
     
+    assign                     saxi_bready=1'b1;
+    
     assign {en_chn3, en_chn2, en_chn1, en_chn0} = en_chn_mclk; 
 
     assign {read_burst3, read_burst2, read_burst1, read_burst0} = grant_wr; // single clock pulse

compressor_jp/compressor393.v

@@ -179,7 +179,7 @@ module  compressor393 # (
     output                 [ 3:0] afi0_awcache,
     output                 [ 2:0] afi0_awprot,
     output                 [ 3:0] afi0_awlen,
-    output                 [ 2:0] afi0_awsize,
+    output                 [ 1:0] afi0_awsize,
     output                 [ 1:0] afi0_awburst,
     output                 [ 3:0] afi0_awqos,
     // write data
@@ -208,7 +208,7 @@ module  compressor393 # (
     output                 [ 3:0] afi1_awcache,
     output                 [ 2:0] afi1_awprot,
     output                 [ 3:0] afi1_awlen,
-    output                 [ 2:0] afi1_awsize,
+    output                 [ 1:0] afi1_awsize,
     output                 [ 1:0] afi1_awburst,
     output                 [ 3:0] afi1_awqos,
     // write data

compressor_jp/huffman393.v

@@ -303,7 +303,7 @@ module huffman393    (
         .dv        (tser_we),           // input
         .ta        (ta),                // output[22:0] 
         .td        (tdi),               // output[15:0] 
-        .twe       (twe)               // output
+        .twe       (twe)                // output
     );
   
   
@@ -367,8 +367,10 @@ module huffman393    (
 //        .data_out({unused[11:0],tables_out[19:0]}), // output[31:0] 
         .data_out(tables_out), // output[31:0] 
         .wclk(mclk), // input
-        .waddr({ta[8:0],twe_d}), // input[9:0] 
-        .we(twe | twe_d), // input
+//        .waddr({ta[8:0],twe_d}), // input[9:0] 
+//        .we(twe | twe_d), // input
+        .waddr(ta[9:0]), // input[9:0] 
+        .we   (twe), // input
         .web(4'hf), // input[3:0] 
         .data_in(tdi[15:0]) // input[15:0] 
     );

compressor_jp/stuffer393.v

@@ -143,7 +143,8 @@ module stuffer393 (
     
     wire          ts_rstb; // one cycle before getting timestamp data from FIFO
     wire    [7:0] ts_dout; // timestamp data, byte at a time
-    reg     [7:0] ts_cycles; // 1-hot we for the portions of the 'old" timestamp registers
+//    reg     [7:0] ts_cycles; // 1-hot we for the portions of the 'old" timestamp registers
+    reg     [6:0] ts_cycles; // 1-hot we for the portions of the 'old" timestamp registers
     
     reg           color_first_r; // registered with the same clock as color_first to extract leading edge
     wire          stb_start; // re-clocked  color_first
@@ -151,7 +152,8 @@ module stuffer393 (
     
     assign ts_rstb = trailer && !was_trailer;  // enough time to have timestamp data
     always @ (negedge clk) begin
-        ts_cycles <= {ts_cycles[6:0],ts_rstb};
+//        ts_cycles <= {ts_cycles[6:0],ts_rstb};
+        ts_cycles <= {ts_cycles[5:0],ts_rstb};
         if      (ts_cycles[0])  sec_r[ 7: 0] <= ts_dout;
         else if (time_size_out) sec_r[ 7: 0] <= sec_r[23:16];
         else if (start_sizeout) sec_r[ 7: 0] <= size_count[ 7:0];

memctrl/mcntrl393.v

@@ -421,7 +421,6 @@ module  mcntrl393 #(
     wire        need_rq1;
     wire        channel_pgm_en1; 
     wire        seq_done1;
-    wire        page_nxt_chn1;
 // routed outside to membredge module    
 /*
     wire        buf_wr_chn1;
@@ -435,7 +434,6 @@ module  mcntrl393 #(
     wire        need_rq2;
     wire        channel_pgm_en2; 
     wire        seq_done2;
-    wire        page_nxt_chn2;
     wire        buf_wr_chn2;
     wire        buf_wpage_nxt_chn2;
     wire [63:0] buf_wdata_chn2;
@@ -447,7 +445,6 @@ module  mcntrl393 #(
     wire        need_rq3;
     wire        channel_pgm_en3; 
     wire        seq_done3;
-    wire        page_nxt_chn3;
     wire        buf_wr_chn3;
     wire        buf_wpage_nxt_chn3;
     wire [63:0] buf_wdata_chn3;
@@ -459,7 +456,6 @@ module  mcntrl393 #(
     wire        need_rq4;
     wire        channel_pgm_en4; 
     wire        seq_done4;
-    wire        page_nxt_chn4;
     wire        buf_wr_chn4;
     wire        buf_wpage_nxt_chn4;
     wire [63:0] buf_wdata_chn4;
@@ -554,7 +550,7 @@ module  mcntrl393 #(
     wire                   [3:0] cmprs_keep_open;   // start generating commands
     wire                   [3:0] cmprs_partial; // output
     wire                   [3:0] cmprs_seq_done; // input : sequence over
-    assign cmprs_page_ready = cmprs_seq_done;// mcntrl_tiled_rw does not generate page_ready pulse as it is the same as xfer_done input
+//    assign cmprs_page_ready = cmprs_seq_done;// mcntrl_tiled_rw does not generate page_ready pulse as it is the same as xfer_done input
 
 // combinatorial early signals
     wire                         select_cmd0_w;
@@ -757,13 +753,6 @@ module  mcntrl393 #(
     assign buf4rd_rd=    axird_ren   && select_buf4rd;
     assign buf4rd_regen= axird_regen && select_buf4rd_d;
     
-    
-    assign page_ready_chn1=page_nxt_chn1; //seq_done2;
-    assign page_ready_chn2=page_nxt_chn2; //seq_done2;
-    assign page_ready_chn3=page_nxt_chn3; //seq_done3;      // TODO - check if it should not be rpage_next
-    assign page_ready_chn4=page_nxt_chn4; //rpage_nxt_chn4;
-    
-    
     assign axird_selected=axird_selected_r;
     assign select_cmd0_w = ((axiwr_pre_awaddr ^ MCONTR_CMD_WR_ADDR) & MCONTR_WR_MASK)==0;
     assign select_buf0rd_w = ((axird_pre_araddr ^ MCONTR_BUF0_RD_ADDR) & MCONTR_RD_MASK)==0;
@@ -1784,7 +1773,7 @@ module  mcntrl393 #(
         .need_rq1           (need_rq1), // input
         .channel_pgm_en1    (channel_pgm_en1), // output reg 
         .seq_done1          (seq_done1), // output
-        .page_nxt_chn1      (page_nxt_chn1), //rpage_nxt_chn0), not used
+        .page_nxt_chn1      (page_ready_chn1), //rpage_nxt_chn0), not used
         .buf_run1           (), //buf_run1),
         .buf_wr_chn1        (buf_wr_chn1), // output
         .buf_wpage_nxt_chn1 (buf_wpage_nxt_chn1), // output
@@ -1799,7 +1788,7 @@ module  mcntrl393 #(
         .need_rq2           (need_rq2), // input
         .channel_pgm_en2    (channel_pgm_en2), // output reg 
         .seq_done2          (seq_done2), // output
-        .page_nxt_chn2      (page_nxt_chn2), //rpage_nxt_chn0), not used
+        .page_nxt_chn2      (page_ready_chn2), //rpage_nxt_chn0), not used
         .buf_run2           (), //buf_run2),
         .buf_wr_chn2        (buf_wr_chn2), // output
         .buf_wpage_nxt_chn2 (buf_wpage_nxt_chn2), // output
@@ -1813,7 +1802,7 @@ module  mcntrl393 #(
         .need_rq3           (need_rq3), // input
         .channel_pgm_en3    (channel_pgm_en3), // output reg 
         .seq_done3          (seq_done3), // output
-        .page_nxt_chn3      (page_nxt_chn3), //rpage_nxt_chn0), not used
+        .page_nxt_chn3      (page_ready_chn3), //rpage_nxt_chn0), not used
         .buf_run3           (), //buf_run3),
         .buf_wr_chn3        (buf_wr_chn3), // output
         .buf_wpage_nxt_chn3 (buf_wpage_nxt_chn3), // output
@@ -1827,7 +1816,7 @@ module  mcntrl393 #(
         .need_rq4           (need_rq4), // input
         .channel_pgm_en4    (channel_pgm_en4), // output reg 
         .seq_done4          (seq_done4), // output
-        .page_nxt_chn4      (page_nxt_chn4), //rpage_nxt_chn0), not used
+        .page_nxt_chn4      (page_ready_chn4), //rpage_nxt_chn0), not used
         .buf_run4           (), //buf_run4),
         .buf_wr_chn4        (buf_wr_chn4), // output
         .buf_wpage_nxt_chn4 (buf_wpage_nxt_chn4), // output
@@ -1881,7 +1870,7 @@ module  mcntrl393 #(
         .need_rq12          (cmprs_need[0]),               // input
         .channel_pgm_en12   (cmprs_channel_pgm_en[0]),     // output reg 
         .seq_done12         (cmprs_seq_done[0]),           // output
-        .page_nxt_chn12     (cmprs_next_page[0]),          // output ???
+        .page_nxt_chn12     (cmprs_page_ready[0]),          // output ???
         .buf_run12          (), // output
         .buf_wr_chn12       (cmprs_buf_we[0]),             // output
         .buf_wpage_nxt_chn12(cmprs_buf_wpage_nxt[0]),      // output
@@ -1892,7 +1881,7 @@ module  mcntrl393 #(
         .need_rq13          (cmprs_need[1]),               // input
         .channel_pgm_en13   (cmprs_channel_pgm_en[1]),     // output reg 
         .seq_done13         (cmprs_seq_done[1]),           // output
-        .page_nxt_chn13     (cmprs_next_page[1]),          // output ???
+        .page_nxt_chn13     (cmprs_page_ready[1]),          // output ???
         .buf_run13          (), // output
         .buf_wr_chn13       (cmprs_buf_we[1]),             // output
         .buf_wpage_nxt_chn13(cmprs_buf_wpage_nxt[1]),      // output
@@ -1903,7 +1892,7 @@ module  mcntrl393 #(
         .need_rq14          (cmprs_need[2]),               // input
         .channel_pgm_en14   (cmprs_channel_pgm_en[2]),     // output reg 
         .seq_done14         (cmprs_seq_done[2]),           // output
-        .page_nxt_chn14     (cmprs_next_page[2]),          // output ???
+        .page_nxt_chn14     (cmprs_page_ready[2]),          // output ???
         .buf_run14          (), // output
         .buf_wr_chn14       (cmprs_buf_we[2]),             // output
         .buf_wpage_nxt_chn14(cmprs_buf_wpage_nxt[2]),      // output
@@ -1914,7 +1903,7 @@ module  mcntrl393 #(
         .need_rq15          (cmprs_need[3]),               // input
         .channel_pgm_en15   (cmprs_channel_pgm_en[3]),     // output reg 
         .seq_done15         (cmprs_seq_done[3]),           // output
-        .page_nxt_chn15     (cmprs_next_page[3]),          // output ???
+        .page_nxt_chn15     (cmprs_page_ready[3]),          // output ???
         .buf_run15          (), // output
         .buf_wr_chn15       (cmprs_buf_we[3]),             // output
         .buf_wpage_nxt_chn15(cmprs_buf_wpage_nxt[3]),      // output

sensor/sens_histogram.v

@@ -58,7 +58,8 @@ module  sens_histogram #(
     reg  [31:0] to_inc;
     wire [31:0] hist_new;
     reg         hist_rwen;  // read/write enable
-    reg   [2:0] hist_regen; // bram output register enable: [0] - ren, [1] - regen, [2] - next after regen
+//    reg   [2:0] hist_regen; // bram output register enable: [0] - ren, [1] - regen, [2] - next after regen
+    reg   [1:0] hist_regen; // bram output register enable: [0] - ren, [1] - regen, [2] - next after regen
     reg         hist_we;    // bram write enable
     reg         hist_bank_mclk;
     
@@ -204,7 +205,8 @@ module  sens_histogram #(
             
         end
         hist_rwen <= (woi[0] & ~pclk_sync) || (woi[2] & pclk_sync);
-        hist_regen <= {hist_regen[1:0], woi[0] & ~pclk_sync};
+//        hist_regen <= {hist_regen[1:0], woi[0] & ~pclk_sync};
+        hist_regen <= {hist_regen[0], woi[0] & ~pclk_sync};
         hist_we <= woi[2] & pclk_sync;
         
         if     (woi[0] & ~pclk_sync) hist_rwaddr <= hist_addr;

sensor/sens_parallel12.v

@@ -393,8 +393,10 @@ module  sens_parallel12 #(
                 .ipclk2x        (ipclk2x),         // input
                 .rst            (rst),             // input
                 .mclk           (mclk),            // input
-                .dly_data       (data_r[8*((i+2)&3)+:8]), // input[7:0] alternating bytes of 32-bit word
-                .set_idelay     (set_pxd_delay[(i+2)>>2]),// input 0 for pxd[3:2], 1 for pxd[7:4], 2 for pxd [11:8]
+//                .dly_data       (data_r[8*((i+2)&3)+:8]), // input[7:0] alternating bytes of 32-bit word
+//                .set_idelay     (set_pxd_delay[(i+2)>>2]),// input 0 for pxd[3:2], 1 for pxd[7:4], 2 for pxd [11:8]
+                .dly_data       (data_r[8 * (i & 3) +: 8]), // input[7:0] alternating bytes of 32-bit word
+                .set_idelay     (set_pxd_delay[i >> 2]),// input 0 for pxd[3:2], 1 for pxd[7:4], 2 for pxd [11:8]
                 .ld_idelay      (ld_idelay),       // input
                 .quadrant       (quadrants[1:0])   // input[1:0] 
             );

sensor/sensor_channel.v

@@ -370,7 +370,7 @@ module  sensor_channel#(
         .status_ad             (sens_i2c_status_ad), // output[7:0] 
         .status_rq             (sens_i2c_status_rq), // output
         .status_start          (sens_i2c_status_start), // input
-        .frame_sync      (), // input
+        .frame_sync            (sof_out_mclk), // input
         .scl                   (sns_scl), // inout
         .sda                   (sns_sda) // inout
     );
@@ -474,7 +474,7 @@ module  sensor_channel#(
     ) sens_sync_i (
         .rst          (rst), // input
         .pclk         (pclk), // input
-        .mclk         (), // input
+        .mclk         (mclk), // input
         .en(), // input
         .sof_in       (sof), // input
         .eof_in       (eof), // input

sensor/sensor_i2c.v

@@ -171,7 +171,8 @@ module  sensor_i2c#(
      wire          set_status_w;
 
      reg            [1:0] wen_r;
-     reg            [1:0] wen_fifo;
+//     reg            [1:0] wen_fifo;
+     reg            wen_fifo; // [1] was not used - we_fifo_wp was used instead
 
      
      assign set_ctrl_w = we_cmd && (wa == SENSI2C_CTRL );// ==0
@@ -232,8 +233,8 @@ module  sensor_i2c#(
     always @ (posedge mclk) begin
         if (wen) di_r <= di; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long
         wen_r    <= {wen_r[0],wen}; // is it needed?      
-        wen_fifo <= {wen_fifo[0],we_rel || we_abs};      
-        
+//        wen_fifo <= {wen_fifo[0],we_rel || we_abs};      
+        wen_fifo <= we_rel || we_abs;              
          
 // signals related to writing to i2c FIFO
 // delayed versions of address, data write strobe
@@ -292,13 +293,15 @@ module  sensor_i2c#(
 //      we_fifo_wp <= wen || wpage0_inc; // during commands and during reset?
 
 ///   we_fifo_wp <= wen_fifo[0] || wpage0_inc; // during commands and during reset?
-      we_fifo_wp <= wen_fifo[0] || we_rel || we_abs; // ??
+//      we_fifo_wp <= wen_fifo[0] || we_rel || we_abs; // ??
+      we_fifo_wp <= wen_fifo || we_rel || we_abs; // ??
       
 //     reg            [1:0] wen_r;
 //     reg            [1:0] wen_fifo;
       
       
-       if (wen_fifo[0])  fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
+//       if (wen_fifo[0])  fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
+       if (wen_fifo)  fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
        
        // write to dual-port pointer memory
        if (we_fifo_wp) fifo_wr_pointers[wpage_wr] <= wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1); 
@@ -306,11 +309,12 @@ module  sensor_i2c#(
         fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri
 // command i2c fifo (RAMB16_S9_S18)
 
-      if (wen_fifo[0]) i2c_cmd_wa <= {wpage_wr[3:0],fifo_wr_pointers_outw[5:0]};
+//      if (wen_fifo[0]) i2c_cmd_wa <= {wpage_wr[3:0],fifo_wr_pointers_outw[5:0]};
+      if (wen_fifo) i2c_cmd_wa <= {wpage_wr[3:0],fifo_wr_pointers_outw[5:0]};
 //      if (wen_d[1]) i2c_cmd_wa[10:1] <= {wpage_wr[3:0],fifo_wr_pointers_outw[5:0]};
 //        i2c_cmd_wa[0] <= !wen_d[1]; // 0 for the first in a pair, 1 - for the second
   //    i2c_cmd_we    <=  !reset_cmd && (wen_d[1]  || (i2c_cmd_we && !wen_d[3])); //reset_cmd added to keep simulator happy
-      i2c_cmd_we    <=  !reset_cmd && wen_fifo[0];
+      i2c_cmd_we    <=  !reset_cmd && wen_fifo; // [0];
         
 // signals related to reading from i2c FIFO
       if      (reset_on)      page_r<=0;

timing/rtc393.v

@@ -177,7 +177,7 @@ module  rtc393 #(
         .EXTRA_WORDS         (2),
         .EXTRA_REG_ADDR      (RTC_SEC_USEC_ADDR)
     ) status_generate_i (
-        .rst           (), // input
+        .rst           (rst), // input
         .clk           (mclk), // input
         .we            (set_status_w), // input
         .wd            (cmd_data[7:0]), // input[7:0] 

timing/timestamp_snapshot.v

@@ -45,10 +45,14 @@ module  timestamp_snapshot(
     end
     
     always @(posedge rst or posedge sclk) begin
-        pulse_busy_r <= pulse_busy;
         if      (rst)                          snd <= 0;
         else if (!pulse_busy && pulse_busy_r)  snd <= 1;
         else if ((&cntr) || snap)              snd <= 0;
+    end
+
+    always @(posedge sclk) begin
+
+        pulse_busy_r <= pulse_busy;
         
         if (!snd) cntr <= 0;
         else      cntr <=  cntr + 1;
@@ -63,8 +67,6 @@ module  timestamp_snapshot(
             3'h6: ts_data <= {4'b0,sec_usec_snap[51:48]};
             3'h7: ts_data <= 8'b0;
         endcase
-        
-        
     end
     
     pulse_cross_clock #(

util_modules/clocks393.v

@@ -123,10 +123,11 @@ module  clocks393#(
     wire ffclk1_rst = reset_clk[6];
     
     always @ (posedge mclk or posedge rst) begin
-        if (rst)        reset_clk <= 0;
-        if (set_ctrl_w) reset_clk <= {cmd_data[10:8], cmd_data[3:0]}; 
-        if (rst)        pwrdwn_clk <= 0;
-        if (set_ctrl_w) pwrdwn_clk <= cmd_data[7:4]; 
+        if (rst)             reset_clk <= 0;
+        else if (set_ctrl_w) reset_clk <= {cmd_data[10:8], cmd_data[3:0]};
+         
+        if (rst)             pwrdwn_clk <= 0;
+        else if (set_ctrl_w) pwrdwn_clk <= cmd_data[7:4]; 
     end
     assign status_data = {test_clk, locked, extra_status};
     always @ (posedge memclk or posedge memclk_rst) if (memclk_rst) test_clk[0] <= ~test_clk[0];
@@ -154,7 +155,7 @@ module  clocks393#(
         .PAYLOAD_BITS        (9),
         .REGISTER_STATUS     (0)
     ) status_generate_i (
-        .rst           (), // input
+        .rst           (rst), // input
         .clk           (mclk), // input
         .we            (set_status_w), // input
         .wd            (cmd_data[7:0]), // input[7:0] 

util_modules/gpio393.v

@@ -187,7 +187,7 @@ module  gpio393  #(
         .PAYLOAD_BITS        (12),
         .REGISTER_STATUS     (1)
     ) status_generate_i (
-        .rst           (), // input
+        .rst           (rst), // input
         .clk           (mclk), // input
         .we            (set_status_w), // input
         .wd            (cmd_data[7:0]), // input[7:0] 

util_modules/status_generate.v

@@ -175,10 +175,10 @@ endmodule
 //module that generates several 32-bit words and optionally status message
 module  status_generate_extra #(
     parameter STATUS_REG_ADDR=   7, // status register address to direct data to
-    parameter PAYLOAD_BITS =     15, //6   // >=2! (2..26)
-    parameter REGISTER_STATUS =  1,  // 1 - register input status data (for different clock domains),  0 - do not register (same domain)
-    parameter EXTRA_WORDS=       1, // should always be >0
-    parameter EXTRA_WORDS_LN2 =  3, // number of bits to select among extra words and (optional) status 
+    parameter PAYLOAD_BITS =     1, ///15, //6   // >=2! (2..26)
+    parameter REGISTER_STATUS =  0, ///1,  // 1 - register input status data (for different clock domains),  0 - do not register (same domain)
+    parameter EXTRA_WORDS=       2, ///1, // should always be >0
+//    parameter EXTRA_WORDS_LN2 =  3, // number of bits to select among extra words and (optional) status 
     // if EXTRA_WORDS >0 the mesasges with these extra data will be generated and sent before the status message itself
     // if PAYLOAD_BITS == 0, then one status bit will still have to be provided (status input will have width of 1+32*EXTRA_WORDS),
     // but the status message will not be sent - only the data words
@@ -195,6 +195,8 @@ module  status_generate_extra #(
     input                    start   // acknowledge of address (first byte) from downsteram   
 );
 
+//    localparam EXTRA_WORDS_LN2 =  $clog2(EXTRA_WORDS+1); // number of bits to select among extra words and (optional) status 
+    localparam EXTRA_WORDS_LN2 =  clogb2(EXTRA_WORDS+1); // number of bits to select among extra words and (optional) status 
 // multiple of 32 bits added to PAYLOAD_BITS, these words are not compared but always sent before status to locations above/below status one
 // no need to register extra words - status should be modified after the extra.
     localparam STATUS_BITS = ((PAYLOAD_BITS > 0) ? PAYLOAD_BITS: 1);
@@ -235,18 +237,19 @@ module  status_generate_extra #(
     
     reg  [EXTRA_WORDS_LN2-1:0] msg_num;
     wire                [31:0] dont_care= 32'bx;
-    wire                [31:0] pre_mux [0:(1<<EXTRA_WORDS_LN2)-1];
+//    wire                [31:0] pre_mux [0:(1<<EXTRA_WORDS_LN2)-1];
+    wire [32 * (1<<EXTRA_WORDS_LN2) -1 :0] pre_mux;
     wire                [31:0] status32=(NUM_BYTES>2) ?
          ((ALIGNED_STATUS_WIDTH < 26)?
-              {{(26-ALIGNED_STATUS_WIDTH){1'b0}},aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,status_r0[1:0]}:
-              {                                  aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,status_r0[1:0]}):
-              {24'b0,seq,status_r0[1:0]};
+              {{(26-ALIGNED_STATUS_WIDTH){1'b0}},aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,aligned_status[1:0]}:
+              {                                  aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,aligned_status[1:0]}):
+              {24'b0,seq,aligned_status[1:0]};
     genvar i;
     generate
         for (i = 0; i <  (1<<EXTRA_WORDS_LN2); i=i+1) begin:gen_cyc1
-            assign pre_mux[i] = (i < EXTRA_WORDS)?  //status[PAYLOAD_BITS + 32*i +:32] : // actually change order!
-                                {status[PAYLOAD_BITS + 32*i + 24 +:8],status[PAYLOAD_BITS + 32*i +:24] }:
-                                (((i == EXTRA_WORDS) && (PAYLOAD_BITS > 0)) ? status32 : dont_care);
+            assign pre_mux[32 * i +: 32] = (i < EXTRA_WORDS)?  //status[PAYLOAD_BITS + 32*i +:32] : // actually change order!
+                                               {status[PAYLOAD_BITS + 32*i + 24 +:8],status[PAYLOAD_BITS + 32*i +:24] }:
+                                               (((i == EXTRA_WORDS) && (PAYLOAD_BITS > 0)) ? status32 : dont_care);
         end
     endgenerate
     
@@ -256,7 +259,7 @@ module  status_generate_extra #(
     assign need_to_send=cmd_pend || (mode[1] && status_changed_r); // latency
     assign rq=rq_r[0]; // NUM_BYTES-2];
     assign mode_w=wd[7:6];
-    assign status_r0 = REGISTER_STATUS? status_r0r : status;
+    assign status_r0 = REGISTER_STATUS? status_r0r : status[STATUS_BITS-1:0];
     
     assign msg_is_last =   msg1hot[NUM_MSG-1];
     assign msg_is_status = msg_is_last && (PAYLOAD_BITS > 0);
@@ -314,9 +317,19 @@ module  status_generate_extra #(
     end
     
     always @ (posedge clk) begin
-        if      (!rq)            data <= {next_addr, pre_mux[msg_num]};
+        if      (!rq)            data <= {next_addr, pre_mux[32 * msg_num +:32]};
         else if (start || start) data <= data >> 8;
     end
+ //http://www.edaboard.com/thread177879.html
+    function integer clogb2;
+        input [31:0] value;
+        integer  i;
+        begin
+            clogb2 = 0;
+            for(i = 0; 2**i < value; i = i + 1)
+                clogb2 = i + 1;
+       end
+    endfunction
     
     
 endmodule

util_modules/table_ad_receive.v

@@ -29,7 +29,7 @@ module  table_ad_receive #(
     input                    [7:0] ser_d,      // byte-wide address/data
     input            [NUM_CHN-1:0] dv,         // data valid - active for each address or data bytes
     output     [23-MODE_16_BITS:0] ta,         // table address
-    output [(MODE_16_BITS?15:7):0] td,         // 8/16 bit table data
+    output [(MODE_16_BITS?15:7):0] td,         // 8/16 bit table data, LSB first
     output           [NUM_CHN-1:0] twe         // table write enable
 );
     reg                  [23:0] addr_r;
@@ -48,7 +48,7 @@ module  table_ad_receive #(
         else if (|twe_r)       addr_r[23:0] <= addr_r[23:0] + 1;
     end
     generate
-        if (MODE_16_BITS) always @ (posedge clk) td_r[15:0] <= {ser_d[7:0],td_r[15:8]};
+        if (MODE_16_BITS) always @ (posedge clk) td_r[15:0] <= {ser_d[7:0],td_r[15:8]}; //LSB received first
         else              always @ (posedge clk) td_r[ 7:0] <= ser_d[7:0];
     endgenerate
 

util_modules/table_ad_transmit.v

@@ -30,7 +30,7 @@ module  table_ad_transmit#(
     input                         a_not_d_in, // address/not data input (valid @ we)
     input                         we,         // write address/data (single cycle) with at least 5 inactive between
     input                  [31:0] din,        // 32 bit data to send or 8-bit channel select concatenated with 24-bit byte address (@we)
-    output                 [ 7:0] ser_d,      // 8-bit address/data to be sent to submodules that have table write port(s)
+    output                 [ 7:0] ser_d,      // 8-bit address/data to be sent to submodules that have table write port(s), LSB first
     output reg                    a_not_d,    // sending adderass / not data - valid during all bytes
     output reg [NUM_CHANNELS-1:0] chn_en      // sending  address or data
 );

wrap/ram18_var_w_var_r.v

@@ -189,8 +189,8 @@ module  ram18_32w_32r
       input                  [ 3:0] web,      // write byte enable
       input                  [31:0] data_in  // data out
     );
-    localparam  PWIDTH_WR=72;
-    localparam  PWIDTH_RD=72;
+    localparam  PWIDTH_WR=36;
+    localparam  PWIDTH_RD=36;
     
     RAMB18E1
     #(
@@ -213,9 +213,9 @@ module  ram18_32w_32r
     (
         // Port A (Read port in SDP mode):
         .DOADO           (data_out[15:0]), // Port A data/LSB data[15:0], output
-        .DOPADOP         (data_out[17:16]),// Port A parity/LSB parity[2:0], output
+        .DOPADOP         (),               // Port A parity/LSB parity[2:0], output
         .DIADI           (data_in[15:0]),  // Port A data/LSB data[15:0], input
-        .DIPADIP         (data_in[17:16]), // Port A parity/LSB parity[2:0], input
+        .DIPADIP         (),               // Port A parity/LSB parity[2:0], input
         .ADDRARDADDR     ({raddr[8:0],5'b11111}),  // Port A (read port in SDP) address [13:0], unused should be high, input
         .CLKARDCLK       (rclk),           // Port A (read port in SDP) clock, input
         .ENARDEN         (ren),            // Port A (read port in SDP) Enable, input
@@ -366,7 +366,7 @@ module  ram18_lt32w_32r
     (
         // Port A (Read port in SDP mode):
         .DOADO           (data_out[15:0]), // Port A data/LSB data[15:0], output
-        .DOPADOP         (data_out[17:16]),// Port A parity/LSB parity[3:0], output
+        .DOPADOP         (),               // Port A parity/LSB parity[3:0], output
         .DIADI           (16'h0),          // Port A data/LSB data[31:0], input
         .DIPADIP         (2'h0),           // Port A parity/LSB parity[3:0], input
         .ADDRARDADDR     ({raddr[8:0],5'b11111}),  // Port A (read port in SDP) address [15:0]. used from [14] down, unused should be high, input
@@ -412,7 +412,7 @@ module  ram18_32w_lt32r
       input                         [ 3:0] web,      // write byte enable
       input                         [31:0] data_in   // data out
     );
-    localparam  PWIDTH_WR = 72;
+    localparam  PWIDTH_WR = 36;
     localparam  PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
     localparam  WIDTH_RD  = 1 << LOG2WIDTH_RD;
     wire          [15:0] data_out16;

x393.v

@@ -88,7 +88,10 @@ module  x393 #(
     input                        ffclk0n, // Y11
     input                        ffclk1p, // W14
     input                        ffclk1n  // W13
+    ,output                      DUMMY_TO_KEEP
+    
 );
+ assign DUMMY_TO_KEEP = frst[2] && fclk[1];
 
 //    localparam ADDRESS_NUMBER=15;
 //    localparam COLADDR_NUMBER=10;
@@ -1170,7 +1173,7 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
     wire [ 3:0] afi0_awcache;     // output[3:0] 
     wire [ 2:0] afi0_awprot;     // output[2:0] 
     wire [ 3:0] afi0_awlen;     // output[3:0] 
-    wire [ 2:0] afi0_awsize;     // output[2:0] 
+    wire [ 1:0] afi0_awsize;     // output[2:0] 
     wire [ 1:0] afi0_awburst;     // output[1:0] 
     wire [ 3:0] afi0_awqos;     // output[3:0] 
     wire [63:0] afi0_wdata;     // output[63:0] 
@@ -1194,7 +1197,7 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
     wire [ 3:0] afi0_arcache;     // output[3:0] 
     wire [ 2:0] afi0_arprot;     // output[2:0] 
     wire [ 3:0] afi0_arlen;     // output[3:0] 
-    wire [ 2:0] afi0_arsize;     // output[2:0] 
+    wire [ 1:0] afi0_arsize;     // output[2:0] 
     wire [ 1:0] afi0_arburst;     // output[1:0] 
     wire [ 3:0] afi0_arqos;     // output[3:0] 
     wire [63:0] afi0_rdata;     // input[63:0] 
@@ -1474,43 +1477,6 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
         .sns_ctl           ({sns4_ctl, sns3_ctl, sns2_ctl, sns1_ctl}),         // inout
         .sns_pg            ({sns4_pg, sns3_pg, sns2_pg, sns1_pg}),             // inout
 
-/*
-        .sns1_dp            (sns1_dp),             // inout[7:0] 
-        .sns1_dn            (sns1_dn),             // inout[7:0] 
-        .sns1_clkp          (sns1_clkp),           // inout
-        .sns1_clkn          (sns1_clkn),           // inout
-        .sns1_scl           (sns1_scl),            // inout
-        .sns1_sda           (sns1_sda),            // inout
-        .sns1_ctl           (sns1_ctl),            // inout
-        .sns1_pg            (sns1_pg),             // inout
-
-        .sns2_dp            (sns2_dp),             // inout[7:0] 
-        .sns2_dn            (sns2_dn),             // inout[7:0] 
-        .sns2_clkp          (sns2_clkp),           // inout
-        .sns2_clkn          (sns2_clkn),           // inout
-        .sns2_scl           (sns2_scl),            // inout
-        .sns2_sda           (sns2_sda),            // inout
-        .sns2_ctl           (sns2_ctl),            // inout
-        .sns2_pg            (sns2_pg),             // inout
-
-        .sns3_dp            (sns3_dp),             // inout[7:0] 
-        .sns3_dn            (sns3_dn),             // inout[7:0] 
-        .sns3_clkp          (sns3_clkp),           // inout
-        .sns3_clkn          (sns3_clkn),           // inout
-        .sns3_scl           (sns3_scl),            // inout
-        .sns3_sda           (sns3_sda),            // inout
-        .sns3_ctl           (sns3_ctl),            // inout
-        .sns3_pg            (sns3_pg),             // inout
-
-        .sns4_dp            (sns4_dp),             // inout[7:0] 
-        .sns4_dn            (sns4_dn),             // inout[7:0] 
-        .sns4_clkp          (sns4_clkp),           // inout
-        .sns4_clkn          (sns4_clkn),           // inout
-        .sns4_scl           (sns4_scl),            // inout
-        .sns4_sda           (sns4_sda),            // inout
-        .sns4_ctl           (sns4_ctl),            // inout
-        .sns4_pg            (sns4_pg),             // inout
-*/
         .rpage_set          (sens_rpage_set),      // input
         .rpage_next         (sens_rpage_next),     // input
         .buf_rd             (sens_buf_rd),         // input
@@ -1564,7 +1530,7 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
     wire [ 3:0] afi1_awcache;     // output[3:0] 
     wire [ 2:0] afi1_awprot;     // output[2:0] 
     wire [ 3:0] afi1_awlen;     // output[3:0] 
-    wire [ 2:0] afi1_awsize;     // output[2:0] 
+    wire [ 1:0] afi1_awsize;     // output[2:0] 
     wire [ 1:0] afi1_awburst;     // output[1:0] 
     wire [ 3:0] afi1_awqos;     // output[3:0] 
     wire [63:0] afi1_wdata;     // output[63:0] 
@@ -1590,7 +1556,7 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
     wire [ 3:0] afi2_awcache;     // output[3:0] 
     wire [ 2:0] afi2_awprot;     // output[2:0] 
     wire [ 3:0] afi2_awlen;     // output[3:0] 
-    wire [ 2:0] afi2_awsize;     // output[2:0] 
+    wire [ 1:0] afi2_awsize;     // output[2:0] 
     wire [ 1:0] afi2_awburst;     // output[1:0] 
     wire [ 3:0] afi2_awqos;     // output[3:0] 
     wire [63:0] afi2_wdata;     // output[63:0] 

x393.xdc

@@ -204,14 +204,16 @@ set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
 set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
 
 #    output                      DUMMY_TO_KEEP,  // to keep PS7 signals from "optimization"
-set_property IOSTANDARD SSTL15 [get_ports {DUMMY_TO_KEEP}]
-set_property PACKAGE_PIN E3 [get_ports {DUMMY_TO_KEEP}]
+#set_property IOSTANDARD SSTL15 [get_ports {DUMMY_TO_KEEP}]
+set_property PACKAGE_PIN T11 [get_ports {DUMMY_TO_KEEP}]
 
 #not yet used, just for debugging
 #    input                      memclk,
 #set_property IOSTANDARD SSTL15 [get_ports {memclk}]
 set_property PACKAGE_PIN M5 [get_ports {memclk}]
 
+
+
 # ================= Sensor port 0 =================
 #        inout                  [7:0] sns1_dp,
 #        inout                  [7:0] sns1_dn,

x393_timing.xdc

@@ -72,7 +72,8 @@ create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
 create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
 create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
 create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
-create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre ]
+#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre ]
+create_generated_clock -name mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk
 create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]