made tools run successfully, no timing errors (8b0a0f11) · Commits · Elphel / x393

.project

+15 −15

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		@@ -62,77 +62,77 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150722003723406.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150722181016920.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150722003207037.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150722181016920.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150722003723406.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150722181016920.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150722003207037.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150722181016920.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150722003207037.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150722181016920.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150722003723406.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150722181016920.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150722002329036.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150722180528066.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150722003723406.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150722181016920.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150722002329036.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150722180528066.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150722003723406.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150722181016920.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150722002329036.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150722180528066.log</location>
		</link>
		<link>
		<name>vivado_state/x393-opt-phys.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150722003723406.dcp</location>
		<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150722181016920.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393-place.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_state/x393-place-20150722003207037.dcp</location>
		<location>/home/andrey/git/x393/vivado_state/x393-place-20150722181016920.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393-route.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_state/x393-route-20150722003723406.dcp</location>
		<location>/home/andrey/git/x393/vivado_state/x393-route-20150722181016920.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393-synth.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_state/x393-synth-20150722002329036.dcp</location>
		<location>/home/andrey/git/x393/vivado_state/x393-synth-20150722180528066.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

.settings/com.elphel.vdt.VivadoSynthesis.prefs

+1 −1

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		@@ -4,6 +4,6 @@ VivadoSynthesis_115_flatten_hierarchy=none
		VivadoSynthesis_127_verbose=true
		VivadoSynthesis_81_parser_mode=1
		VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
		VivadoSynthesis_95_ShowInfo=false
		VivadoSynthesis_95_ShowInfo=true
		com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
		eclipse.preferences.version=1

compressor_jp/huff_fifo393.v

+61 −63

Original line number	Diff line number	Diff line
		@@ -34,13 +34,16 @@ module huff_fifo393 (
		input want_read,
		input want_read_early,
		output reg dav, // FIFO output latch has data (fifo_or_full)
		output reg [15:0] q_latch); // output data
		`ifdef INFER_LATCHES
		output reg [15:0] q_latch
		`else
		output [15:0] q_latch
		`endif
		); // output data

		reg [9:0] wa;
		reg [9:0] sync_wa; // delayed wa, re_latch-calculated at output clock
		reg [9:0] ra_r;
		reg [9:0] ra_latch;
		reg load_q;
		wire [15:0] fifo_o;
		reg ds1; // ds delayed by one xclk to give time to block ram to write data. Not needed likely.
		reg synci;
		@@ -49,12 +52,20 @@ module huff_fifo393 (
		reg en2x; // en sync to xclk2x;

		reg re_r;
		reg re_latch;
		reg fifo_dav; // RAM output reg has data
		reg dav_and_fifo_dav;
		wire ram_dav; // RAM has data inside
		reg [9:0] diff_a;
		wire next_re;
		reg load_q;
		`ifdef INFER_LATCHES
		reg [9:0] ra_latch;
		reg re_latch;
		`else
		wire [9:0] ra_latch;
		wire re_latch;
		`endif



		always @ (posedge xclk) begin // input stage, no overrun detection
		@@ -90,71 +101,58 @@ module huff_fifo393 (
		else if (!sync_we && next_re) diff_a[9:0] <= diff_a[9:0]-1;

		end
		/*
		LD i_re (.Q(re_latch),.G(xclk2x),.D(next_re));

		LD i_ra9 (.Q(ra_latch[9]),.G(xclk2x),.D(ra_r[9]));
		LD i_ra8 (.Q(ra_latch[8]),.G(xclk2x),.D(ra_r[8]));
		LD i_ra7 (.Q(ra_latch[7]),.G(xclk2x),.D(ra_r[7]));
		LD i_ra6 (.Q(ra_latch[6]),.G(xclk2x),.D(ra_r[6]));
		LD i_ra5 (.Q(ra_latch[5]),.G(xclk2x),.D(ra_r[5]));
		LD i_ra4 (.Q(ra_latch[4]),.G(xclk2x),.D(ra_r[4]));
		LD i_ra3 (.Q(ra_latch[3]),.G(xclk2x),.D(ra_r[3]));
		LD i_ra2 (.Q(ra_latch[2]),.G(xclk2x),.D(ra_r[2]));
		LD i_ra1 (.Q(ra_latch[1]),.G(xclk2x),.D(ra_r[1]));
		LD i_ra0 (.Q(ra_latch[0]),.G(xclk2x),.D(ra_r[0]));
		*/
		always @* if (xclk2x) re_latch <= next_re;
		always @* if (xclk2x) ra_latch <= ra_r;


		always @ (posedge xclk2x) begin
		load_q <= dav?want_read_early:re_r;
		end
		/*
		LD_1 i_q15 (.Q( q_latch[15]),.G(xclk2x),.D(load_q?fifo_o[15]:q_latch[15]));
		LD_1 i_q14 (.Q( q_latch[14]),.G(xclk2x),.D(load_q?fifo_o[14]:q_latch[14]));
		LD_1 i_q13 (.Q( q_latch[13]),.G(xclk2x),.D(load_q?fifo_o[13]:q_latch[13]));
		LD_1 i_q12 (.Q( q_latch[12]),.G(xclk2x),.D(load_q?fifo_o[12]:q_latch[12]));
		LD_1 i_q11 (.Q( q_latch[11]),.G(xclk2x),.D(load_q?fifo_o[11]:q_latch[11]));
		LD_1 i_q10 (.Q( q_latch[10]),.G(xclk2x),.D(load_q?fifo_o[10]:q_latch[10]));
		LD_1 i_q9 (.Q( q_latch[ 9]),.G(xclk2x),.D(load_q?fifo_o[ 9]:q_latch[ 9]));
		LD_1 i_q8 (.Q( q_latch[ 8]),.G(xclk2x),.D(load_q?fifo_o[ 8]:q_latch[ 8]));
		LD_1 i_q7 (.Q( q_latch[ 7]),.G(xclk2x),.D(load_q?fifo_o[ 7]:q_latch[ 7]));
		LD_1 i_q6 (.Q( q_latch[ 6]),.G(xclk2x),.D(load_q?fifo_o[ 6]:q_latch[ 6]));
		LD_1 i_q5 (.Q( q_latch[ 5]),.G(xclk2x),.D(load_q?fifo_o[ 5]:q_latch[ 5]));
		LD_1 i_q4 (.Q( q_latch[ 4]),.G(xclk2x),.D(load_q?fifo_o[ 4]:q_latch[ 4]));
		LD_1 i_q3 (.Q( q_latch[ 3]),.G(xclk2x),.D(load_q?fifo_o[ 3]:q_latch[ 3]));
		LD_1 i_q2 (.Q( q_latch[ 2]),.G(xclk2x),.D(load_q?fifo_o[ 2]:q_latch[ 2]));
		LD_1 i_q1 (.Q( q_latch[ 1]),.G(xclk2x),.D(load_q?fifo_o[ 1]:q_latch[ 1]));
		LD_1 i_q0 (.Q( q_latch[ 0]),.G(xclk2x),.D(load_q?fifo_o[ 0]:q_latch[ 0]));
		*/
		always @* if (~xclk2x) begin

		`ifdef INFER_LATCHES
		always @* if (xclk2x) re_latch <= next_re;
		always @* if (xclk2x) ra_latch <= ra_r;
		always @* if (~xclk2x)
		if (load_q) q_latch <= fifo_o;
		end
		/*
		RAMB16_S18_S18 i_fifo (
		.DOA(), // Port A 16-bit Data Output
		.DOPA(), // Port A 2-bit Parity Output
		.ADDRA(wa[9:0]), // Port A 10-bit Address Input
		.CLKA(xclk), // Port A Clock
		.DIA(di[15:0]), // Port A 16-bit Data Input
		.DIPA(2'b0), // Port A 2-bit parity Input
		.ENA(ds), // Port A RAM Enable Input
		.SSRA(1'b0), // Port A Synchronous Set/Reset Input
		.WEA(1'b1), // Port A Write Enable Input

		.DOB(fifo_o[15:0]),// Port B 16-bit Data Output
		.DOPB(), // Port B 2-bit Parity Output
		.ADDRB(ra_latch[9:0]), // Port B 10-bit Address Input
		.CLKB(xclk2x), // Port B Clock
		.DIB(16'b0), // Port B 16-bit Data Input
		.DIPB(2'b0), // Port-B 2-bit parity Input
		.ENB(re_latch), // PortB RAM Enable Input
		.SSRB(1'b0), // Port B Synchronous Set/Reset Input
		.WEB(1'b0) // Port B Write Enable Input

		`else
		latch_g_ce #(
		.WIDTH (1),
		.INIT (0),
		.IS_CLR_INVERTED (0),
		.IS_G_INVERTED (0)
		) latch_re_i (
		.rst (1'b0), // input
		.g (xclk2x), // input
		.ce (1'b1), // input
		.d_in (next_re), // input[0:0]
		.q_out (re_latch) // output[0:0]
		);
		*/

		latch_g_ce #(
		.WIDTH (10),
		.INIT (0),
		.IS_CLR_INVERTED (0),
		.IS_G_INVERTED (0)
		) latch_ra_i (
		.rst (1'b0), // input
		.g (xclk2x), // input
		.ce (1'b1), // input
		.d_in (ra_r), // input[0:0]
		.q_out (ra_latch) // output[0:0]
		);

		latch_g_ce #(
		.WIDTH (16),
		.INIT (0),
		.IS_CLR_INVERTED (0),
		.IS_G_INVERTED (1'b1) // inverted!
		) latch_q_i (
		.rst (1'b0), // input
		.g (xclk2x), // input
		.ce (load_q), // input
		.d_in (fifo_o), // input[0:0]
		.q_out (q_latch) // output[0:0]
		);
		`endif

		ram18_var_w_var_r #(
		.REGISTERS (0),

includes/x393_parameters.vh

+14 −2

Original line number	Diff line number	Diff line
		@@ -433,8 +433,20 @@
		parameter IPCLK_PHASE = 0.000,
		parameter IPCLK2X_PHASE = 0.000,

		parameter BUF_IPCLK = "BUFG", // "BUFR",
		parameter BUF_IPCLK2X = "BUFG", // "BUFR",
		// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
		// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",

		parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
		parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR",

		parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
		parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",

		parameter BUF_IPCLK_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
		parameter BUF_IPCLK2X_SENS2 = "BUFR", //G", // "BUFR",

		parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
		parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFR",

		parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
		parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)

memctrl/phy/dq_single.v

+2 −1

Original line number	Diff line number	Diff line
		@@ -121,7 +121,8 @@ iserdes_mem #(
		.rst(rst), // reset
		.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
		.ddly(dq_dly), // serial input from idelay
		.dout(dout[3:0]) // parallel data out
		.dout(dout[3:0]), // parallel data out
		.comb_out() // output
		);

		endmodule

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