Commits · 48b08174a5a20f807f013a109b8ce10b59ed5359 · Elphel / x393

19 Jul, 2015 1 commit
- working on synthesis errors · 48b08174
  Andrey Filippov authored 9 years ago
  
  48b08174
18 Jul, 2015 1 commit
- Trying synthesis, fixing revealed bugs · bf7c096d
  Andrey Filippov authored 9 years ago
  
  bf7c096d
17 Jul, 2015 1 commit
- adding synchronization and logger modules · 2585b4af
  Andrey Filippov authored 9 years ago
  
  2585b4af
15 Jul, 2015 3 commits
- replaced non-memory 2-d arrays with 1-d ones, added _ram suffix to all memories · baa32a59
  Andrey Filippov authored 9 years ago
  
  baa32a59
- Reverted changes - it was what I meant · 3946f6c4
  Andrey Filippov authored 9 years ago
  
  3946f6c4
- Working a top-level compressor module · bdfcabf1
  Andrey Filippov authored 9 years ago
  
  bdfcabf1
14 Jul, 2015 1 commit
- fixed potential ADDRESS_BITS+1 bus boundary tresspassing · 4d159459
  Alexey Grebenkin authored 9 years ago
  
  4d159459
12 Jul, 2015 4 commits
- Increase command adderss space, modified address map to fit sesnor/compressor related registers · cadd05c1
  Andrey Filippov authored 9 years ago
  
  cadd05c1
- implemented channel FIFO (mult_saxi_wr_inbuf) for mult_saxi_wr · d42644e2
  Andrey Filippov authored 9 years ago
  
  d42644e2
- Changed 'author' to full name · 41babf8a
  Andrey Filippov authored 9 years ago
  
  41babf8a
- implemented 4-channel data transfer to the system memory over a single s_axi · 5d61e6fb
  Andrey Filippov authored 9 years ago
  
  5d61e6fb
08 Jul, 2015 1 commit
- Moved histogram_saxi.v to axi/ subdirectory · f685f103
  Andrey Filippov authored 9 years ago
  
  f685f103
06 Jul, 2015 1 commit
- Fixed teplate error in the headers · 93e8aa42
  Andrey Filippov authored 9 years ago
  
  93e8aa42
05 Jul, 2015 1 commit
- typo fix in multiple files · f92c85e2
  Andrey Filippov authored 9 years ago
  
  f92c85e2
29 Jun, 2015 2 commits
- added status generation module for cmprs_afi_mux · 18addecb
  Andrey Filippov authored 9 years ago
  
  18addecb
- Working on cmprs_afi_mux.v, extracted 2 sub-modules: cmprs_afi_mux_ptr.v and... · d2699ad8
  Andrey Filippov authored 9 years ago
```
Working on cmprs_afi_mux.v, extracted 2 sub-modules: cmprs_afi_mux_ptr.v and cmprs_afi_mux_ptr_wresp.v
```
  d2699ad8
28 Jun, 2015 1 commit
- working on the afi multiplexer to trasfer up tp 4 compressor output data to the system memory · 3e682017
  Andrey Filippov authored 9 years ago
  
  3e682017
13 Jun, 2015 1 commit
- Working on compressors interaction with external memory buffer · 8b1599eb
  Andrey Filippov authored 9 years ago
  
  8b1599eb
06 May, 2015 1 commit
- Debugging hardware, added functionality to detect cache-related problems · cdf97c98
  Andrey Filippov authored 9 years ago
  
  cdf97c98
05 May, 2015 2 commits
- Fixed handling AXI write responce channel - both in work and simulation... · 988095ef
  Andrey Filippov authored 9 years ago
```
Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
```
  988095ef
- Fixed ddr3 -> system memory transfer · 0fda102e
  Andrey Filippov authored 9 years ago
  
  0fda102e
04 May, 2015 1 commit
- made membridge work in system -> videobuffer mode · 59a577c9
  Andrey Filippov authored 9 years ago
  
  59a577c9
30 Apr, 2015 2 commits
- more debuggin/simulation of the membridge module · 7274dadc
  Andrey Filippov authored 9 years ago
  
  7274dadc
- simulating/debugging · 8b79e3f7
  Andrey Filippov authored 9 years ago
  
  8b79e3f7
29 Apr, 2015 1 commit
- connecting new modules for membridge to top module and test fixture · 890bad1c
  Andrey Filippov authored 9 years ago
  
  890bad1c
28 Apr, 2015 1 commit
- Working on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp · 7a0fa46b
  Andrey Filippov authored 9 years ago
  
  7a0fa46b
28 Feb, 2015 1 commit
- working on synthesis with Vivado tools · 05378ee7
  Andrey Filippov authored 10 years ago
  
  05378ee7
22 Feb, 2015 1 commit
- re-organized top structure · ad0351ef
  Andrey Filippov authored 10 years ago
  
  ad0351ef
20 Feb, 2015 1 commit
- added another channel for testing - tile write · a445ef42
  Andrey Filippov authored 10 years ago
  
  a445ef42
16 Feb, 2015 1 commit
- more debugging · 7c5ab53d
  Andrey Filippov authored 10 years ago
  
  7c5ab53d
10 Feb, 2015 1 commit
- tested register writes, status generation, routing and reading · 9f629dc4
  Andrey Filippov authored 10 years ago
  
  9f629dc4
11 Jun, 2014 1 commit
- debugging hardware · 5450474d
  Andrey Filippov authored 10 years ago
  
  5450474d
01 Jun, 2014 2 commits
- bug fixes, implemented read pattern test, so all major DDR3 modes are tested:... · 01028931
  Andrey Filippov authored 10 years ago
```
bug fixes, implemented read pattern test, so all major DDR3 modes are tested: write and read leveling, write and read
```
  01028931
- added configuration for ISE, timing constraints for Vivado · 46cf253d
  Andrey Filippov authored 10 years ago
  
  46cf253d
22 May, 2014 1 commit
- added modules, simulating · c8904b67
  Andrey Filippov authored 10 years ago
  
  c8904b67
20 May, 2014 1 commit
- added modules to test ddrc phy over axi read/write · 5034058e
  Andrey Filippov authored 10 years ago
  
  5034058e
19 May, 2014 1 commit
- addint top level module to test pasrt of ddr controller · 03bce211
  Andrey Filippov authored 10 years ago
  
  03bce211
18 May, 2014 1 commit
- axi interface files added · f57364b8
  Andrey Filippov authored 10 years ago
  
  f57364b8