Working on compressors interaction with external memory buffer

axi/membridge.v

@@ -49,7 +49,7 @@ module  membridge#(
     // mcntrl_linear_rw.v interface
     output                        frame_start_chn, // input
     output                        next_page_chn, // input
-    input                         cmd_wrmem,      //
+    input                         cmd_wrmem,      // @mclk - writing to DDR3 mode (0 - reading from DDR3)
     input                         page_ready_chn, // output single mclk
     input                         frame_done_chn, // output single mclk
     input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn1, // output[15:0] @SuppressThisWarning VEditor unused (yet)

compressor_jp/color_proc393.v

@@ -27,7 +27,13 @@ module  color_proc393 (
          input          en,         // Enable (0 will reset states)
          input          en_sdc,     // enable subtracting of DC component
          input          go,         // pulse to star/restart (needed for each frame, repeat generated by the caller)
+         // TODO: Remove
          input   [25:0] nblocks,    // ***** was [17:0] number of 16x16 blocks to read (valid @ "go" pulse)
+         // NEW: Now number of SDRAM blobks (tiles) is not equal to number of macroblocks
+         input   [12:0] n_blocks_in_row,   // number of macroblocks in a macroblock row
+         input   [12:0] n_block_rows,      // number of macroblock rows in a frame
+//         input          reset_sdram_page,  // SDRAM buffer page may be reset (normally just increments for each new tile
+         // end of NEW
          output         eot,            // single-cycle end of transfer pulse
          input   [ 9:0] m_cb,       // [9:0] scale for CB - default 0.564 (10'h90)
          input   [ 9:0] m_cr,       // [9:0] scale for CB - default 0.713 (10'hb6)
@@ -114,7 +120,7 @@ module  color_proc393 (
    reg    [2:0]   sdrama_line_inc; // increment amount when proceeding to next tile line
    reg    [1:0]   inc_sdrama_r;
    reg            last_from_sdram; // reading last_r byte from SDRAM
-   reg            first_pixel; // reading first_r pixel to color converter (di will be evailable next cycle)
+   reg            first_pixel; // reading first_r pixel to color converter (di will be available next cycle)
    reg            tim2next;
    reg    [8:0]   y_in, c_in;
    reg    [7:0]   yaddrw, caddrw;
@@ -471,7 +477,7 @@ module  color_proc393 (
 
 wire limit_diff=1'b1;
 
- csconvert18    i_csconvert18 (
+ csconvert18a    i_csconvert18 (
                          .RST           (!en_converters[0]),
                          .CLK           (clk),
                          .mono          (ignore_color_r),
@@ -536,39 +542,39 @@ assign conv20_pre_first_out= conv18_pre_first_out;
 
 
 // currently only 8 bits are used in the memories
-    ramp_var_w_var_r #(
+    ram18p_var_w_var_r #(
         .REGISTERS    (1), // will need to delay output strobe(s) by 1
         .LOG2WIDTH_WR (3),
         .LOG2WIDTH_RD (3),
         .DUMMY        (0)
     ) i_y_buff (
         .rclk         (clk),                           // input
-        .raddr        ({2'b0,rpage[1:0],raddr[7:0]}),  // input[11:0] 
+        .raddr        ({1'b0,rpage[1:0],raddr[7:0]}),  // input[11:0] 
         .ren          (!raddr[8]),                     // input
         .regen        (!raddr8_d),                     // input
         .data_out     (y_out[8:0]),                    // output[8:0] 
         .wclk         (clk),                           // input
-        .waddr        ({2'b0,wpage[1:0],yaddrw[7:0]}), // input[11:0] 
+        .waddr        ({1'b0,wpage[1:0],yaddrw[7:0]}), // input[11:0] 
         .we           (ywe),                           // input
-        .web          (8'hf),                          // input[7:0] 
+        .web          (4'hf),                          // input[7:0] 
         .data_in      (y_in[8:0])                      // input[9:0] 
     );
 
-    ramp_var_w_var_r #(
+    ram18p_var_w_var_r #(
         .REGISTERS    (1), // will need to delay output strobe(s) by 1
         .LOG2WIDTH_WR (3),
         .LOG2WIDTH_RD (3),
         .DUMMY        (0)
     ) i_CrCb_buff (
         .rclk         (clk),                           // input
-        .raddr        ({2'b0,rpage[1:0],raddr[7:0]}),  // input[11:0] 
+        .raddr        ({1'b0,rpage[1:0],raddr[7:0]}),  // input[11:0] 
         .ren          (raddr[8]),                      // input
         .regen        (raddr8_d),                      // input
         .data_out     (c_out[8:0]),                    // output[8:0] 
         .wclk         (clk),                           // input
-        .waddr        ({2'b0,wpage[1:0],yaddrw[7:0]}), // input[11:0] 
+        .waddr        ({1'b0,wpage[1:0],yaddrw[7:0]}), // input[11:0] 
         .we           (ywe),                           // input
-        .web          (8'hf),                          // input[7:0] 
+        .web          (4'hf),                          // input[7:0] 
         .data_in      (y_in[8:0])                      // input[71:0] 
     );
 

util_modules/multipulse_cross_clock.v

+/*******************************************************************************
+ * Module: multipulse_cross_clock
+ * Date:2015-04-27  
+ * Author: andrey     
+ * Description: Generate a train of pulses through clock domains boundary
+ * Maximal duty cycle (with EXTRA_DLY=0 and Fdst << Fsrc) = 50%
+ * same frequencies - ~1/3 (with EXTRA_DLY=0) and 1/5 (with EXTRA_DLY=1)
+ * Lowering Fsrc reduces duty cycle proportianally as counter is in src_clk
+ * domain.
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * multipulse_cross_clock.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  multipulse_cross_clock.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  multipulse_cross_clock#(
+    parameter WIDTH=1,          // width of the pulse counter (assign MSB of input to 0 to
+                                // have more pending that possible input)
+    parameter EXTRA_DLY=0)(     // 0 or 1 - output duty cycle control
+    input              rst,
+    input              src_clk,
+    input              dst_clk,
+    input  [WIDTH-1:0] num_pulses, // single-cycle positive pulse
+    input              we,
+    output             out_pulse,
+    output             busy
+);
+    reg   [WIDTH-1:0] pend_cntr=0;
+    wire              busy_single;
+    wire              single_rq_w;
+    reg               single_rq_r=0;
+
+    assign busy = busy_single && (|pend_cntr);
+    assign single_rq_w = busy_single && (|pend_cntr);
+    
+    always @(posedge src_clk) begin
+        single_rq_r <= single_rq_w;
+        pend_cntr <= pend_cntr + (we ? num_pulses : {WIDTH{1'b0}}) + (single_rq_r ? {WIDTH{1'b1}}:{WIDTH{1'b0}});
+    end
+    
+    pulse_cross_clock #(
+        .EXTRA_DLY(EXTRA_DLY)
+    ) pulse_cross_clock_i (
+        .rst       (rst), // input
+        .src_clk   (src_clk), // input
+        .dst_clk   (dst_clk), // input
+        .in_pulse  (single_rq_w), // input
+        .out_pulse (out_pulse), // output
+        .busy      (busy_single) // output
+    );
+    
+endmodule
+

util_modules/pulse_cross_clock.v

@@ -3,6 +3,8 @@
  * Date:2015-04-27  
  * Author: andrey     
  * Description: Propagate a single pulse through clock domain boundary
+ * For same frequencies input pulses can have 1:3 duty cycle EXTRA_DLY=0
+ * and 1:5 for EXTRA_DLY=1 
  *
  * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
  * pulse_cross_clock.v is free software; you can redistribute it and/or modify
@@ -20,7 +22,9 @@
  *******************************************************************************/
 `timescale 1ns/1ps
 
-module  pulse_cross_clock(
+module  pulse_cross_clock#(
+    parameter EXTRA_DLY=0 // for 
+)(
     input  rst,
     input  src_clk,
     input  dst_clk,
@@ -28,13 +32,17 @@ module  pulse_cross_clock(
     output out_pulse,
     output busy
 );
-    reg       in_reg;
-    reg [2:0] out_reg;
+    localparam EXTRA_DLY_SAFE=EXTRA_DLY ? 1 : 0;
+    reg       in_reg = 0;
+    reg [2:0] out_reg = 0;
+    reg       busy_r = 0;
     assign out_pulse=out_reg[2];
-    assign busy=in_reg;
+    assign busy=busy_r; // in_reg;
     always @(posedge src_clk or posedge rst) begin
         if   (rst) in_reg <= 0;
-        else       in_reg <= in_pulse || (in_reg && !out_reg[1]);
+        else       in_reg <= in_pulse || (in_reg && !out_reg[EXTRA_DLY_SAFE]);
+        if   (rst) busy_r <= 0;
+        else       busy_r <= in_pulse || in_reg || (busy_r && out_reg[EXTRA_DLY_SAFE]);
     end
     always @(posedge dst_clk or posedge rst) begin
         if   (rst) out_reg <= 0;