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Commit 7274dadc authored by Andrey Filippov's avatar Andrey Filippov
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more debuggin/simulation of the membridge module

parent 8b79e3f7
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axi/membridge.v
View file @ 7274dadc
......@@ -355,7 +355,15 @@ module membridge#(
// DDR3 read - AFI write
//rdwr_en
reg [7:0] wresp_pending; // count not-yet-confirmed afi writes
reg [7:0] axi_arw_requested; // 64-bit words to be read/written over axi queued to AR/AW channels
reg [7:0] wresp_conf; // number of 64-bit words confirmed through axi b channel
wire [7:0] axi_wr_pending; // Number of words qued to AW but not yet confirmed through B-channel;
wire [7:0] axi_rd_pending;
reg [7:0] axi_rd_received;
assign axi_rd_pending= axi_arw_requested - axi_rd_received;
assign axi_wr_pending= axi_arw_requested - wresp_conf;
reg read_busy;
reg read_over;
reg afi_bvalid_r;
......@@ -380,16 +388,14 @@ module membridge#(
if (rst) read_started <= 0;
else if (!read_busy) read_started <= 0;
else if (page_ready) read_started <= 1; // first page is in the buffer - use it to mask page number comparison
afi_bvalid_r <=afi_bvalid;
//TODO: Make wresp_pending as difference of 2 counters, wa - on input (variable increment) wresp - on output
if (rst) wresp_conf <= 0;
else if (!read_busy) wresp_conf <= 0;
else if (afi_bvalid_r) wresp_conf <= wresp_conf +1;
if (rst) wresp_pending <= 0;
else if (!read_busy) wresp_pending <= 0;
else if ( afi_wvalid && !afi_bvalid_r) wresp_pending <= wresp_pending +1;
else if (!afi_wvalid && afi_bvalid_r) wresp_pending <= wresp_pending -1;
// TODO: Make a counter for addresses outside of afi_wacount
read_over <= left_zero && (wresp_pending == 0) && (afi_wacount==0);
read_over <= left_zero && (axi_wr_pending == 0) && read_started;
if (rst) read_page <= 0;
else if (reset_page_rd) read_page <= 0;
......@@ -414,11 +420,6 @@ module membridge#(
else if ((write_busy && frame_done) || (read_busy && read_over)) done <= 1;
else if (rdwr_start) done <= 0;
end
always @ (posedge hclk) begin
afi_bvalid_r <=afi_bvalid;
end
// handle interaction with the buffer, advance addresses, keep track of partial (last) pages in each line
......@@ -461,12 +462,6 @@ module membridge#(
assign afi_wvalid=bufrd_rd[2];
// write to ddr3 from afi
wire [7:0] axi_rd_pending;
reg [7:0] axi_rd_requested;
reg [7:0] axi_rd_received;
// wire axi_rd_data; // assign
assign axi_rd_pending= axi_rd_requested - axi_rd_received;
// wire some_read_ready;
reg afi_rd_safe_not_empty;
reg afi_ra_safe_not_full;
reg afi_safe_rd_pending;
......@@ -478,10 +473,7 @@ module membridge#(
assign bufwr_we_w= afi_rd_safe_not_empty && !write_pages_ready[2] && (!(&write_pages_ready[1:0]) || !is_last_in_page);
//afi_len_plus1
// handle buffer address, page
reg [1:0] write_page; // current number of buffer page
reg [2:0] write_pages_ready; // number of pages in the buffer
reg [1:0] write_page_r; // 1-cycle delayed page address
......@@ -494,9 +486,9 @@ module membridge#(
else if (wr_start) write_busy <= 1;
else if (frame_done) write_busy <= 0;
if (rst) axi_rd_requested <= 0;
else if (!write_busy) axi_rd_requested <= 0;
else if (advance_rel_addr) axi_rd_requested <= axi_rd_requested + afi_len_plus1;
if (rst) axi_arw_requested <= 0;
else if (!write_busy && !read_started) axi_arw_requested <= 0;
else if (advance_rel_addr) axi_arw_requested <= axi_arw_requested + afi_len_plus1;
if (rst) axi_rd_received <= 0;
else if (!write_busy) axi_rd_received <= 0;
......@@ -511,8 +503,9 @@ module membridge#(
if (rst) afi_ra_safe_not_full <= 0;
else afi_ra_safe_not_full <= rdwr_en && ( !afi_racount[2] && !(&afi_racount[1:0]));
if (rst) afi_safe_rd_pending <= 0;
else afi_safe_rd_pending <= rdwr_en && ( !axi_rd_pending[7] && !(&axi_rd_pending[6:4]));
if (rst) afi_safe_rd_pending <= 0;
else if (!write_busy) afi_safe_rd_pending <= 0;
else afi_safe_rd_pending <= rdwr_en && ( !axi_rd_pending[7] && !(&axi_rd_pending[6:4]));
// handle buffer address, page
if (rst) write_page <= 0;
......@@ -530,8 +523,6 @@ module membridge#(
write_page_r <= write_page;
buf_in_line64_r <= buf_in_line64[6:0];
end
//{write_page, buf_in_line64[6:0]}
//bufwr_we
cmd_deser #(
.ADDR (MEMBRIDGE_ADDR),
......
x393_testbench01.sav
View file @ 7274dadc
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Thu Apr 30 06:18:13 2015
[*] Thu Apr 30 18:06:37 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150429235314774.lxt"
[dumpfile_mtime] "Thu Apr 30 05:56:34 2015"
[dumpfile_size] 174025939
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150430115913649.lxt"
[dumpfile_mtime] "Thu Apr 30 18:02:38 2015"
[dumpfile_size] 174024137
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 44401000
[size] 1823 1173
[timestart] 37450000
[size] 1823 1180
[pos] 1919 0
*-18.982071 45883334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-21.063198 46660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.ddr3_i.
[treeopen] x393_testbench01.simul_axi_hp_wr_i.
......@@ -324,6 +324,7 @@ x393_testbench01.simul_axi_hp_wr_i.awready[0]
x393_testbench01.simul_axi_hp_wr_i.awvalid[0]
x393_testbench01.simul_axi_hp_wr_i.aw_nempty[0]
x393_testbench01.simul_axi_hp_wr_i.wvalid[0]
@29
x393_testbench01.x393_i.membridge_i.left_was_1[0]
@c00022
x393_testbench01.x393_i.membridge_i.src_wcntr[3:0]
......@@ -365,13 +366,14 @@ x393_testbench01.x393_i.membridge_i.read_busy[0]
x393_testbench01.x393_i.membridge_i.afi_wvalid[0]
x393_testbench01.simul_axi_hp_wr_i.fifo_wd_rd[0]
x393_testbench01.simul_axi_hp_wr_i.fifo_wd_rd_dly[0]
@29
x393_testbench01.simul_axi_hp_wr_i.wresp_re[0]
@28
x393_testbench01.x393_i.membridge_i.afi_bvalid[0]
x393_testbench01.x393_i.membridge_i.afi_bvalid_r[0]
@22
x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
x393_testbench01.x393_i.membridge_i.axi_arw_requested[7:0]
x393_testbench01.x393_i.membridge_i.wresp_conf[7:0]
x393_testbench01.x393_i.membridge_i.axi_wr_pending[7:0]
@200
-
@28
......@@ -463,7 +465,6 @@ x393_testbench01.x393_i.membridge_i.afi_wvalid[0]
x393_testbench01.x393_i.membridge_i.axi_addr64[28:0]
x393_testbench01.x393_i.membridge_i.axi_rd_pending[7:0]
x393_testbench01.x393_i.membridge_i.axi_rd_received[7:0]
x393_testbench01.x393_i.membridge_i.axi_rd_requested[7:0]
x393_testbench01.x393_i.membridge_i.buf_in_line64[13:0]
x393_testbench01.x393_i.membridge_i.buf_in_line64_r[6:0]
x393_testbench01.x393_i.membridge_i.buf_left64[28:0]
......
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