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Commit 988095ef authored by Andrey Filippov's avatar Andrey Filippov
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Fixed handling AXI write responce channel - both in work and simulation... 

Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
parent 0fda102e
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.project
View file @ 988095ef
......@@ -62,77 +62,77 @@
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</projectDescription>
axi/axibram_write.v
View file @ 988095ef
......@@ -135,9 +135,11 @@ module axibram_write #(
(wburst[0]? (write_address[ADDRESS_BITS-1:0]+1):(write_address[ADDRESS_BITS-1:0]));
assign bram_we_w= w_nempty_ready && write_in_progress;
assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));
// assign write_in_progress_w= aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0)));
assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0)));
// assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));
// assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0)));
// adding wlast_out to take precedence over (write_left[3:0]==4'b0), maybe wlast_out itself is sufficient
assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));
assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));
always @ (posedge aclk or posedge rst) begin
if (rst) wburst[1:0] <= 0;
......@@ -249,7 +251,7 @@ fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(bram_we_w),
.we(bram_we_w &&((write_left[3:0]==4'b0) || wlast_out)), // added ((write_left[3:0]==4'b0) || wlast_out) - only last wrtite -> bresp
// .re(bready && bvalid),
.re(bresp_re), // not allowing RE next cycle after bvalid
.data_in({wid_out[11:0],bresp_in[1:0]}),
......
axi/membridge.v
View file @ 988095ef
......@@ -355,6 +355,7 @@ module membridge#(
wire rw_in_progress;
reg busy;
reg done;
reg pre_done;
assign rw_in_progress = read_started || write_busy;
......@@ -392,14 +393,16 @@ module membridge#(
// DDR3 read - AFI write
//rdwr_en
reg [7:0] axi_arw_requested; // 64-bit words to be read/written over axi queued to AR/AW channels
reg [7:0] axi_arw_requested; // 64-bit words to be read/written over axi queued to AR/AW channels
reg [7:0] axi_bursts_requested; // number of bursts requested
reg [7:0] wresp_conf; // number of 64-bit words confirmed through axi b channel
wire [7:0] axi_wr_pending; // Number of words qued to AW but not yet confirmed through B-channel;
wire [7:0] axi_rd_pending;
reg [7:0] axi_rd_received;
assign axi_rd_pending= axi_arw_requested - axi_rd_received;
assign axi_wr_pending= axi_arw_requested - wresp_conf;
// assign axi_wr_pending= axi_arw_requested - wresp_conf;
assign axi_wr_pending= axi_bursts_requested - wresp_conf;
reg read_busy;
reg read_over;
......@@ -480,10 +483,13 @@ module membridge#(
if (rst) busy <= 0;
else busy <= read_busy || write_busy;
if (rst) done <= 0;
else if (!rdwr_en) done <= 0; // disabling when idle will reset done
else if ((write_busy && frame_done) || (read_busy && read_over)) done <= 1;
else if (rdwr_start) done <= 0;
if (rst) pre_done <= 0; // delay done to turn on same time busy is off
else pre_done <= (write_busy && frame_done) || (read_busy && read_over);
if (rst) done <= 0;
else if (!rdwr_en) done <= 0; // disabling when idle will reset done
else if (pre_done) done <= 1;
else if (rdwr_start) done <= 0;
end
......@@ -573,6 +579,10 @@ module membridge#(
if (rst) axi_arw_requested <= 0;
else if (!write_busy && !read_started) axi_arw_requested <= 0;
else if (advance_rel_addr) axi_arw_requested <= axi_arw_requested + afi_len_plus1;
if (rst) axi_bursts_requested <= 0;
else if (!write_busy && !read_started) axi_bursts_requested <= 0;
else if (advance_rel_addr) axi_bursts_requested <= axi_bursts_requested + 1;
if (rst) axi_rd_received <= 0;
else if (!write_busy) axi_rd_received <= 0;
......@@ -630,7 +640,7 @@ module membridge#(
`ifdef MEMBRIDGE_DEBUG_READ
.PAYLOAD_BITS (18) // 2) // With debug
`else
.PAYLOAD_BITS (2)
.PAYLOAD_BITS (18) //2)
`endif
) status_generate_i (
.rst (rst), // input
......@@ -640,7 +650,8 @@ module membridge#(
`ifdef MEMBRIDGE_DEBUG_READ
.status ({debug_aw_allowed, debug_w_allowed, done, busy}), // input[25:0]
`else
.status ({done,busy}), // input[25:0]
// .status ({done,busy}), // input[25:0]
.status ({axi_arw_requested, wresp_conf, done, busy}), // input[25:0]
`endif
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
......
includes/x393_tasks_mcntrl_buffers.vh
View file @ 988095ef
......@@ -69,7 +69,7 @@ task write_block_incremtal;
i, // id
start_value+i+j,
4'hf, // wstrb
(1 == 15) ? 1 : 0 // last
(j == 15) ? 1 : 0 // last
);
$display(" Write block incremental (addr:data): 0x%08x:0x%x @%t", (i + j), start_value+i+j, $time);
end
......@@ -122,7 +122,7 @@ task write_block_buf;
i, // id
(i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24),
4'hf, // wstrb
(1 == 15) ? 1 : 0 // last
(j == 15) ? 1 : 0 // last
);
$display(" Write block data (addr:data): 0x%08x:0x%x @%t", (i + j),
(i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24), $time);
......
py393/x393_mcntrl_membridge.py
View file @ 988095ef
......@@ -298,7 +298,7 @@ class X393McntrlMembridge(object):
1, # enable
0) # chn_reset
# self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64);
# self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR, frame_start_addr) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, window_full_width);
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | window_width) # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
......@@ -320,10 +320,10 @@ class X393McntrlMembridge(object):
if wait_ready:
self.x393_axi_tasks.wait_status_condition ( # may also be read directly from the same bit of mctrl_linear_rw (address=5) status
vrlg.MEMBRIDGE_STATUS_REG, # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
vrlg.MCNTRL_SCANLINE_CHN1_ADDR +vrlg.MEMBRIDGE_STATUS_CNTRL, # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
vrlg.MEMBRIDGE_ADDR +vrlg.MEMBRIDGE_STATUS_CNTRL, # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
vrlg.DEFAULT_STATUS_MODE,
2 << vrlg.STATUS_2LSB_SHFT, # bit 24 - busy, bit 25 - frame done
2 << vrlg.STATUS_2LSB_SHFT, # mask for the 4-bit page number
0, # equal to
0); # no need to synchronize sequence number
1); # synchronize sequence number
simulation_modules/simul_axi_hp_wr.v
View file @ 988095ef
......@@ -121,6 +121,7 @@ Alex
wire [3:0] awlen_out;
wire [31:0] awaddr_out;
wire [5:0] wid_out;
wire wlast_out;
wire [7:0] wstrb_out;
wire [63:0] wdata_out;
......@@ -209,7 +210,7 @@ Alex
assign enough_data=|num_full_data || ((WrCmdReleaseMode==2'b01) && (wcount > {4'b0,WrDataThreshold}));
assign fifo_wd_rd= write_in_progress && w_nempty && sim_wr_ready;
assign sim_wr_valid= write_in_progress && w_nempty; // for continuing writes
assign last_confirmed_write = (write_left==0) && fifo_wd_rd;
assign last_confirmed_write = (write_left==0) && fifo_wd_rd && wlast_out; // wlast_out should take precedence over write_left?
assign start_write_burst_w=
aw_nempty && enough_data &&
(! write_in_progress || last_confirmed_write);
......@@ -296,15 +297,15 @@ fifo_same_clock_fill #( .DATA_WIDTH(51),.DATA_DEPTH(5)) // read - 4, write - 3
.rcount (), //waddr_rcount), // output[3:0] reg
.num_in_fifo(wacount) // output[3:0]
);
fifo_same_clock_fill #( .DATA_WIDTH(78),.DATA_DEPTH(7))
fifo_same_clock_fill #( .DATA_WIDTH(79),.DATA_DEPTH(7))
wdata_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(wvalid && wready),
.re(fifo_wd_rd), //start_write_burst_w), // wrong
.data_in({wid[5:0], wstrb[7:0], wdata[63:0]}),
.data_out({wid_out[5:0], wstrb_out[7:0], wdata_out[63:0]}),
.data_in({wlast, wid[5:0], wstrb[7:0], wdata[63:0]}),
.data_out({wlast_out,wid_out[5:0], wstrb_out[7:0], wdata_out[63:0]}),
.nempty(w_nempty),
.half_full(), //w_half_full),
.under (), //wdata_under), // output reg
......@@ -320,7 +321,7 @@ fifo_same_clock_fill #( .DATA_WIDTH(78),.DATA_DEPTH(7))
wire fifo_wd_rd_dly;
wire [5:0] bid_in;
// input [ 3:0] sim_bresp_latency, // latency in writeing data outside of the module
// input [ 3:0] sim_bresp_latency, // latency in writing data outside of the module
dly_16 #(
.WIDTH(1)
......@@ -328,18 +329,18 @@ fifo_same_clock_fill #( .DATA_WIDTH(78),.DATA_DEPTH(7))
.clk(aclk), // input
.rst(rst), // input
.dly(sim_bresp_latency[3:0]), // input[3:0]
.din(fifo_wd_rd), // input[0:0]
.din(last_confirmed_write), //fifo_wd_rd), // input[0:0]
.dout(fifo_wd_rd_dly) // output[0:0]
);
// first FIFO for bresp - latency outside of the module
// wresp per burst, not per item !
fifo_same_clock_fill #( .DATA_WIDTH(8),.DATA_DEPTH(5))
wresp_ext_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(fifo_wd_rd),
.we(last_confirmed_write), // fifo_wd_rd),
.re(fifo_wd_rd_dly), // not allowing RE next cycle after bvalid
.data_in({wid_out[5:0],bresp_value[1:0]}),
.data_out({bid_in[5:0],bresp_in[1:0]}),
......
util_modules/status_generate.v
View file @ 988095ef
......@@ -32,7 +32,7 @@ module status_generate #(
input clk,
input we, // command strobe
input [7:0] wd, // command data - 6 bits of sequence and 2 mode bits
input [PAYLOAD_BITS-1:0] status, // parallel status data to be sent out
input [PAYLOAD_BITS-1:0] status, // parallel status data to be sent out, may come from different clock domain
output [7:0] ad, // byte-wide address/data
output rq, // request to send downstream (last byte with rq==0)
input start // acknowledge of address (first byte) from downsteram
......@@ -48,6 +48,7 @@ module status_generate #(
wire [1:0] mode_w;
reg [1:0] mode;
reg [5:0] seq;
reg [PAYLOAD_BITS-1:0] status_r0; // registered status as it may come from the different clock domain
reg [PAYLOAD_BITS-1:0] status_r; // "frozen" status to be sent;
reg status_changed_r; // not reset if status changes back to original
reg cmd_pend;
......@@ -58,7 +59,7 @@ module status_generate #(
reg [NUM_BYTES-2:0] rq_r;
assign aligned_status=(ALIGNED_STATUS_WIDTH==PAYLOAD_BITS)?status:{{(ALIGNED_STATUS_WIDTH-PAYLOAD_BITS){1'b0}},status};
assign aligned_status=(ALIGNED_STATUS_WIDTH==PAYLOAD_BITS)?status_r0:{{(ALIGNED_STATUS_WIDTH-PAYLOAD_BITS){1'b0}},status_r0};
assign ad=data[7:0];
assign need_to_send=cmd_pend || (mode[1] && status_changed_r); // latency
assign rq=rq_r[0]; // NUM_BYTES-2];
......@@ -69,7 +70,7 @@ module status_generate #(
if (rst) status_changed_r <= 0;
// else status_changed_r <= (status_changed_r && !start) || (status_r != status);
else if (start) status_changed_r <= 0;
else status_changed_r <= status_changed_r || (status_r != status);
else status_changed_r <= status_changed_r || (status_r != status_r0);
if (rst) mode <= 0;
else if (we) mode <= mode_w; // wd[7:6];
......@@ -82,13 +83,16 @@ module status_generate #(
else if (we && (mode_w!=0)) cmd_pend <= 1;
else if (start) cmd_pend <= 0;
if (rst) status_r0 <= 0;
else status_r0 <= status;
if (rst) status_r<=0;
else if (start) status_r<=status;
else if (start) status_r<=status_r0;
if (rst) data <= STATUS_REG_ADDR;
else if (start) data <= (NUM_BYTES>2)?
{aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,status[1:0]}:
{seq,status[1:0]};
{aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,status_r0[1:0]}:
{seq,status_r0[1:0]};
else if ((NUM_BYTES>2) && snd_rest) data <= data >> 8; // never happens with 2-byte packet
else data <= STATUS_REG_ADDR;
......
x393_testbench01.sav
View file @ 988095ef
This diff is collapsed.
x393_testbench01.tf
View file @ 988095ef
......@@ -31,7 +31,7 @@
//`define TEST_READ_PATTERN 1
//`define TEST_WRITE_BLOCK 1
//`define TEST_READ_BLOCK 1
`define TEST_SCANLINE_WRITE
//`define TEST_SCANLINE_WRITE
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_SCANLINE_READ
`define TEST_READ_SHOW 1
......@@ -42,7 +42,7 @@
//`define TEST_TILED_WRITE32 1
//`define TEST_TILED_READ32 1
//`define TEST_AFI_WRITE 1
`define TEST_AFI_WRITE 1
`define TEST_AFI_READ 1
module x393_testbench01 #(
......@@ -571,6 +571,21 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
AFI_LO_ADDR64, // input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words
0); // input continue; // 0 start from start64, 1 - continue from where it was
$display("===================== #2 TEST_%s =========================",TEST_TITLE);
test_afi_rw (
0, // write_ddr3;
SCANLINE_EXTRA_PAGES,// extra_pages;
FRAME_START_ADDRESS, // input [21:0] frame_start_addr;
FRAME_FULL_WIDTH, // input [15:0] window_full_width; // 13 bit - in 8*16=128 bit bursts
WINDOW_WIDTH, // input [15:0] window_width; // 13 bit - in 8*16=128 bit bursts
WINDOW_HEIGHT, // input [15:0] window_height; // 16 bit (only 14 are used here)
WINDOW_X0, // input [15:0] window_left;
WINDOW_Y0, // input [15:0] window_top;
0, // input [28:0] start64; // relative start adderss of the transfer (set to 0 when writing lo_addr64)
AFI_LO_ADDR64, // input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words
0); // input continue; // 0 start from start64, 1 - continue from where it was
`endif
TEST_TITLE = "ALL_DONE";
......@@ -580,6 +595,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
end
// protect from never end
initial begin
// #30000;
// #200000;
#60000;
$display("finish testbench 2");
......@@ -1468,12 +1484,12 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
// just wait done
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
MEMBRIDGE_STATUS_REG, // MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
MCNTRL_SCANLINE_CHN1_ADDR + MEMBRIDGE_STATUS_CNTRL, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
MEMBRIDGE_ADDR + MEMBRIDGE_STATUS_CNTRL, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
0, // equal to
0); // no need to synchronize sequence number
1); // do synchronize sequence number
end
endtask
......
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