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Commit a445ef42 authored by Andrey Filippov's avatar Andrey Filippov
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added another channel for testing - tile write

parent 31a6b971
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.editor_defines.vh
View file @ a445ef42
......@@ -2,7 +2,7 @@
// TODO: Fix VDT - without IVERILOG defined, closure does not include modules needed for Icarus
`define IVERILOG 1
`define USE_CMD_ENCOD_TILED_32_RD 1
// It can be used to check different `ifdef branches
//`define XIL_TIMING //Simprim
`define den4096Mb 1
......@@ -33,8 +33,10 @@
`define def_read_mem_chn4
`define def_tiled_chn4
// chn 5 is disabled
`undef def_enable_mem_chn5
// chn 5 is enabled
`define def_enable_mem_chn5
`undef def_read_mem_chn5
`define def_tiled_chn5
// chn 6 is disabled
`undef def_enable_mem_chn6
......
axi/axibram.v deleted 100644 → 0
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axi/axibram_write.v
View file @ a445ef42
......@@ -19,7 +19,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`define DEBUG_FIFO 1
//`define DEBUG_FIFO 1
module axibram_write #(
parameter ADDRESS_BITS = 10 // number of memory address bits
)(
......@@ -197,6 +197,7 @@ fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
waddr_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),
......@@ -216,6 +217,7 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
wdata_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(wvalid && wready),
.re(bram_we_w), //start_write_burst_w), // wrong
.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),
......@@ -244,6 +246,7 @@ fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))
wresp_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(bram_we_w),
// .re(bready && bvalid),
.re(bresp_re), // not allowing RE next cycle after bvalid
......
ddrc_test01.v deleted 100644 → 0
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ddrc_test01_testbench.tf deleted 100644 → 0
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includes/x393_localparams.vh
View file @ a445ef42
......@@ -68,7 +68,7 @@
localparam DQSTRI_LAST= 4'hc; // DQS tri-state control word, first after disabling output
localparam DQTRI_FIRST= 4'h7; // DQ tri-state control word, first when enabling output
localparam DQTRI_LAST= 4'he; // DQ tri-state control word, first after disabling output
localparam WBUF_DLY_DFLT= 4'h6; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
localparam WBUF_DLY_DFLT= DFLT_WBUF_DELAY; //4'h8; // 4'h6; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
localparam WBUF_DLY_WLV= 4'h7; // write leveling mode: extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
// localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
......
includes/x393_parameters.vh
View file @ a445ef42
......@@ -27,6 +27,7 @@
parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
......@@ -99,7 +100,7 @@
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_WBUF_DELAY= 4'h8, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
......@@ -203,6 +204,7 @@
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_CHN5_ADDR= 'h150,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......@@ -232,6 +234,10 @@
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_CHN5_MODE= 'ha, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN5_STATUS_CNTRL= 'hb, // control status reporting for channel 5
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f // status/readback register for channel 4
\ No newline at end of file
includes/x393_tasks_mcntrl_buffers.vh
View file @ a445ef42
......@@ -86,6 +86,7 @@ task write_block_buf_chn; // S uppressThisWarning VEditor : may be unused
case (chn)
1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
5: start_addr=MCONTR_BUF5_WR_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for write buffer = %d @%t", chn, $time);
start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
......
includes/x393_tasks_pio_sequences.vh
View file @ a445ef42
......@@ -47,11 +47,11 @@ task set_read_block;
// first read
// read
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 2, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0);
data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining reads
for (i=1;i<64;i=i+1) begin
......@@ -62,11 +62,11 @@ task set_read_block;
end
// nop - all 3 below are the same? - just repeat?
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
......@@ -188,11 +188,11 @@ task set_read_pattern;
// first read
// read
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( 0, 0, 2, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0);
data <= func_encode_cmd( 0, 0, 2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop (combine with previous?)
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining reads
for (i = 1; i < nrep; i = i + 1) begin
......@@ -206,11 +206,11 @@ task set_read_pattern;
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop, no write buffer - next page
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
......
includes/x393_tasks_status.vh
View file @ a445ef42
......@@ -66,6 +66,7 @@ endtask
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN5_ADDR);
end
endtask
......@@ -88,9 +89,11 @@ endtask
program_status (MCNTRL_SCANLINE_CHN2_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
program_status (MCNTRL_TILED_CHN4_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TILED_CHN5_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN5_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f,
end
endtask
......
memctrl/cmd_encod_linear_rd.v
View file @ a445ef42
......@@ -125,9 +125,9 @@ module cmd_encod_linear_rd #(
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) | (1 << ENC_DCI);
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
......
memctrl/cmd_encod_linear_wr.v
View file @ a445ef42
......@@ -208,74 +208,5 @@ module cmd_encod_linear_wr #(
// move to include?
`include "includes/x393_mcontr_encode_cmd.vh"
/*
function [31:0] func_encode_skip;
input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
input done; // end of sequence
input [2:0] bank; // bank (here OK to be any)
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
bank[2:0], // bank (here OK to be any)
3'b0, // RAS/CAS/WE, positive logic
odt_en, // enable ODT
cke, // disable CKE
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // connect to external buffer (but only if not paused)
1'b0, // nop
buf_rst);
end
endfunction
function [31:0] func_encode_cmd;
input [14:0] addr; // 15-bit row/column adderss
input [2:0] bank; // bank (here OK to be any)
input [2:0] rcw; // RAS/CAS/WE, positive logic
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input nop; // add NOP after the current command, keep other data
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column adderss
bank [2:0], // bank
rcw[2:0], // RAS/CAS/WE
odt_en, // enable ODT
cke, // may be optimized (removed from here)?
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
nop, // add NOP after the current command, keep other data
buf_rst // Reserved for future use
};
end
endfunction
*/
endmodule
memctrl/cmd_encod_tiled_32_rd.v
View file @ a445ef42
......@@ -2,7 +2,7 @@
* Module: cmd_encod_tiled_32_rd
* Date:2015-02-218
* Author: andrey
* Description: Command sequencer generator for reading a tiled aread
* Description: Command sequencer generator for reading a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 32 bytes wide,
* then proceding to the next column (if >1).
......
memctrl/cmd_encod_tiled_rd.v
View file @ a445ef42
This diff is collapsed.
memctrl/mcntrl393.v
View file @ a445ef42
This diff is collapsed.
memctrl/mcntrl393_test01.v
View file @ a445ef42
This diff is collapsed.
memctrl/mcntrl_tiled_rw.v
View file @ a445ef42
......@@ -173,7 +173,7 @@ module mcntrl_tiled_rw#(
// otherwise (smaller widths) round up to the nearest power of 2
reg [FRAME_WIDTH_BITS:0] window_width; // (programmed) 0- max
reg [FRAME_HEIGHT_BITS:0] window_height; // (programmed) 0- max
reg [FRAME_HEIGHT_BITS:0] window_m_tile_height; // (window height-tile height
// reg [FRAME_HEIGHT_BITS:0] window_m_tile_height; // (window height-tile height
reg [FRAME_WIDTH_BITS-1:0] window_x0; // (programmed) window left
reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top
reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start
......@@ -323,7 +323,7 @@ module mcntrl_tiled_rw#(
last_in_row <= last_in_row_w;
end
window_m_tile_height <= window_height - tile_rows;
// window_m_tile_height <= window_height - tile_rows;
end
// now have row start address, bank and row_left ;
......
memctrl/memctrl16.v
View file @ a445ef42
......@@ -94,7 +94,7 @@ module memctrl16 #(
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_WBUF_DELAY= 4'h8, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
......
memctrl/phy/ddrc_sequencer.v
View file @ a445ef42
......@@ -413,6 +413,7 @@ module ddrc_sequencer #(
.buf_rdata (buf_rdata[63:0]), // input[63:0]
.buf_wr (buf_wr_ndly), // output
.buf_rd (buf_rd), // output
.buf_rst (), // output
.cmda_en (cmda_en), // input
.ddr_rst (ddr_rst), // input
.dci_rst (dci_rst), // input
......
memctrl/phy/mcontr_sequencer.v
View file @ a445ef42
......@@ -64,7 +64,7 @@ module mcontr_sequencer #(
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc,// DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_WBUF_DELAY= 4'h8, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter PHASE_WIDTH = 8,
......
util_modules/mcont_from_chnbuf_reg.v
View file @ a445ef42
......@@ -48,7 +48,8 @@ module mcont_from_chnbuf_reg #(
else buf_run <= (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh && ext_buf_rrun;
if (rst) latency_reg<= 0;
else latency_reg <= buf_rd_chn | (latency_reg << 1);
// else latency_reg <= buf_rd_chn | (latency_reg << 1);
else latency_reg <= {latency_reg[CHN_LATENCY-1:0], buf_rd_chn};
// if (rst) buf_done <= 0;
// else buf_done <= buf_chn_sel && seq_done;
......
x393.v
View file @ a445ef42
......@@ -20,7 +20,7 @@
*******************************************************************************/
`timescale 1ns/1ps
`define use200Mhz 1
`define DEBUG_FIFO 1
//`define DEBUG_FIFO 1
`include ".editor_defines.vh"
module x393 #(
parameter MCONTR_WR_MASK = 'h1c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
......@@ -32,6 +32,7 @@ module x393 #(
parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
......@@ -104,7 +105,7 @@ module x393 #(
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_WBUF_DELAY= 4'h8, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
......@@ -208,6 +209,7 @@ module x393 #(
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_CHN5_ADDR= 'h140,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......@@ -237,9 +239,12 @@ module x393 #(
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_CHN5_MODE= 'ha, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN5_STATUS_CNTRL= 'hb, // control status reporting for channel 5
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f // status/readback register for channel 4
)(
// DDR3 interface
output SDRST, // DDR3 reset (active low)
......@@ -472,6 +477,12 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
wire frame_done_chn4; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn4; // output[15:0]
wire suspend_chn4; // input
wire frame_start_chn5; // input
wire next_page_chn5; // input
wire page_ready_chn5; // output
wire frame_done_chn5; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn5; // output[15:0]
wire suspend_chn5; // input
assign cmd_mcontr_ad= cmd_root_ad;
assign cmd_mcontr_stb=cmd_root_stb;
......@@ -500,9 +511,12 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCNTRL_TEST01_CHN3_STATUS_CNTRL (MCNTRL_TEST01_CHN3_STATUS_CNTRL),
.MCNTRL_TEST01_CHN4_MODE (MCNTRL_TEST01_CHN4_MODE),
.MCNTRL_TEST01_CHN4_STATUS_CNTRL (MCNTRL_TEST01_CHN4_STATUS_CNTRL),
.MCNTRL_TEST01_CHN5_MODE (MCNTRL_TEST01_CHN5_MODE),
.MCNTRL_TEST01_CHN5_STATUS_CNTRL (MCNTRL_TEST01_CHN5_STATUS_CNTRL),
.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN5_ADDR (MCNTRL_TEST01_STATUS_REG_CHN5_ADDR)
) mcntrl393_test01_i (
.rst(axi_rst), // input
.mclk (mclk), // input
......@@ -528,7 +542,13 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.page_ready_chn4 (page_ready_chn4), // input
.frame_done_chn4 (frame_done_chn4), // input
.line_unfinished_chn4 (line_unfinished_chn4), // input[15:0]
.suspend_chn4 (suspend_chn4) // output
.suspend_chn4 (suspend_chn4), // output
.frame_start_chn5 (frame_start_chn5), // output
.next_page_chn5 (next_page_chn5), // output
.page_ready_chn5 (page_ready_chn5), // input
.frame_done_chn5 (frame_done_chn5), // input
.line_unfinished_chn5 (line_unfinished_chn5), // input[15:0]
.suspend_chn5 (suspend_chn5) // output
);
// Interface to channels to read/write memory (including 4 page BRAM buffers)
......@@ -626,6 +646,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCONTR_BUF2_RD_ADDR (MCONTR_BUF2_RD_ADDR),
.MCONTR_BUF3_WR_ADDR (MCONTR_BUF3_WR_ADDR),
.MCONTR_BUF4_RD_ADDR (MCONTR_BUF4_RD_ADDR),
.MCONTR_BUF5_WR_ADDR (MCONTR_BUF5_WR_ADDR),
.DLY_LD (DLY_LD),
.DLY_LD_MASK (DLY_LD_MASK),
.MCONTR_PHY_0BIT_ADDR (MCONTR_PHY_0BIT_ADDR),
......@@ -721,6 +742,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_CHN4_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_CHN5_ADDR (MCNTRL_TILED_CHN5_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
......@@ -777,6 +799,12 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.frame_done_chn4 (frame_done_chn4), // output
.line_unfinished_chn4 (line_unfinished_chn4), // output[15:0]
.suspend_chn4 (suspend_chn4), // input
.frame_start_chn5 (frame_start_chn5), // input
.next_page_chn5 (next_page_chn5), // input
.page_ready_chn5 (page_ready_chn5), // output
.frame_done_chn5 (frame_done_chn5), // output
.line_unfinished_chn5 (line_unfinished_chn5), // output[15:0]
.suspend_chn5 (suspend_chn5), // input
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
......@@ -800,7 +828,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
//MEMCLK
wire [63:0] gpio_in;
assign gpio_in={
assign gpio_in= {52'h0,tmp_debug};
/*
{
frst[3]?{
16'b0,
1'b1, // 1
......@@ -839,6 +869,7 @@ frst[3]?{
// dly_ready // 1 0
}:{
waddr_wcount[3:0],
waddr_rcount[3:0],
waddr_num_in_fifo[3:0],
......@@ -853,6 +884,7 @@ frst[3]?{
wleft[3:0],
wlength[3:0],
wlen_in_dbg[3:0]
},
......@@ -879,6 +911,7 @@ frst[3]?{
fifo_rst, // fclk[0], // 0/1
axi_rst_pre //axi_rst // 0
};
*/
axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS)
) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
......
x393_testbench01.sav
View file @ a445ef42
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x393_testbench01.tf
View file @ a445ef42
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