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Commit d2699ad8 authored by Andrey Filippov's avatar Andrey Filippov
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Working on cmprs_afi_mux.v, extracted 2 sub-modules: cmprs_afi_mux_ptr.v and... 

Working on cmprs_afi_mux.v, extracted 2 sub-modules: cmprs_afi_mux_ptr.v and cmprs_afi_mux_ptr_wresp.v
parent 3e682017
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Showing with 333 additions and 45 deletions
axi/axibram_write.v
View file @ d2699ad8
......@@ -162,7 +162,7 @@ module axibram_write #(
if (rst) dev_ready_r <= 1'b0;
else dev_ready_r <= dev_ready;
end
// **** Write responce channel ****
// **** Write response channel ****
wire [ 1:0] bresp_in;
assign bresp_in=2'b0;
......
axi/cmprs_afi_mux.v
View file @ d2699ad8
......@@ -100,7 +100,13 @@ module cmprs_afi_mux#(
output afi_wrissuecap1en
);
reg en; // enable mux
reg en_d;
reg [3:0] en_chn; // per-channel enable
wire [31:0] cmd_data;
wire [ 3:0] cmd_a;
wire cmd_we_sa_len;
// reg [2:0] cur_chn; // 'b0xx - none, 'b1** - ** - channel number (should match fifo_ren*)
reg [1:0] cur_chn; // 'b0xx - none, 'b1** - ** - channel number (should match fifo_ren*)
reg [7:0] left_to_eof[0:3]; // number of chunks left to end of frame
......@@ -123,50 +129,50 @@ module cmprs_afi_mux#(
wire need_to_bother = |counts_corr2[8:2];
reg ready_to_start; // TBD: either idle or soon will finish the previous burst (include AFI FIFO level here too?)
wire [3:0] last_chunk_w;
reg [2:0] busy; // TODO: adjust number of bits. During continuous run busy is deasseted for 1 clock cycle
reg [3:0] busy; // TODO: adjust number of bits. During continuous run busy is deasseted for 1 clock cycle
wire done_burst_w; // de-asset busy
wire pre_busy_w;
reg last_burst_in_frame;
// reg [1:0] wlen32; // 2 high bits of burst len (LSB are always 2'b11)
reg [3:0] wleft; // number of 64-bit words left to be sent - also used as awlen (valid @ awvalid)
reg [2:0] chunk_inc; // how much to increment chunk pointer (1..4)
wire [ 3:0] reset_pointers; // per-channel - after chunk_start_hclk or chunk_len_hclk were written or explicit fifo_rst*
reg [26:0] chunk_addr_chn[0:3]; //system memory address in "chunks" (32-bytes)
reg [26:0] chunk_addr;
reg awvalid;
wire ptr_resetting; // pointers are being reset in cmprs_afi_mux_ptr module
wire [26:0] chunk_addr;
reg [1:0] awvalid;
reg wvalid;
reg wlast;
reg [3:0] eof_written;
reg [63:0] wdata; // registered data from one of the 4 buffers
wire wdata_en; // register enable for wdata
wire [1:0] wdata_sel; // source select for wdata
reg [3:0] fifo_ren;
wire [26:0] chunk_ptr_rd;
wire [ 3:0] chunk_ptr_ra;
// use last_chunk_w to apply a special id to waddr and wdata and watch for it during readout
// compose ID of channel number, frame bumber LSBs and last/not last chunk
// assign last_chunk_w[3:0] = {~(|left_to_eof[3]),~(|left_to_eof[2]),~(|left_to_eof[1]),~(|left_to_eof[0])};
assign last_chunk_w[3:0] = {(left_to_eof[3]==1)?1'b1:1'b0,
(left_to_eof[2]==1)?1'b1:1'b0,
(left_to_eof[1]==1)?1'b1:1'b0,
(left_to_eof[0]==1)?1'b1:1'b0};
assign pre_busy_w = !busy && ready_to_start && need_to_bother;
assign done_burst_w = busy && !(|wleft[3:1]); // when wleft[3:0] == 0, busy is 0
assign eof_written0 = eof_written[0];
assign eof_written1 = eof_written[1];
assign eof_written2 = eof_written[2];
assign eof_written3 = eof_written[3];
assign fifo_ren0 = fifo_ren[0];
assign fifo_ren1 = fifo_ren[1];
assign fifo_ren2 = fifo_ren[2];
assign fifo_ren3 = fifo_ren[3];
assign pre_busy_w = !busy[0] && ready_to_start && need_to_bother && !ptr_resetting;
assign done_burst_w = busy[0] && !(|wleft[3:1]); // when wleft[3:0] == 0, busy is 0
assign {fifo_rst3, fifo_rst2, fifo_rst1, fifo_rst0} = reset_pointers;
assign {fifo_ren3, fifo_ren2, fifo_ren1, fifo_ren0} = fifo_ren;
assign afi_awaddr = {chunk_addr,5'b0};
assign afi_awid = {3'b0,last_burst_in_frame,cur_chn};
assign afi_awvalid = awvalid;
assign afi_awlen = wleft;
// assign afi_wid = {3'b0,last_burst_in_frame,cur_chn};
// assign afi_wvalid = wvalid;
// assign afi_wlast = wlast;
assign afi_awid = {1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
assign afi_awvalid = awvalid[1];
assign afi_awlen = {wleft[3:2],2'b11};
assign afi_wdata = wdata;
assign afi_bready = 1'b1; // always ready
......@@ -181,8 +187,9 @@ module cmprs_afi_mux#(
assign afi_wrissuecap1en = 1'b0;
always @ (posedge hclk) begin
en_d <= en;
ready_to_start <= en && // ready to strta a burst
!afi_wacount[5] && !(&afi_wacount[4:1]) && // >=2 free
!afi_wcount[7] && !(&afi_wcount[6:3]); // >=8 free (4 would be enough too)
......@@ -254,18 +261,18 @@ module cmprs_afi_mux#(
//ready_to_start need_to_bother
//done_burst
if (!en) busy <= 0;
else if (pre_busy_w) busy <= {busy[1:0],1'b1};
else if (done_burst_w) busy <= {busy[1:0],1'b0};
else if (pre_busy_w) busy <= {busy[2:0],1'b1};
else if (done_burst_w) busy <= 0; // {busy[2:0],1'b0};
if (!en) wleft <= 0;
else if (pre_busy_w) wleft <= {(|counts_corr2[7:2])? 2'b11 : left_to_eof[winner2][1:0], 2'b11};
else if (wleft != 0) wleft <= wleft - 1;
if (!en) wvalid <= 0;
else if (pre_busy_w) wvalid <= 1;
else if (wlast) wvalid <= 0; // should be after pre_busy_w as both can happen simultaneously
//fifo_ren
if (!en) fifo_ren <= 0;
else if (pre_busy_w) fifo_ren <= {(winner2 == 3) ?1'b1:1'b0,
(winner2 == 2) ?1'b1:1'b0,
......@@ -273,27 +280,21 @@ module cmprs_afi_mux#(
(winner2 == 0) ?1'b1:1'b0};
else if (wlast) fifo_ren <= 0;
awvalid <= pre_busy_w; // no need to wait for afi_awready, will use fifo levels to enable pre_busy_w
awvalid <= {awvalid[0],pre_busy_w}; // no need to wait for afi_awready, will use fifo levels to enable pre_busy_w
if (pre_busy_w) begin
cur_chn <= winner2;
last_burst_in_frame <= last_chunk_w[winner2];
wleft <= {(|counts_corr2[7:2])? 2'b11 : left_to_eof[winner2][1:0], 2'b11};
chunk_addr <= chunk_addr_chn[winner2];
end
wlast <= done_burst_w; // when wleft==4'h1
// wdata register mux
if (wdata_en) wdata <= wdata_sel[1]?(wdata_sel[1]?fifo_rdata3:fifo_rdata2):(wdata_sel[1]?fifo_rdata1:fifo_rdata0);
// Watch write responce channel, detect EOF IDs, generate eof_written* output signals
eof_written[0] <= afi_bvalid && (afi_bid[2:0]== 3'h4);
eof_written[1] <= afi_bvalid && (afi_bid[2:0]== 3'h5);
eof_written[2] <= afi_bvalid && (afi_bid[2:0]== 3'h6);
eof_written[3] <= afi_bvalid && (afi_bid[2:0]== 3'h7);
// calculate and rollover channel addresses
if (pre_busy_w) chunk_inc <= (|counts_corr2[7:2])?
3'h4 :
({1'b0,left_to_eof[winner2][1:0]} + 3'h1);
end
......@@ -304,7 +305,7 @@ module cmprs_afi_mux#(
.clk (hclk), // input
.rst (!en), // input
.dly (AFI_MUX_BUF_LATENCY), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
.din ({ wvalid, wlast, 3'b0,last_burst_in_frame, cur_chn}), // input[0:0]
.din ({ wvalid, wlast, afi_awid}), // input[0:0]
.dout ({afi_wvalid, afi_wlast, afi_wid}) // output[0:0]
);
......@@ -317,6 +318,42 @@ module cmprs_afi_mux#(
.din ({wvalid, cur_chn}), // input[0:0]
.dout ({wdata_en,wdata_sel}) // output[0:0]
);
wire [26:0] chunk_ptr_rd01[0:1];
cmprs_afi_mux_ptr cmprs_afi_mux_ptr_i (
.hclk (hclk), // input
.sa_len_di (cmd_data[26:0]), // input[26:0]
.sa_len_wa (cmd_a[2:0]), // input[2:0]
.sa_len_we (cmd_we_sa_len), // input
.en (en), // input
.reset_pointers (reset_pointers), // input[3:0]
.pre_busy_w (pre_busy_w), // input
.winner_channel (winner2), // input[1:0]
.need_to_bother (need_to_bother), // input
.chunk_inc (chunk_inc), // input[2:0]
.last_burst_in_frame (last_burst_in_frame), // input
.busy (busy), // input[3:0]
.ptr_resetting (ptr_resetting), // output
.chunk_addr (chunk_addr), // output[26:0] reg
.chunk_ptr_ra (chunk_ptr_ra[2:0]), // input[2:0]
.chunk_ptr_rd (chunk_ptr_rd01[0]) // output[26:0]
);
assign chunk_ptr_rd=chunk_ptr_ra[3]?chunk_ptr_rd01[1]:chunk_ptr_rd01[0];
cmprs_afi_mux_ptr_wresp cmprs_afi_mux_ptr_wresp_i (
.hclk (hclk), // input
.length_di (cmd_data[26:0]), // input[26:0]
.length_wa (cmd_a[1:0]), // input[1:0]
.length_we (cmd_we_sa_len & cmd_a[2]), // input
.en (en), // input
.reset_pointers (reset_pointers), // input[3:0]
.chunk_ptr_ra (chunk_ptr_ra[2:0]), // input[2:0]
.chunk_ptr_rd (chunk_ptr_rd01[1]), // output[26:0]
.eof_written ({eof_written3,eof_written2,eof_written1,eof_written0}), // output[3:0] reg
.afi_bvalid (afi_bvalid), // input
.afi_bready (afi_bready), // output
.afi_bid (afi_bid) // input[5:0]
);
endmodule
......
axi/cmprs_afi_mux_ptr.v 0 → 100644
View file @ d2699ad8
/*******************************************************************************
* Module: cmprs_afi_mux_ptr
* Date:2015-06-28
* Author: andrey
* Description: Maintain 4-channel chunk pointers (before AXI)
* Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmprs_afi_mux_ptr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmprs_afi_mux_ptr.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmprs_afi_mux_ptr(
input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels
// Write dual port 8x27 channel start address/length RAM
input [26:0] sa_len_di, // data to write per-channle buffer sa/length in chunks
input [ 2:0] sa_len_wa, // channel address to write sa/lengths
input sa_len_we, // write enable sa/length data
input en, // 0 - resets, 0->1 resets all pointers. While rezset allows write response
input [ 3:0] reset_pointers, // per-channel - reset pointers
input pre_busy_w, // combinatorial signal - one before busy[0] (depends on ptr_resetting)
input [ 1:0] winner_channel, // channel that won arbitration for AXI axxess, valid @ pre_busy_w
input need_to_bother, // whants to start access if address and data FIFO permit
input [2:0] chunk_inc, // how much to increment chunk pointer (1..4) - valid witrh busy[0]
input last_burst_in_frame, // valid with busy[0] (last_burst_in_frame<=last_chunk_w[winner2])
input [ 3:0] busy, // one cycle less than sending 1-4 bursts, [1] - delayed by 1, [2] - by 2
output ptr_resetting, // pointers will be reset next cycle (2-cycle-long pulse)
output reg [26:0] chunk_addr, // chunk absolute address, valid with busy[1]
input [ 2:0] chunk_ptr_ra, // chunk pointer read address {eof, chn[1:0]}
output [26:0] chunk_ptr_rd // chunk pointer read data (non-registered
);
reg [3:0] reset_rq; // request to reset pointers when ready
reg [3:0] reset_rq_pri; // one-hot reset rq
wire [1:0] reset_rq_enc; // encoded reset_rq_pri
wire start_resetting_w;
reg [1:0] resetting; // resetting chunk_pointer and eof_pointer
reg [2:0] ptr_wa; // pointer memory write port address, msb - eof/current, 2 LSB - channel
reg ptr_we; // pointer memory write enable
reg [26:0] ptr_ram[0:7]; // pointer (current and eof) memory (in 32-byte chunks
wire [26:0] ptr_ram_di; // data to be written to ptr_ram
reg [26:0] sa_len_ram[0:7]; // start chunk/num cunks in a buffer (write port @mclk)
reg [26:0] chunk_ptr_inc; // incremented by 1..4 chunk pointer
reg [27:0] chunk_ptr_rovr; // incremented chunk pointer, decremented by length (MSB - sign)
reg en_d; //enable delayed by 1 cycle
wire [ 2:0] sa_len_ra; // start/len read address
assign ptr_resetting = resetting[0];
assign sa_len_ra= {busy[1],ptr_wa[1:0]};
assign reset_rq_enc = {reset_rq_pri[3] | reset_rq_pri[2],
reset_rq_pri[3] | reset_rq_pri[1]};
assign ptr_ram_di= resetting[1] ? 27'b0 : (chunk_ptr_rovr[27] ? chunk_ptr_inc : chunk_ptr_rovr[26:0]);
assign chunk_ptr_rd = ptr_ram[chunk_ptr_ra];
assign start_resetting_w = en && !busy[0] && !resetting[0] && (|reset_rq) && !need_to_bother;
always @ (posedge hclk) begin
en_d <= en;
// ===== calculate and rollover channel addresses ====
// clear (during "resetting" or update 8x27 RAM that holds chunk pointers for the current burst and currenty frame
// uses (reads) additional memory with per-channel start addresses and lengths (both measured in 32-byte chunks
// read port of the ptr_ram will be used to monitor pointers through the status network
// TODO: Make sure correct RAM modules are inferred
// write length RAM
if (sa_len_we) sa_len_ram[sa_len_wa] <= sa_len_di;
if (start_resetting_w) reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),
reset_rq[2] & ~(|reset_rq[1:0]),
reset_rq[1] & ~reset_rq[0],
reset_rq[0]};
if (en && !en_d) reset_rq <= 4'hf;
else reset_rq <= reset_pointers | (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
if (!en) resetting <= 0;
else resetting <= {resetting[0], start_resetting_w | (resetting[0] & ~resetting[1])};
if (resetting == 2'b1) ptr_wa[1:0] <= reset_rq_enc;
else if (pre_busy_w) ptr_wa[1:0] <= winner_channel;
if (start_resetting_w || pre_busy_w) ptr_wa[2] <= 0;
else if (ptr_we) ptr_wa[2] <= 1;
ptr_we <= resetting[0] || // a pair of cycles to reset chunk pointer and frame chunk pointer
(busy[1] && !busy[2]) || // always update chunk pointer
(busy[2] && !busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
if (busy[0] && !busy[1]) begin // first clock of busy
// calculate full adderss for current AXI burst (valid 1 clk after busy)
chunk_addr <= ptr_ram[ptr_wa] + sa_len_ram[sa_len_ra];
chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc;
end
if (busy[1] && !busy[2]) begin // first clock of busy
chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,sa_len_ram[sa_len_ra]}; // sa_len_ra now points at length
end
// write to ptr_ram (1 or 2 locations - if eof)
if (ptr_we) ptr_ram[ptr_wa] <= ptr_ram_di;
end
endmodule
axi/cmprs_afi_mux_ptr_wresp.v 0 → 100644
View file @ d2699ad8
/*******************************************************************************
* Module: cmprs_afi_mux_ptr_wresp
* Date:2015-06-28
* Author: andrey
* Description: Maintain 4-channel chunk pointers for wrirte response
* Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmprs_afi_mux_ptr_wresp.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmprs_afi_mux_ptr_wresp.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmprs_afi_mux_ptr_wresp(
input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels
// Write dual port 4x27 channel length RAM (shadows 1/2 of the similar RAM for main pointers)
input [26:0] length_di, // data to write per-channle buffer length in chunks
input [ 1:0] length_wa, // channel address to write lengths
input length_we, // write enable length data
input en, // 0 - resets, 0->1 resets all pointers. While rezset allows write response
input [ 3:0] reset_pointers, // per-channel - reset pointers
input [ 2:0] chunk_ptr_ra, // chunk pointer read address {eof, chn[1:0]}
output [26:0] chunk_ptr_rd, // chunk pointer read data (non-registered
output reg [ 3:0] eof_written, // per-channel end of frame confirmed written to system memory by write response
// AFI write response channels
input afi_bvalid,
output afi_bready,
input [ 5:0] afi_bid // encodes channel, eof, and burst size minus 1 in chunks (0..3)
);
reg [3:0] reset_rq; // request to reset pointers when ready
reg [3:0] reset_rq_pri; // one-hot reset rq
wire [1:0] reset_rq_enc; // encoded reset_rq_pri
wire start_resetting_w;
reg [1:0] resetting; // resetting chunk_pointer and eof_pointer
wire [2:0] ptr_wa; // pointer memory write port address, msb - eof/current, 2 LSB - channel
reg ptr_we; // pointer memory write enable
reg [26:0] ptr_ram[0:7]; // pointer (current and eof) memory (in 32-byte chunks
wire [26:0] ptr_ram_di; // data to be written to ptr_ram
reg [26:0] len_ram[0:3]; // start chunk/num cunks in a buffer (write port @mclk)
reg [26:0] chunk_ptr_inc; // incremented by 1..4 chunk pointer
reg [27:0] chunk_ptr_rovr; // incremented chunk pointer, decremented by length (MSB - sign)
reg [ 3:0] busy; // one-hot busy stages (usually end with [3]
reg [ 5:0] id_r; // registered ID data
reg [1:0] chn; // selected channel
reg eof; // eof register being written
reg last_burst_in_frame; // this response is for eof
reg [2:0] chunk_inc;
reg afi_bready_r; //
reg afi_bvalid_r; // make it slow;
wire pre_busy;
wire pre_we;
reg en_d; //enable delayed by 1 cycle
assign reset_rq_enc = {reset_rq_pri[3] | reset_rq_pri[2],
reset_rq_pri[3] | reset_rq_pri[1]};
assign ptr_ram_di= resetting[1] ? 27'b0 : (chunk_ptr_rovr[27] ? chunk_ptr_inc : chunk_ptr_rovr[26:0]);
assign ptr_wa = {eof,chn};
assign afi_bready = afi_bready_r;
assign pre_we= resetting[0] || // a pair of cycles to reset chunk pointer and frame chunk pointer
busy[2] || // always update chunk pointer
(busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
assign pre_busy= afi_bvalid_r && en && !(|busy[1:0]) && !pre_we;
assign start_resetting_w = !afi_bvalid_r && en && !(|busy[1:0]) && !pre_we && (|reset_rq);
assign chunk_ptr_rd = ptr_ram[chunk_ptr_ra];
always @ (posedge hclk) begin
en_d <= en;
// write length RAM
if (length_we) len_ram[length_wa] <= length_di;
afi_bvalid_r <= afi_bvalid;
afi_bready_r <= !en || pre_busy; // (!busy[0] && !pre_busy && !resetting[0] && !start_resetting_w);
busy <= {busy[2:0], pre_busy}; // adjust bits
id_r <= afi_bid;
if (start_resetting_w) reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),
reset_rq[2] & ~(|reset_rq[1:0]),
reset_rq[1] & ~reset_rq[0],
reset_rq[0]};
if (en && !en_d) reset_rq <= 4'hf; // request reset all
else reset_rq <= reset_pointers | (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
if (!en) resetting <= 0;
else resetting <= {resetting[0], start_resetting_w | (resetting[0] & ~resetting[1])};
if (resetting == 2'b01) chn <= reset_rq_enc;
else if (busy[0]) chn <= id_r[0 +: 2];
if (busy[0]) begin // first busy cycle
last_burst_in_frame <= id_r[2];
chunk_inc <= {1'b0,id_r[3 +:2]} + 1;
end
ptr_we <= pre_we;
if ((resetting == 2'b01) || busy[0]) eof <= 0;
else if (ptr_we) eof <= 1; // always second write cycle
if (busy[1]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy
if (busy[2]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy
// write to ptr_ram (1 or 2 locations - if eof)
if (ptr_we) ptr_ram[ptr_wa] <= ptr_ram_di;
// Watch write response channel, detect EOF IDs, generate eof_written* output signals
eof_written[0] <= afi_bvalid_r && afi_bready_r && (id_r[2:0]== 3'h4);
eof_written[1] <= afi_bvalid_r && afi_bready_r && (id_r[2:0]== 3'h5);
eof_written[2] <= afi_bvalid_r && afi_bready_r && (id_r[2:0]== 3'h6);
eof_written[3] <= afi_bvalid_r && afi_bready_r && (id_r[2:0]== 3'h7);
end
endmodule
simulation_modules/simul_axi_hp_wr.v
View file @ d2699ad8
......@@ -314,7 +314,7 @@ fifo_same_clock_fill #( .DATA_WIDTH(79),.DATA_DEPTH(7))
.rcount (), //wdata_rcount), // output[3:0] reg
.num_in_fifo(wcount) // output[3:0]
);
// **** Write responce channel ****
// **** Write response channel ****
wire [ 1:0] bresp_value=2'b0;
wire [ 1:0] bresp_in;
......
x393.v
View file @ d2699ad8
......@@ -1088,7 +1088,7 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
.EMIOENET0SOFRX(), // GMII 0 Rx Start of Frame, output
.EMIOENET0PTPDELAYREQRX(), // GMII 0 Rx PTP delay req frame detected
.EMIOENET0PTPPDELAYREQRX(), // GMII 0 Rx PTP peer delay frame detected, output
.EMIOENET0PTPPDELAYRESPRX(), // GMII 0 Rx PTP peer delay responce frame detected, output
.EMIOENET0PTPPDELAYRESPRX(), // GMII 0 Rx PTP peer delay response frame detected, output
.EMIOENET0PTPSYNCFRAMERX(), // GMII 0 Rx PTP sync frame detected, output
// MDIO 0
.EMIOENET0MDIOMDC(), // MDIO 0 MD clock output, output
......@@ -1120,7 +1120,7 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
.EMIOENET1SOFRX(), // GMII 1 Rx Start of Frame, output
.EMIOENET1PTPDELAYREQRX(), // GMII 1 Rx PTP delay req frame detected
.EMIOENET1PTPPDELAYREQRX(), // GMII 1 Rx PTP peer delay frame detected, output
.EMIOENET1PTPPDELAYRESPRX(), // GMII 1 Rx PTP peer delay responce frame detected, output
.EMIOENET1PTPPDELAYRESPRX(), // GMII 1 Rx PTP peer delay response frame detected, output
.EMIOENET1PTPSYNCFRAMERX(), // GMII 1 Rx PTP sync frame detected, output
// MDIO 1
.EMIOENET1MDIOMDC(), // MDIO 1 MD clock output, output
......
x393_testbench01.tf
View file @ d2699ad8
......@@ -657,7 +657,7 @@ assign wready= x393_i.ps7_i.MAXIGP0WREADY;
assign x393_i.ps7_i.MAXIGP0WID= wid;
assign x393_i.ps7_i.MAXIGP0WLAST= wlast;
assign x393_i.ps7_i.MAXIGP0WSTRB= wstrb;
// Write responce
// Write response
assign bvalid= x393_i.ps7_i.MAXIGP0BVALID;
assign x393_i.ps7_i.MAXIGP0BREADY= bready;
assign bid= x393_i.ps7_i.MAXIGP0BID;
......
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