Commit 59a577c9 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

made membridge work in system -> videobuffer mode

parent 9b16ac66

.project

+15 −15
Original line number Diff line number Diff line
@@ -62,77 +62,77 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150430123957882.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150503212342992.log</location>

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			<type>1</type>

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			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150503212342992.log</location>

		</link>

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			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150430123957882.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150503212342992.log</location>

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			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150430123957882.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150503212342992.log</location>

		</link>

		<link>

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			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150503212342992.log</location>

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			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150430123957882.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150503212342992.log</location>

		</link>

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			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150430123759800.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150503212133457.log</location>

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		</link>

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			<location>/home/andrey/git/x393/vivado_state/x393-place-20150503212342992.dcp</location>

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			<location>/home/andrey/git/x393/vivado_state/x393-route-20150430123957882.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-route-20150503212342992.dcp</location>

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			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150430123759800.dcp</location>

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</projectDescription>

axi/membridge.v

+3 −2
Original line number Diff line number Diff line
@@ -518,10 +518,11 @@ module membridge#( 
        else if (!page_ready_wr &&  next_page_wr_w) write_pages_ready <= write_pages_ready +1; //-1;



    end

        

    reg [63:0] rdata_r;        

    always @ (posedge hclk) begin

        write_page_r    <= write_page;

        buf_in_line64_r <= buf_in_line64[6:0];

        rdata_r <= afi_rdata;

    end    

        

    cmd_deser #(
@@ -579,7 +580,7 @@ module membridge#( 
        .ext_clk      (hclk), // input

        .ext_waddr    ({write_page_r, buf_in_line64_r[6:0]}), // input[8:0] 

        .ext_we       (bufwr_we[1]), // input

        .ext_data_in  (afi_rdata), // input[63:0] buf_wdata - from AXI

        .ext_data_in  (rdata_r), //afi_rdata), // input[63:0] buf_wdata - from AXI

        .rclk         (mclk), // input

        .rpage_in     (2'b0), // input[1:0] 

        .rpage_set    (xfer_reset_page_wr), // input  @ posedge mclk

x393_testbench01.sav

+51 −15
Original line number Diff line number Diff line 
[*]

[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI

[*] Thu Apr 30 18:37:14 2015

[*] Mon May  4 03:20:08 2015

[*]

[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150430120701234.lxt"

[dumpfile_mtime] "Thu Apr 30 18:10:21 2015"

[dumpfile_size] 174023349

[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150503211205371.lxt"

[dumpfile_mtime] "Mon May  4 03:17:38 2015"

[dumpfile_size] 274999726

[savefile] "/home/andrey/git/x393/x393_testbench01.sav"

[timestart] 37450000

[timestart] 41895630

[size] 1823 1180

[pos] 1919 0

*-21.063198 46660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

*-13.063198 41917667 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[treeopen] x393_testbench01.

[treeopen] x393_testbench01.ddr3_i.

[treeopen] x393_testbench01.simul_axi_hp_wr_i.

[treeopen] x393_testbench01.x393_i.

[sst_width] 301

[signals_width] 446

[treeopen] x393_testbench01.x393_i.membridge_i.

[sst_width] 202

[signals_width] 547

[sst_expanded] 1

[sst_vpaned_height] 367

[sst_vpaned_height] 644

@800200

-DDR3

@28
@@ -199,7 +200,7 @@ x393_testbench01.simul_axi_hp_wr_i.wstrb_out[7:0] 
x393_testbench01.simul_axi_hp_wr_i.wvalid[0]

@1401200

-simul_afi_wr

@c00200

@800200

-simul_afi_rd

@28

x393_testbench01.simul_axi_hp_rd_i.aclk[0]
@@ -229,8 +230,8 @@ x393_testbench01.simul_axi_hp_rd_i.arready[0] 
x393_testbench01.simul_axi_hp_rd_i.arsize[2:0]

x393_testbench01.simul_axi_hp_rd_i.arsize_out[2:0]

x393_testbench01.simul_axi_hp_rd_i.arvalid[0]

x393_testbench01.simul_axi_hp_rd_i.fifo_data_rd[0]

@22

x393_testbench01.simul_axi_hp_rd_i.fifo_data_rd[0]

x393_testbench01.simul_axi_hp_rd_i.fifo_with_requested[7:0]

@28

x393_testbench01.simul_axi_hp_rd_i.last_confirmed_read[0]
@@ -283,14 +284,19 @@ x393_testbench01.simul_axi_hp_rd_i.rst[0] 
x393_testbench01.simul_axi_hp_rd_i.rvalid[0]

@22

x393_testbench01.simul_axi_hp_rd_i.sim_rd_address[31:0]

@28

x393_testbench01.simul_axi_hp_rd_i.sim_rd_cap[2:0]

@22

x393_testbench01.simul_axi_hp_rd_i.sim_rd_data[63:0]

x393_testbench01.simul_axi_hp_rd_i.sim_rd_qos[3:0]

@28

x393_testbench01.simul_axi_hp_rd_i.sim_rd_ready[0]

@c00029

x393_testbench01.simul_axi_hp_rd_i.sim_rd_resp[1:0]

@29

(0)x393_testbench01.simul_axi_hp_rd_i.sim_rd_resp[1:0]

(1)x393_testbench01.simul_axi_hp_rd_i.sim_rd_resp[1:0]

@1401201

-group_end

@28

x393_testbench01.simul_axi_hp_rd_i.sim_rd_valid[0]

@22

x393_testbench01.simul_axi_hp_rd_i.sim_rid[5:0]
@@ -299,11 +305,42 @@ x393_testbench01.simul_axi_hp_rd_i.start_read_burst_w[0] 
x393_testbench01.simul_axi_hp_rd_i.was_addr_fifo_write[0]

x393_testbench01.simul_axi_hp_rd_i.was_data_fifo_read[0]

x393_testbench01.simul_axi_hp_rd_i.was_data_fifo_write[0]

@1401200

@1000200

-simul_afi_rd

@800200

-membridge

@22

x393_testbench01.x393_i.membridge_i.afi_arlen[3:0]

@28

x393_testbench01.x393_i.membridge_i.afi_arvalid[0]

x393_testbench01.x393_i.membridge_i.afi_rvalid[0]

x393_testbench01.x393_i.membridge_i.afi_rready[0]

@800028

x393_testbench01.x393_i.membridge_i.bufwr_we[1:0]

@28

(0)x393_testbench01.x393_i.membridge_i.bufwr_we[1:0]

(1)x393_testbench01.x393_i.membridge_i.bufwr_we[1:0]

@1001200

-group_end

@28

x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_we[0]

@c00022

x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]

@28

(0)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]

(1)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]

(2)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]

(3)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]

(4)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]

(5)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]

(6)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]

(7)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]

(8)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]

@1401200

-group_end

@22

x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_data_in[63:0]

x393_testbench01.x393_i.membridge_i.afi_rdata[63:0]

x393_testbench01.x393_i.membridge_i.last_in_line64[13:0]

x393_testbench01.x393_i.membridge_i.buf_in_line64[13:0]

@28
@@ -324,7 +361,6 @@ x393_testbench01.simul_axi_hp_wr_i.awready[0] 
x393_testbench01.simul_axi_hp_wr_i.awvalid[0]

x393_testbench01.simul_axi_hp_wr_i.aw_nempty[0]

x393_testbench01.simul_axi_hp_wr_i.wvalid[0]

@29

x393_testbench01.x393_i.membridge_i.left_was_1[0]

@c00022

x393_testbench01.x393_i.membridge_i.src_wcntr[3:0]

x393_testbench01.tf

+1 −1
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ module x393_testbench01 #( 


  assign HCLK = x393_i.ps7_i.SAXIHP0ACLK; // shortcut name

// afi loopback

  assign #1 afi_sim_rd_data= {2'h0,afi_sim_rd_address[31:3],1'h1,  2'h0,afi_sim_rd_address[31:3],1'h0};

  assign #1 afi_sim_rd_data=  afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1,  2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;

  assign #1 afi_sim_rd_valid = afi_sim_rd_ready;

  assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;

  assign #1 afi_sim_wr_ready = afi_sim_wr_valid;