Commit 05378ee7 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

working on synthesis with Vivado tools

parent df69d555

.editor_defines.vh

+1 −75
Original line number Diff line number Diff line
@@ -2,79 +2,5 @@ 


// TODO: Fix VDT - without IVERILOG defined, closure does not include modules needed for Icarus

`define IVERILOG 1

`undef DEBUG_FIFO

`define USE_CMD_ENCOD_TILED_32_RD 1  

  // It can be used to check different `ifdef branches

  //`define XIL_TIMING //Simprim 

  `define den4096Mb 1

//  `define IVERILOG

  // defines for memory channels

  // chn 0 is read from memory and write to memory

 `define def_enable_mem_chn0

 `define def_read_mem_chn0

 `define def_write_mem_chn0

 `undef  def_scanline_chn0

 `undef  def_tiled_chn0

 

  // chn 1 is scanline r+w

 `define  def_enable_mem_chn1

 `define  def_read_mem_chn1

 `define  def_write_mem_chn1

 `define  def_scanline_chn1

 `undef   def_tiled_chn1



  // chn 2 is tiled r+w

 `define  def_enable_mem_chn2

 `define  def_read_mem_chn2

 `define  def_write_mem_chn2

 `undef   def_scanline_chn2

 `define  def_tiled_chn2



  // chn 3 is scanline r+w (reuse later)

 `define  def_enable_mem_chn3

 `define  def_read_mem_chn3

 `define  def_write_mem_chn3

 `define  def_scanline_chn3

 `undef   def_tiled_chn3



  // chn 4 is tiled r+w (reuse later)

 `define  def_enable_mem_chn4

 `define  def_read_mem_chn4

 `define  def_write_mem_chn4

 `undef   def_scanline_chn4

 `define  def_tiled_chn4



  // chn 5 is disabled

 `undef def_enable_mem_chn5



  // chn 6 is disabled

 `undef  def_enable_mem_chn6

 

  // chn 7 is disabled

 `undef  def_enable_mem_chn7

 

  // chn 8 is disabled

 `undef  def_enable_mem_chn8

 

  // chn 9 is disabled

 `undef  def_enable_mem_chn9

 

  // chn 10 is disabled

 `undef  def_enable_mem_chn10

 

  // chn 11 is disabled

 `undef  def_enable_mem_chn11

 

  // chn 12 is disabled

 `undef  def_enable_mem_chn12

 

  // chn 13 is disabled

 `undef  def_enable_mem_chn13

 

  // chn 14 is disabled

 `undef  def_enable_mem_chn14

 

  // chn 15 is disabled

 `undef  def_enable_mem_chn15

 

`include "system_defines.vh"

 
 No newline at end of file

.project

+17 −17
Original line number Diff line number Diff line
@@ -52,87 +52,87 @@ 
		<link>

			<name>ise_logs/ISExst.log</name>

			<type>1</type>

			<location>ise_logs/ISExst-20140607155721361.log</location>

			<location>/home/andrey/git/x393/ise_logs/ISExst-20150226190731427.log</location>

		</link>

		<link>

			<name>ise_state/x393-synth.tgz</name>

			<type>1</type>

			<location>ise_state/x393-synth-20140607155721361.tgz</location>

			<location>/home/andrey/git/x393/ise_state/x393-synth-20150226190731427.tgz</location>

		</link>

		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoBitstream-20140611174132808.log</location>

			<locationURI>vivado_logs/VivadoBitstream-20140611174132808.log</locationURI>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoOpt-20140611174132808.log</location>

			<locationURI>vivado_logs/VivadoOpt-20140611174132808.log</locationURI>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoOptPhys-20140611174132808.log</location>

			<locationURI>vivado_logs/VivadoOptPhys-20140611174132808.log</locationURI>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoOptPower-20140611174132808.log</location>

			<locationURI>vivado_logs/VivadoOptPower-20140611174132808.log</locationURI>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoPlace-20140611174132808.log</location>

			<locationURI>vivado_logs/VivadoPlace-20140611174132808.log</locationURI>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoRoute-20140611174132808.log</location>

			<locationURI>vivado_logs/VivadoRoute-20140611174132808.log</locationURI>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoSynthesis-20140611174056482.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150227195107460.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoTimimgSummaryReportImplemented-20140611174132808.log</location>

			<locationURI>vivado_logs/VivadoTimimgSummaryReportImplemented-20140611174132808.log</locationURI>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoTimimgSummaryReportSynthesis-20140611174132808.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150227195107460.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoTimingReportImplemented-20140611174132808.log</location>

			<locationURI>vivado_logs/VivadoTimingReportImplemented-20140611174132808.log</locationURI>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>vivado_logs/VivadoTimingReportSynthesis-20140611174132808.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150227195107460.log</location>

		</link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>

			<type>1</type>

			<location>vivado_state/x393-opt-phys-20140611174132808.dcp</location>

			<locationURI>vivado_state/x393-opt-phys-20140611174132808.dcp</locationURI>

		</link>

		<link>

			<name>vivado_state/x393-place.dcp</name>

			<type>1</type>

			<location>vivado_state/x393-place-20140611174132808.dcp</location>

			<locationURI>vivado_state/x393-place-20140611174132808.dcp</locationURI>

		</link>

		<link>

			<name>vivado_state/x393-route.dcp</name>

			<type>1</type>

			<location>vivado_state/x393-route-20140611174132808.dcp</location>

			<locationURI>vivado_state/x393-route-20140611174132808.dcp</locationURI>

		</link>

		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<location>vivado_state/x393-synth-20140610113942407.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150227195107460.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

.settings/com.elphel.vdt.ISExst.prefs

+2 −1
Original line number Diff line number Diff line 
ISExst_170_constraints=ddrc_test01.xcf

com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->

ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->

com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->

eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoSynthesis.prefs

+6 −2
Original line number Diff line number Diff line 
VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->ddrc_test01_timing.xdc<-@\#\#@->

VivadoSynthesis_101_MaxMsg=10000

VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->

VivadoSynthesis_115_flatten_hierarchy=none

VivadoSynthesis_127_verbose=true

VivadoSynthesis_81_parser_mode=1

VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->

VivadoSynthesis_95_ShowInfo=false

com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->

com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->

eclipse.preferences.version=1

axi/axibram_read.v

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *******************************************************************************/

 // Check that this fix did not break anything:

`include "system_defines.vh" 

`define USE_SHORT_REN_REGEN 

module  axibram_read #(

    parameter ADDRESS_BITS = 10 // number of memory address bits