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Commit 05378ee7 authored by Andrey Filippov's avatar Andrey Filippov
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working on synthesis with Vivado tools

parent df69d555
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.editor_defines.vh
View file @ 05378ee7
......@@ -2,79 +2,5 @@
// TODO: Fix VDT - without IVERILOG defined, closure does not include modules needed for Icarus
`define IVERILOG 1
`undef DEBUG_FIFO
`define USE_CMD_ENCOD_TILED_32_RD 1
// It can be used to check different `ifdef branches
//`define XIL_TIMING //Simprim
`define den4096Mb 1
// `define IVERILOG
// defines for memory channels
// chn 0 is read from memory and write to memory
`define def_enable_mem_chn0
`define def_read_mem_chn0
`define def_write_mem_chn0
`undef def_scanline_chn0
`undef def_tiled_chn0
// chn 1 is scanline r+w
`define def_enable_mem_chn1
`define def_read_mem_chn1
`define def_write_mem_chn1
`define def_scanline_chn1
`undef def_tiled_chn1
// chn 2 is tiled r+w
`define def_enable_mem_chn2
`define def_read_mem_chn2
`define def_write_mem_chn2
`undef def_scanline_chn2
`define def_tiled_chn2
// chn 3 is scanline r+w (reuse later)
`define def_enable_mem_chn3
`define def_read_mem_chn3
`define def_write_mem_chn3
`define def_scanline_chn3
`undef def_tiled_chn3
// chn 4 is tiled r+w (reuse later)
`define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_write_mem_chn4
`undef def_scanline_chn4
`define def_tiled_chn4
// chn 5 is disabled
`undef def_enable_mem_chn5
// chn 6 is disabled
`undef def_enable_mem_chn6
// chn 7 is disabled
`undef def_enable_mem_chn7
// chn 8 is disabled
`undef def_enable_mem_chn8
// chn 9 is disabled
`undef def_enable_mem_chn9
// chn 10 is disabled
`undef def_enable_mem_chn10
// chn 11 is disabled
`undef def_enable_mem_chn11
// chn 12 is disabled
`undef def_enable_mem_chn12
// chn 13 is disabled
`undef def_enable_mem_chn13
// chn 14 is disabled
`undef def_enable_mem_chn14
// chn 15 is disabled
`undef def_enable_mem_chn15
`include "system_defines.vh"
\ No newline at end of file
.project
View file @ 05378ee7
......@@ -52,87 +52,87 @@
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</projectDescription>
.settings/com.elphel.vdt.ISExst.prefs
View file @ 05378ee7
ISExst_170_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->
ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 05378ee7
VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->ddrc_test01_timing.xdc<-@\#\#@->
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
eclipse.preferences.version=1
axi/axibram_read.v
View file @ 05378ee7
......@@ -19,6 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// Check that this fix did not break anything:
`include "system_defines.vh"
`define USE_SHORT_REN_REGEN
module axibram_read #(
parameter ADDRESS_BITS = 10 // number of memory address bits
......
axi/axibram_write.v
View file @ 05378ee7
......@@ -20,6 +20,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
//`define DEBUG_FIFO 1
`include "system_defines.vh"
`undef DEBUG_FIFO
module axibram_write #(
parameter ADDRESS_BITS = 10 // number of memory address bits
......
includes/x393_parameters.vh
View file @ 05378ee7
......@@ -208,7 +208,7 @@
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN2_ADDR= 'h140,
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_CHN4_ADDR= 'h150,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......
memctrl/cmd_encod_4mux.v
View file @ 05378ee7
......@@ -25,27 +25,27 @@ module cmd_encod_4mux(
input clk,
input start0, // this channel was started
input [31:0] enc_cmd0, // encoded commnad
input [31:0] enc_cmd0, // encoded command
input enc_wr0, // write encoded command
input enc_done0, // encoding finished
input start1, // this channel was started
input [31:0] enc_cmd1, // encoded commnad
input [31:0] enc_cmd1, // encoded command
input enc_wr1, // write encoded command
input enc_done1, // encoding finished
input start2, // this channel was started
input [31:0] enc_cmd2, // encoded commnad
input [31:0] enc_cmd2, // encoded command
input enc_wr2, // write encoded command
input enc_done2, // encoding finished
input start3, // this channel was started
input [31:0] enc_cmd3, // encoded commnad
input [31:0] enc_cmd3, // encoded command
input enc_wr3, // write encoded command
input enc_done3, // encoding finished
output reg start, // combined output was started (1 clk from |start*)
output reg [31:0] enc_cmd, // encoded commnad
output reg [31:0] enc_cmd, // encoded command
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
......
memctrl/cmd_encod_linear_mux.v
View file @ 05378ee7
......@@ -21,7 +21,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
module cmd_encod_linear_mux#(
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10
......
memctrl/cmd_encod_linear_rd.v
View file @ 05378ee7
......@@ -40,7 +40,7 @@ module cmd_encod_linear_rd #(
input [NUM_XFER_BITS-1:0] num128_in, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input skip_next_page_in, // do not reset external buffer (continue)
input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad
output reg [31:0] enc_cmd, // encoded command SuppressThisWarning VivadoSynthesis [Synth 8-3332] Sequential element cmd_encod_linear_rd.enc_cmd_reg[10:9,7:5,2] is unused and will be removed from module cmd_encod_linear_rd.
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
......@@ -77,7 +77,7 @@ module cmd_encod_linear_rd #(
// reg gen_run_d;
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
reg [ROM_WIDTH-1:0] rom_r; // SuppressThisWarning VivadoSynthesis [Synth 8-3332] Sequential element cmd_encod_linear_rd.rom_r_reg[0] is unused and will be removed from module cmd_encod_linear_rd.
wire pre_done;
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
......
memctrl/cmd_encod_linear_rw.v
View file @ 05378ee7
......@@ -41,14 +41,14 @@ module cmd_encod_linear_rw#(
input start_rd, // start generating commands by cmd_encod_linear_rd
input start_wr, // start generating commands by cmd_encod_linear_wr
output reg start, // this channel was started (1 clk from start_rd || start_wr
output reg [31:0] enc_cmd, // encoded commnad
output reg [31:0] enc_cmd, // encoded command
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
wire [31:0] enc_cmd_rd; // encoded commnad
wire [31:0] enc_cmd_rd; // encoded command
wire enc_wr_rd; // write encoded command
wire enc_done_rd; // encoding finished
wire [31:0] enc_cmd_wr; // encoded commnad
wire [31:0] enc_cmd_wr; // encoded command
wire enc_wr_wr; // write encoded command
wire enc_done_wr; // encoding finished
reg select_wr;
......
memctrl/cmd_encod_linear_wr.v
View file @ 05378ee7
......@@ -37,7 +37,7 @@ module cmd_encod_linear_wr #(
input [NUM_XFER_BITS-1:0] num128_in, // number of 128-bit words to transfer (8*16 bits) - full burst of 8 (0 - full 64)
input skip_next_page_in, // do not reset external buffer (continue)
input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad
output reg [31:0] enc_cmd, // encoded command SuppressThisWarning VivadoSynthesis [Synth 8-3332] Sequential element cmd_encod_linear_wr.enc_cmd_reg[9,6,4:3] is unused and will be removed from module cmd_encod_linear_wr.
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
......@@ -90,7 +90,7 @@ module cmd_encod_linear_wr #(
// reg gen_run_d;
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
reg [ROM_WIDTH-1:0] rom_r; // SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_linear_wr.rom_r_reg[8] is unused and will be removed from module cmd_encod_linear_wr.
wire pre_done;
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
......@@ -103,7 +103,7 @@ module cmd_encod_linear_wr #(
reg dual_write; // Two bursts have to be written
reg few_write; //write 1,2 or 3 bursts
wire write_addr_w; // gen_addr that generates write commands
reg [ROM_DEPTH-1:0] jump_gen_addr; // will overrun as stop comes from ROM
reg [ROM_DEPTH-1:0] jump_gen_addr; // will overrun as stop comes from ROM SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_linear_wr.jump_gen_addr_reg[0] is unused and will be removed from module cmd_encod_linear_wr.
assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2];
......@@ -155,7 +155,7 @@ module cmd_encod_linear_wr #(
// else few_write <= single_write | dual_write | triple_write;
if (rst) jump_gen_addr <= 0;
else jump_gen_addr <= single_write ? NO_WRITE_ADDR : (dual_write ? LAST_WRITE_ADDR:PRELAST_WRITE_ADDR);
else jump_gen_addr <= single_write ? NO_WRITE_ADDR : (dual_write ? LAST_WRITE_ADDR : PRELAST_WRITE_ADDR);
//triple_write
......
memctrl/cmd_encod_tiled_32_rd.v
View file @ 05378ee7
......@@ -63,7 +63,7 @@ module cmd_encod_tiled_32_rd #(
input keep_open_in, // keep banks open (for <=8 banks only
input skip_next_page_in, // do not reset external buffer (continue)
input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad
output reg [31:0] enc_cmd, // encoded command SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.enc_cmd_reg[11:9,7:5,2] is unused and will be removed from module cmd_encod_tiled_32_rd.
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
......@@ -94,10 +94,10 @@ module cmd_encod_tiled_32_rd #(
// localparam AUTOPRECHARGE_BIT=COLADDR_NUMBER;
reg [ADDRESS_NUMBER-1:0] row; // memory row
reg [COLADDR_NUMBER-4:0] col; // start memory column in 8-bursts
reg [COLADDR_NUMBER-4:0] col; // start memory column in 8-bursts SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.col_reg[0] is unused and will be removed from module cmd_encod_tiled_32_rd.
reg [2:0] bank; // memory bank;
reg [5:0] num_rows_m1; // number of rows in a tile minus 1
reg [5:0] num_cols128_m2; // number of r16-byte columns in a tile -2 (even columns)
reg [5:0] num_cols128_m2; // number of r16-byte columns in a tile -2 (even columns) SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.num_cols128_m2_reg[0] is unused and will be removed from module cmd_encod_tiled_32_rd.
// reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
reg [FRAME_WIDTH_BITS:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
......@@ -120,7 +120,7 @@ module cmd_encod_tiled_32_rd #(
wire pre_act; //1 cycle before optional ACTIVATE
wire pre_read; //1 cycle before READ command
reg [5:0] scan_row; // current row in a tile (valid @pre_act)
reg [5:0] scan_col; // current 16-byte column in a tile (valid @pre_act)
reg [5:0] scan_col; // current 16-byte column in a tile (valid @pre_act) SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.scan_col_reg[0] is unused and will be removed from module cmd_encod_tiled_32_rd.
reg start_d; // start, delayed by 1 clocks
wire last_row;
reg [FULL_ADDR_NUMBER-1:0] row_col_bank; // RA,CA, BA - valid @pre_act;
......@@ -269,7 +269,7 @@ module cmd_encod_tiled_32_rd #(
rom_cmd[1]?
row_col_bank[2:0]:
col_bank[2:0], //
full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic
full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic. full_cmd[0]==0 (never write/precharge) => enc_cmd_reg[11]==0
1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE
rom_r[ENC_SEL], // sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
......
memctrl/cmd_encod_tiled_32_rw.v
View file @ 05378ee7
......@@ -41,14 +41,14 @@ module cmd_encod_tiled_32_rw #(
input start_rd, // start generating commands by cmd_encod_linear_rd
input start_wr, // start generating commands by cmd_encod_linear_wr
output reg start, // this channel was started (1 clk from start_rd || start_wr
output reg [31:0] enc_cmd, // encoded commnad
output reg [31:0] enc_cmd, // encoded command
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
wire [31:0] enc_cmd_rd; // encoded commnad
wire [31:0] enc_cmd_rd; // encoded command
wire enc_wr_rd; // write encoded command
wire enc_done_rd; // encoding finished
wire [31:0] enc_cmd_wr; // encoded commnad
wire [31:0] enc_cmd_wr; // encoded command
wire enc_wr_wr; // write encoded command
wire enc_done_wr; // encoding finished
reg select_wr;
......
memctrl/cmd_encod_tiled_32_wr.v
View file @ 05378ee7
......@@ -63,7 +63,7 @@ module cmd_encod_tiled_32_wr #(
input keep_open_in, // keep banks open (for <=8 banks only
input skip_next_page_in, // do not reset external buffer (continue)
input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad
output reg [31:0] enc_cmd, // encoded command
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
......
memctrl/cmd_encod_tiled_mux.v
View file @ 05378ee7
......@@ -21,7 +21,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
module cmd_encod_tiled_mux #(
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
......
memctrl/cmd_encod_tiled_rd.v
View file @ 05378ee7
......@@ -63,7 +63,7 @@ module cmd_encod_tiled_rd #(
input keep_open_in, // keep banks open (for <=8 banks only
input skip_next_page_in, // do not reset external buffer (continue)
input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad
output reg [31:0] enc_cmd, // encoded command SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_rd.enc_cmd_reg[11:9,7:5,2] is unused and will be removed from module cmd_encod_tiled_rd.
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
......@@ -264,7 +264,7 @@ module cmd_encod_tiled_rd #(
rom_cmd[1]?
row_col_bank[2:0]:
col_bank[2:0], //
full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic
full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic. full_cmd[0]==0 (never write/precharge) => enc_cmd_reg[11]==0
1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE
rom_r[ENC_SEL], // sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
......
memctrl/cmd_encod_tiled_rw.v
View file @ 05378ee7
......@@ -41,14 +41,14 @@ module cmd_encod_tiled_rw #(
input start_rd, // start generating commands by cmd_encod_linear_rd
input start_wr, // start generating commands by cmd_encod_linear_wr
output reg start, // this channel was started (1 clk from start_rd || start_wr
output reg [31:0] enc_cmd, // encoded commnad
output reg [31:0] enc_cmd, // encoded command
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
wire [31:0] enc_cmd_rd; // encoded commnad
wire [31:0] enc_cmd_rd; // encoded command
wire enc_wr_rd; // write encoded command
wire enc_done_rd; // encoding finished
wire [31:0] enc_cmd_wr; // encoded commnad
wire [31:0] enc_cmd_wr; // encoded command
wire enc_wr_wr; // write encoded command
wire enc_done_wr; // encoding finished
reg select_wr;
......
memctrl/cmd_encod_tiled_wr.v
View file @ 05378ee7
......@@ -64,7 +64,7 @@ module cmd_encod_tiled_wr #(
input keep_open_in, // keep banks open (for <=8 banks only
input skip_next_page_in, // do not reset external buffer (continue)
input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad
output reg [31:0] enc_cmd, // encoded command SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_wr.enc_cmd_reg[11,9,6,4:3,1] is unused and will be removed from module cmd_encod_tiled_wr.
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
......@@ -107,7 +107,7 @@ module cmd_encod_tiled_wr #(
// reg gen_run_d; // to output "done"?
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
reg [ROM_WIDTH-1:0] rom_r; // SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_wr.rom_r_reg[8,0] is unused and will be removed from module cmd_encod_tiled_wr.
wire pre_done;
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
......@@ -153,7 +153,7 @@ module cmd_encod_tiled_wr #(
assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2]; // & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)
assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];
assign full_cmd= (enable_act && rom_cmd[1])?CMD_ACTIVATE:(rom_cmd[0]?CMD_WRITE:CMD_NOP);
assign full_cmd= (enable_act && rom_cmd[1]) ? CMD_ACTIVATE : (rom_cmd[0] ? CMD_WRITE : CMD_NOP);
assign last_row= (scan_row==num_rows_m1);
assign enable_act= first_col || !keep_open; // TODO: do not forget to zero addresses too (or they will become pause/done)
......
memctrl/mcntrl393.v
View file @ 05378ee7
......@@ -19,7 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
module mcntrl393 #(
// AXI
parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
......@@ -994,6 +994,7 @@ module mcntrl393 #(
.xfer_page_rst_wr (xfer_reset_page3_wr), // output
.xfer_page_rst_rd (xfer_reset_page3_rd) // output
);
mcntrl_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
......@@ -1010,7 +1011,7 @@ module mcntrl393 #(
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_CHN2_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
......
memctrl/mcntrl_linear_rw.v
View file @ 05378ee7
......@@ -87,7 +87,10 @@ module mcntrl_linear_rw #(
reg [FRAME_HEIGHT_BITS:0] next_y; // (calculated) next row number
reg [NUM_RC_BURST_BITS-1:0] line_start_addr;// (calculated) Line start (in {row,col8} in burst8
// calculating full width from the frame width
reg [FRAME_HEIGHT_BITS-1:0] frame_y; // current line number referenced to the frame top
// WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_linear_rw.v:268]
// Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used
// outside of the DSP 48. "dont_touch" seems to work here
(* keep = "true" *) reg [FRAME_HEIGHT_BITS-1:0] frame_y; // current line number referenced to the frame top
reg [FRAME_WIDTH_BITS-1:0] frame_x; // current column number referenced to the frame left
reg [FRAME_HEIGHT_BITS-4:0] frame_y8_r; // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler)
reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY
......
memctrl/mcntrl_ps_pio.v
View file @ 05378ee7
......@@ -20,6 +20,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
`undef DEBUG_FIFO
module mcntrl_ps_pio#(
parameter MCNTRL_PS_ADDR= 'h100,
......
memctrl/mcntrl_tiled_rw.v
View file @ 05378ee7
......@@ -100,7 +100,10 @@ module mcntrl_tiled_rw#(
reg [NUM_RC_BURST_BITS-1:0] line_start_addr;// (calculated) Line start (in {row,col8} in burst8
reg [COLADDR_NUMBER-4:0] line_start_page_left; // number of 8-burst left in the memory page from the start of the frame line
// calculating full width from the frame width
reg [FRAME_HEIGHT_BITS-1:0] frame_y; // current line number referenced to the frame top
//WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_tiled_rw.v:307]
// Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used
// outside of the DSP 48. "dont_touch" seems to work here
(* keep = "true" *) reg [FRAME_HEIGHT_BITS-1:0] frame_y; // current line number referenced to the frame top
reg [FRAME_WIDTH_BITS-1:0] frame_x; // current column number referenced to the frame left
reg [FRAME_HEIGHT_BITS-4:0] frame_y8_r; // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler)
reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY
......@@ -167,14 +170,15 @@ module mcntrl_tiled_rw#(
// wire msw13_zero=!(|cmd_data[FRAME_WIDTH_BITS+15:16]); // MSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
wire tile_width_zero= !(|cmd_data[ 0+:MAX_TILE_WIDTH]);
wire tile_height_zero=!(|cmd_data[ 8+:MAX_TILE_HEIGHT]);
// wire tile_height_zero=!(|cmd_data[ 8+:MAX_TILE_HEIGHT]);
wire tile_vstep_zero= !(|cmd_data[16+:MAX_TILE_HEIGHT]);
// reg [5:0] mode_reg;//mode register: {write_mode,keep_open,extra_pages[1:0],enable,!reset}
reg [6:0] mode_reg;//mode register: {byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_addr; // (programmed) Frame start (in {row,col8} in burst8, bank ==0
reg [MAX_TILE_WIDTH:0] tile_cols; // full number of columns in a tile
reg [MAX_TILE_HEIGHT:0] tile_rows; // full number of rows in a tile
// reg [MAX_TILE_HEIGHT:0] tile_rows; // full number of rows in a tile
reg [MAX_TILE_HEIGHT-1:0] tile_rows; // full number of rows in a tile
reg [MAX_TILE_HEIGHT:0] tile_vstep; // vertical step between rows of tiles
reg [MAX_TILE_WIDTH:0] num_cols_r; // full number of columns to transfer (not minus 1)
......@@ -227,7 +231,8 @@ module mcntrl_tiled_rw#(
tile_vstep <= 0;
end else if (set_tile_whs_w) begin
tile_cols <= {tile_width_zero, cmd_data[ 0+:MAX_TILE_WIDTH]};
tile_rows <= {tile_height_zero, cmd_data[ 8+:MAX_TILE_HEIGHT]};
// tile_rows <= {tile_height_zero, cmd_data[ 8+:MAX_TILE_HEIGHT]};
tile_rows <= { cmd_data[ 8+:MAX_TILE_HEIGHT]};
tile_vstep <= {tile_vstep_zero, cmd_data[16+:MAX_TILE_HEIGHT]};
end
......
memctrl/memctrl16.v
View file @ 05378ee7
......@@ -19,8 +19,9 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
`define use200Mhz 1
`define DEBUG_FIFO 1
//`define DEBUG_FIFO 1
module memctrl16 #(
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
......@@ -604,6 +605,23 @@ wire rst=rst_in; // TODO: decide where toi generate
reg [15:0] chn_want_r;
wire [17:0] status_data;
wire [2:0] mcontr_0bit_addr;
wire mcontr_0bit_we;
wire [2:0] mcontr_16bit_addr;
// ???
// wire [15:0] aaaa;
// assign aaaa={cmd_ad,cmd_ad};// just debugging Vivado synth
wire [15:0] mcontr_16bit_data; // = {cmd_ad,cmd_ad};
// assign mcontr_16bit_data={cmd_ad,cmd_ad};// just debugging Vivado synth
wire mcontr_16bit_we;
// wire [15:0] aaaa;
// assign aaaa={cmd_ad,cmd_ad};// just debugging Vivado synth
assign status_data={chn_want_r,chn_need_some,chn_want_some};
// mux status info from the memory controller and other modules
......@@ -653,8 +671,6 @@ wire rst=rst_in; // TODO: decide where toi generate
);
// generate on/off dependent on lsb and 0-bit commands
wire [2:0] mcontr_0bit_addr;
wire mcontr_0bit_we;
cmd_deser #(
.ADDR (MCONTR_TOP_0BIT_ADDR),
.ADDR_MASK (MCONTR_TOP_0BIT_ADDR_MASK),
......@@ -680,10 +696,6 @@ wire rst=rst_in; // TODO: decide where toi generate
end
// generate 16-bit data commands (and set defaults to registers)
wire [2:0] mcontr_16bit_addr;
wire [15:0] mcontr_16bit_data;
wire mcontr_16bit_we;
cmd_deser #(
.ADDR (MCONTR_TOP_16BIT_ADDR),
.ADDR_MASK (MCONTR_TOP_16BIT_ADDR_MASK),
......@@ -699,14 +711,12 @@ wire rst=rst_in; // TODO: decide where toi generate
.data (mcontr_16bit_data), // output[31:0]
.we (mcontr_16bit_we) // output
);
wire set_chn_en_w;
wire set_refresh_period_w;
wire set_refresh_address_w;
reg set_refresh_period;
// wire control_status_we; // share with write delay (8-but)?
// wire [7:0] contral_status_data;
assign set_chn_en_w= mcontr_16bit_we && (mcontr_16bit_addr[2:0]==MCONTR_TOP_16BIT_CHN_EN);
assign set_refresh_period_w= mcontr_16bit_we && (mcontr_16bit_addr[2:0]==MCONTR_TOP_16BIT_REFRESH_PERIOD);
assign set_refresh_address_w= mcontr_16bit_we && (mcontr_16bit_addr[2:0]==MCONTR_TOP_16BIT_REFRESH_ADDRESS);
......@@ -758,10 +768,7 @@ wire rst=rst_in; // TODO: decide where toi generate
assign mcontr_enabled=mcontr_en && !mcontr_reset;
//assign sel_refresh_w= refresh_need || (refresh_want && (!cmd_seq_need || !(cmd_seq_full || (cmd_seq_fill && seq_set ))));
assign sel_refresh_w= refresh_need || (refresh_want && !(cmd_seq_need && cmd_seq_full));
//assign pre_run_seq_w= mcontr_enabled && !sequencer_run_busy && !refresh_grant && (cmd_seq_full || refresh_need || refresh_want);
//assign pre_run_seq_w= mcontr_enabled && !sequencer_run_busy && !refresh_grant && !cmd_seq_run && (cmd_seq_full || refresh_want);
assign pre_run_seq_w= mcontr_enabled && !sequencer_run_busy && !cmd_seq_run && (cmd_seq_full || refresh_want);
assign pre_run_chn_w= pre_run_seq_w && !sel_refresh_w;
......@@ -779,22 +786,14 @@ always @ (posedge rst or posedge mclk) begin
if (rst) cmd_wr_chn <= 0;
else if (grant) cmd_wr_chn <= grant_chn;
// if (rst) cmd_seq_fill <= 0;
// else if (!mcontr_enabled || pre_run_chn_w ) cmd_seq_fill <= 0;
// else if (grant) cmd_seq_fill <= 1;
//TODO: Modify,cmd_seq_fill was initially used to see if any sequaence data was written (or PS is used), now it is cmd_seq_set
if (rst) cmd_seq_fill <= 0;
// else if (!mcontr_enabled || seq_wr ) cmd_seq_fill <= 0;
// else if (grant) cmd_seq_fill <= 1;
// else if (!mcontr_enabled || grant ) cmd_seq_fill <= 0;
else if (!mcontr_enabled || seq_set || cmd_seq_full ) cmd_seq_fill <= 0;
// else if (seq_wr) cmd_seq_fill <= 1;
else if (grant) cmd_seq_fill <= 1;
if (rst) cmd_seq_full <= 0;
else if (!mcontr_enabled || pre_run_chn_w ) cmd_seq_full <= 0;
// else if (seq_wr) cmd_seq_full <= 1;
else if (seq_set) cmd_seq_full <= 1; // even with no data
......
memctrl/phy/byte_lane.v
View file @ 05378ee7
......@@ -19,6 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
// minimizing total DQS in delay to match DQ (finedelay stage adds some?)
//`define NOFINEDELAY_DQS 1
module byte_lane #(
......
memctrl/phy/dm_single.v
View file @ 05378ee7
......@@ -20,6 +20,7 @@
*******************************************************************************/
`timescale 1ns/1ps
// ISE 14.7 does not have OBUFT_DCIEN
`include "system_defines.vh"
`define USE_IOBUF 1
module dm_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
......
memctrl/scheduler16.v
View file @ 05378ee7
......@@ -104,7 +104,8 @@ module scheduler16 #(
generate
genvar i1;
for (i1=0;i1<16;i1=i1+1) begin: sched_state_block
always @ (posedge rst or posedge clk) begin
// always @ (posedge rst or posedge clk) begin
always @ (posedge clk) begin
// if (rst) sched_state[width*i1 +: width] <= 0; // not needed?
// else
begin
......
system_defines.vh 0 → 100644
View file @ 05378ee7
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define USE_CMD_ENCOD_TILED_32_RD 1
// It can be used to check different `ifdef branches
//`define XIL_TIMING //Simprim
`define den4096Mb 1
// `define IVERILOG
// defines for memory channels
// chn 0 is read from memory and write to memory
`define def_enable_mem_chn0
`define def_read_mem_chn0
`define def_write_mem_chn0
`undef def_scanline_chn0
`undef def_tiled_chn0
// chn 1 is scanline r+w
`define def_enable_mem_chn1
`define def_read_mem_chn1
`define def_write_mem_chn1
`define def_scanline_chn1
`undef def_tiled_chn1
// chn 2 is tiled r+w
`define def_enable_mem_chn2
`define def_read_mem_chn2
`define def_write_mem_chn2
`undef def_scanline_chn2
`define def_tiled_chn2
// chn 3 is scanline r+w (reuse later)
`define def_enable_mem_chn3
`define def_read_mem_chn3
`define def_write_mem_chn3
`define def_scanline_chn3
`undef def_tiled_chn3
// chn 4 is tiled r+w (reuse later)
`define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_write_mem_chn4
`undef def_scanline_chn4
`define def_tiled_chn4
// chn 5 is disabled
`undef def_enable_mem_chn5
// chn 6 is disabled
`undef def_enable_mem_chn6
// chn 7 is disabled
`undef def_enable_mem_chn7
// chn 8 is disabled
`undef def_enable_mem_chn8
// chn 9 is disabled
`undef def_enable_mem_chn9
// chn 10 is disabled
`undef def_enable_mem_chn10
// chn 11 is disabled
`undef def_enable_mem_chn11
// chn 12 is disabled
`undef def_enable_mem_chn12
// chn 13 is disabled
`undef def_enable_mem_chn13
// chn 14 is disabled
`undef def_enable_mem_chn14
// chn 15 is disabled
`undef def_enable_mem_chn15
`endif
\ No newline at end of file
util_modules/cmd_deser.v
View file @ 05378ee7
......@@ -35,7 +35,6 @@ module cmd_deser#(
output [DATA_WIDTH-1:0] data,
output we
);
generate
if (NUM_CYCLES==1)
cmd_deser_single # (
......@@ -191,7 +190,12 @@ module cmd_deser_multi#(
wire match_low;
wire match_high;
reg [NUM_CYCLES-2:0] sr;
// wire [31:0] debug_addr= ADDR;
// wire [31:0] debug_mask= ADDR_MASK;
// wire [31:0] debug_addr_low= ADDR_LOW;
// wire [31:0] debug_addr_high= ADDR_HIGH;
// wire [31:0] debug_mask_low= ADDR_MASK_LOW;
// wire [31:0] debug_mask_high= ADDR_MASK_HIGH;
assign we=sr[0]; // we_r;
assign match_low= ((ad ^ ADDR_LOW) & (8'hff & ADDR_MASK_LOW)) == 0;
assign match_high= ((ad ^ ADDR_HIGH) & (8'hff & ADDR_MASK_HIGH)) == 0;
......
util_modules/fifo_1cycle.v
View file @ 05378ee7
......@@ -20,7 +20,8 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`define DEBUG_FIFO 1
`include "system_defines.vh"
//`define DEBUG_FIFO 1
module fifo_1cycle
#(
parameter integer DATA_WIDTH=16,
......
util_modules/fifo_same_clock.v
View file @ 05378ee7
......@@ -19,6 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
//`define DEBUG_FIFO 1
module fifo_same_clock
#(
......
util_modules/status_router2.v
View file @ 05378ee7
......@@ -20,7 +20,8 @@
*******************************************************************************/
//TODO: make a 4-input mux too?
`timescale 1ns/1ps
`define DEBUG_FIFO 1
`include "system_defines.vh"
//`define DEBUG_FIFO 1
module status_router2 (
input rst,
input clk,
......@@ -83,7 +84,7 @@ module status_router2 (
else if (|fifo_re) next_chn <= fifo_re[0]; // just to be fair
if (rst) current_chn_r <= 0;
if (set_other_only_w) current_chn_r <= ~current_chn_r;
else if (set_other_only_w) current_chn_r <= ~current_chn_r;
else if (snd_pre_start) current_chn_r <= chn_sel_w;
/// else if (|fifo_nempty && !snd_rest_r) current_chn_r <= chn_sel_w;
//|fifo_nempty && (!snd_rest_r
......
x393.v
View file @ 05378ee7
This diff is collapsed.
x393.xcf 0 → 100644
View file @ 05378ee7
This diff is collapsed.
x393.xdc 0 → 100644
View file @ 05378ee7
#################################################################################
# Filename: x393.xdc
# Date:2014-02-25
# Author: Andrey Filippov
# Description: Elphel x393 camera constraints
#
# Copyright (c) 2015 Elphel, Inc.
# x393.xdc is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# x393.xdc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
# output SDRST, // output SDRST, active low
set_property IOSTANDARD SSTL15 [get_ports {SDRST}]
set_property PACKAGE_PIN J4 [get_ports {SDRST}]
# output SDCLK, // DDR3 clock differential output, positive
set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDCLK}]
set_property PACKAGE_PIN K3 [get_ports {SDCLK}]
# output SDNCLK,// DDR3 clock differential output, negative
set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDNCLK}]
set_property PACKAGE_PIN K2 [get_ports {SDNCLK}]
# output [ADDRESS_NUMBER-1:0] SDA, // output address ports (14:0) for 4Gb device
set_property IOSTANDARD SSTL15 [get_ports {SDA[0]}]
set_property PACKAGE_PIN N3 [get_ports {SDA[0]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[1]}]
set_property PACKAGE_PIN H2 [get_ports {SDA[1]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[2]}]
set_property PACKAGE_PIN M2 [get_ports {SDA[2]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[3]}]
set_property PACKAGE_PIN P5 [get_ports {SDA[3]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[4]}]
set_property PACKAGE_PIN H1 [get_ports {SDA[4]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[5]}]
set_property PACKAGE_PIN M3 [get_ports {SDA[5]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[6]}]
set_property PACKAGE_PIN J1 [get_ports {SDA[6]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[7]}]
set_property PACKAGE_PIN P4 [get_ports {SDA[7]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[8]}]
set_property PACKAGE_PIN K1 [get_ports {SDA[8]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[9]}]
set_property PACKAGE_PIN P3 [get_ports {SDA[9]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[10]}]
set_property PACKAGE_PIN F2 [get_ports {SDA[10]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[11]}]
set_property PACKAGE_PIN H3 [get_ports {SDA[11]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[12]}]
set_property PACKAGE_PIN G3 [get_ports {SDA[12]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[13]}]
set_property PACKAGE_PIN N2 [get_ports {SDA[13]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[14]}]
set_property PACKAGE_PIN J3 [get_ports {SDA[14]}]
# output [2:0] SDBA, // output bank address ports
set_property IOSTANDARD SSTL15 [get_ports {SDBA[0]}]
set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}]
set_property IOSTANDARD SSTL15 [get_ports {SDBA[1]}]
set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}]
set_property IOSTANDARD SSTL15 [get_ports {SDBA[2]}]
set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}]
# output SDWE, // output WE port
set_property IOSTANDARD SSTL15 [get_ports {SDWE}]
set_property PACKAGE_PIN G4 [get_ports {SDWE}]
# output SDRAS, // output RAS port
set_property IOSTANDARD SSTL15 [get_ports {SDRAS}]
set_property PACKAGE_PIN L2 [get_ports {SDRAS}]
# output SDCAS, // output CAS port
set_property IOSTANDARD SSTL15 [get_ports {SDCAS}]
set_property PACKAGE_PIN L1 [get_ports {SDCAS}]
# output SDCKE, // output Clock Enable port
set_property IOSTANDARD SSTL15 [get_ports {SDCKE}]
set_property PACKAGE_PIN E1 [get_ports {SDCKE}]
# output SDODT, // output ODT port
set_property IOSTANDARD SSTL15 [get_ports {SDODT}]
set_property PACKAGE_PIN M7 [get_ports {SDODT}]
#
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[0]}]
set_property PACKAGE_PIN K6 [get_ports {SDD[0]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[1]}]
set_property PACKAGE_PIN L4 [get_ports {SDD[1]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[2]}]
set_property PACKAGE_PIN K7 [get_ports {SDD[2]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[3]}]
set_property PACKAGE_PIN K4 [get_ports {SDD[3]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[4]}]
set_property PACKAGE_PIN L6 [get_ports {SDD[4]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[5]}]
set_property PACKAGE_PIN M4 [get_ports {SDD[5]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[6]}]
set_property PACKAGE_PIN L7 [get_ports {SDD[6]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[7]}]
set_property PACKAGE_PIN N5 [get_ports {SDD[7]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[8]}]
set_property PACKAGE_PIN H5 [get_ports {SDD[8]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[9]}]
set_property PACKAGE_PIN J6 [get_ports {SDD[9]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[10]}]
set_property PACKAGE_PIN G5 [get_ports {SDD[10]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[11]}]
set_property PACKAGE_PIN H6 [get_ports {SDD[11]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[12]}]
set_property PACKAGE_PIN F5 [get_ports {SDD[12]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[13]}]
set_property PACKAGE_PIN F7 [get_ports {SDD[13]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[14]}]
set_property PACKAGE_PIN F4 [get_ports {SDD[14]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[15]}]
set_property PACKAGE_PIN F6 [get_ports {SDD[15]}]
# inout DQSL, // LDQS I/O pad
set_property PACKAGE_PIN N7 [get_ports {DQSL}]
#set_property SLEW FAST [get_ports {DQSL}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSL}]
# inout NDQSL, // ~LDQS I/O pad
set_property PACKAGE_PIN N6 [get_ports {NDQSL}]
#set_property SLEW FAST [get_ports {NDQSL}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSL}]
# inout DQSU, // UDQS I/O pad
set_property PACKAGE_PIN H7 [get_ports {DQSU}]
#set_property SLEW FAST [get_ports {DQSU}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSU}]
# inout NDQSU, // ~UDQS I/O pad
set_property PACKAGE_PIN G7 [get_ports {NDQSU}]
#set_property SLEW FAST [get_ports {NDQSU}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSU}]
# inout SDDML, // LDM I/O pad (actually only output)
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDML}]
set_property IOSTANDARD SSTL15 [get_ports {SDDML}]
set_property PACKAGE_PIN L5 [get_ports {SDDML}]
# inout SDDMU, // UDM I/O pad (actually only output)
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDMU}]
set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
# output DUMMY_TO_KEEP, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {DUMMY_TO_KEEP}]
set_property PACKAGE_PIN E3 [get_ports {DUMMY_TO_KEEP}]
#not yet used, just for debugging
# input MEMCLK, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {MEMCLK}]
set_property PACKAGE_PIN M5 [get_ports {MEMCLK}]
# Global constraints
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property DCI_CASCADE 34 [get_iobanks 35]
set_property INTERNAL_VREF 0.750 [get_iobanks 35]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
x393_testbench01.sav
View file @ 05378ee7
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Wed Feb 25 03:07:13 2015
[*] Fri Feb 27 02:13:30 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150224193905311.lxt"
[dumpfile_mtime] "Wed Feb 25 02:50:26 2015"
[dumpfile_size] 666325841
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150226183110913.lxt"
[dumpfile_mtime] "Fri Feb 27 01:46:16 2015"
[dumpfile_size] 861913910
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 43849000
[size] 1823 1180
[timestart] 27500000
[size] 1823 1173
[pos] 2059 0
*-18.698502 45009323 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-24.698502 91599500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
......@@ -34,10 +34,10 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 260
[signals_width] 428
[sst_width] 373
[signals_width] 465
[sst_expanded] 1
[sst_vpaned_height] 628
[sst_vpaned_height] 627
@800200
-top_simulation
@28
......@@ -1300,9 +1300,8 @@ x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.start_w[0]
@1401200
-enc4mux
@800200
-PS_PIO
@c00200
-PS_PIO
-PS_PIO_STATUS
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.ad[7:0]
......@@ -1420,29 +1419,29 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_set[0]
-PS_PIO_RD
@200
-
@800201
@c00200
-PS_PIO_WR
@23
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.data_out[63:0]
@29
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_clk[0]
@23
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_waddr[9:0]
@29
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page_r[1:0]
@23
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.raddr[6:0]
@29
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rclk[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_set[0]
@1000201
@1401200
-PS_PIO_WR
@200
-
......@@ -1535,7 +1534,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_data[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq[0]
@1000200
@1401200
-PS_PIO
@c00200
-LINEAR_CH1
......@@ -2641,8 +2640,79 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.rst[0]
@1401200
-mmcm_phase_cntr
@c00200
@800200
-memcntrl16_0
@200
-
@800200
-debug_ch2_ch4
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.set_tile_whs_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.tile_cols[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_we[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.match_low[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.match_high[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.stb_d[0]
@c00022
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
(1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
(2)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
(3)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
(4)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
@1401200
-group_end
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_tile_whs_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_cols[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_we[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.match_low[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.match_high[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.stb_d[0]
@c00022
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
(1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
(2)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
(3)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
(4)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
@1401200
-group_end
@1000200
-debug_ch2_ch4
@200
-
@c00200
-cmd_deser_16bit_i
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.addr[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.data[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.stb[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_deser_16bit_i.we[0]
@1401200
-cmd_deser_16bit_i
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn_late[3:0]
@28
......@@ -2727,7 +2797,6 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrefresh[0]
@1000200
-cmd0_buf
@1401200
-memcntrl16_0
@c00200
-scheduler
......
x393_testbench01.tf
View file @ 05378ee7
......@@ -20,28 +20,28 @@
*******************************************************************************/
`timescale 1ns/1ps
`define use200Mhz 1
`define DEBUG_FIFO 1
//`define DEBUG_FIFO 1
`undef WAIT_MRS
`define SET_PER_PIN_DEALYS 1 // set individual (including per-DQ pin delays)
`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
// Disabled already passed test to speedup simulation
//`define TEST_WRITE_LEVELLING 1
//`define TEST_READ_PATTERN 1
`define TEST_WRITE_BLOCK 1
`define TEST_READ_BLOCK 1
`define TESTL_SHORT_SCANLINE 1
//`define TEST_WRITE_BLOCK 1
//`define TEST_READ_BLOCK 1
//`define TESTL_SHORT_SCANLINE 1
`define TEST_SCANLINE_WRITE 1
//`define TEST_SCANLINE_WRITE 1
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
`define TEST_SCANLINE_READ 1
//`define TEST_SCANLINE_READ 1
`define TEST_READ_SHOW 1
//`define TEST_TILED_WRITE 1
`define TEST_TILED_WRITE 1
`define TEST_TILED_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_TILED_READ 1
`define TEST_TILED_READ 1
//`define TEST_TILED_WRITE32 1
//`define TEST_TILED_READ32 1
`define TEST_TILED_WRITE32 1
`define TEST_TILED_READ32 1
module x393_testbench01 #(
`include "includes/x393_parameters.vh"
......
x393_timing.xdc 0 → 100644
View file @ 05378ee7
#################################################################################
# Filename: x393_timing.xdc
# Date:2014-02-25
# Author: Andrey Filippov
# Description: DDR3 controller test with axi constraints
#
# Copyright (c) 2015 Elphel, Inc.
# x393_timing.xdc is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# x393_timing.xdc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
#x393_i/mcntrl393_i/memcntrl16/mcontr_sequencer
#Clock Period Waveform Attributes Sources
#axi_aclk 10.00000 {0.00000 5.00000} P {bufg_axi_aclk_i/O}
#clk_fb 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT}
#sdclk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0}
#clk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1}
#clk_div_pre 5.00000 {0.00000 2.50000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2}
#mclk_pre 5.00000 {1.25000 3.75000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3}
#clkfb_ref 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKFBOUT}
#clk_ref_pre 3.33333 {0.00000 1.66667} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKOUT0}
#Each list contains 2 elements - warning later in DRC
#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
#create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
#Not available initially
#create_generated_clock -name ddr3_sdclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre]
#create_generated_clock -name ddr3_clk [get_netsddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/clk_ref_pre]
# try use first from list - seems that 2 are created from the same name
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/sdclk_pre
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre
# lindex is not supported in xdc
#create_generated_clock -name ddr3_sdclk [lindex [get_nets -hierarchical sdclk_pre] 0 ]
#create_generated_clock -name ddr3_clk [lindex [get_nets -hierarchical clk_pre] 0 ]
#create_generated_clock -name ddr3_clk_div [lindex [get_nets -hierarchical clk_div_pre] 0 ]
#create_generated_clock -name ddr3_mclk [lindex [get_nets -hierarchical mclk_pre] 0 ]
#create_generated_clock -name ddr3_clk_ref [lindex [get_nets -hierarchical clk_ref_pre] 0 ]
##create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre -filter {NAME !~ */pll_base_i*} ]
create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical *sdclk_pre ]
#create_generated_clock -name ddr3_clk [get_nets -hierarchical *clk_pre ]
#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical *clk_div_pre ]
#create_generated_clock -name ddr3_mclk [get_nets -hierarchical *mclk_pre ]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical *clk_ref_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
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