Commit c8904b67 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

added modules, simulating

parent 5034058e

.editor_defines

+2 −1
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  // This file may be used to define same pre-processor macros to be included into each parsed file

  // It can be used to check different `ifdef branches

  `define XIL_TIMING //Simprim 
  //`define XIL_TIMING //Simprim 

  `define IVERILOG
 
 No newline at end of file

.gitignore

+1 −0
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@@ -2,3 +2,4 @@ unisims 
glbl.v

vivado_*

syntax_*

simulation/*

.project

+8 −8
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@@ -51,7 +51,7 @@ 
		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140515155524262.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140520232524498.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>
@@ -61,12 +61,12 @@ 
		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140515155524262.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140520232524498.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140515155524262.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140520232524498.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>
@@ -76,7 +76,7 @@ 
		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140515155524262.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140520232242973.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
@@ -86,7 +86,7 @@ 
		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140515155524262.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140520232524498.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
@@ -96,7 +96,7 @@ 
		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140515155524262.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140520232524498.log</location>

		</link>

		<link>

			<name>vivado_state/eddr3-opt-phys.dcp</name>
@@ -106,7 +106,7 @@ 
		<link>

			<name>vivado_state/eddr3-place.dcp</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140515155524262.dcp</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140520232524498.dcp</location>

		</link>

		<link>

			<name>vivado_state/eddr3-route.dcp</name>
@@ -116,7 +116,7 @@ 
		<link>

			<name>vivado_state/eddr3-synth.dcp</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140515155524262.dcp</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140520204515091.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

.settings/com.elphel.vdt.FPGA_project.prefs

+4 −2
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FPGA_project_2_ImplementationTopFile=phy/test_phy_top_01.v

FPGA_project_0_SimulationTopFile=ddrc_test01_testbench.tf

FPGA_project_1_SimulationTopModule=ddrc_test01_testbench

FPGA_project_2_ImplementationTopFile=ddrc_test01.v

FPGA_project_4_part=xc7z030fbg484-2

com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->

com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->

eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoSynthesis.prefs

+3 −2
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VivadoSynthesis_102_ConstraintsFiles=phy/test_phy_top_01.xdc<-@\#\#@->

com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->

VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->

VivadoSynthesis_95_ShowInfo=false

com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->

eclipse.preferences.version=1