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Elphel
x393
Commits
ad0351ef
Commit
ad0351ef
authored
Feb 22, 2015
by
Andrey Filippov
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re-organized top structure
parent
f35bb39d
Changes
26
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26 changed files
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3396 additions
and
1842 deletions
+3396
-1842
.editor_defines.vh
.editor_defines.vh
+30
-21
address_map.txt
address_map.txt
+4
-3
axibram_write.v
axi/axibram_write.v
+1
-0
x393_parameters.vh
includes/x393_parameters.vh
+25
-14
x393_tasks01.vh
includes/x393_tasks01.vh
+2
-0
x393_tasks_mcntrl_buffers.vh
includes/x393_tasks_mcntrl_buffers.vh
+11
-6
x393_tasks_mcntrl_en_dis_priority.vh
includes/x393_tasks_mcntrl_en_dis_priority.vh
+15
-0
x393_tasks_status.vh
includes/x393_tasks_status.vh
+6
-5
cmd_encod_4mux.v
memctrl/cmd_encod_4mux.v
+84
-0
cmd_encod_linear_mux.v
memctrl/cmd_encod_linear_mux.v
+442
-117
cmd_encod_linear_rw.v
memctrl/cmd_encod_linear_rw.v
+111
-0
cmd_encod_tiled_32_rw.v
memctrl/cmd_encod_tiled_32_rw.v
+118
-0
cmd_encod_tiled_mux.v
memctrl/cmd_encod_tiled_mux.v
+486
-121
cmd_encod_tiled_rw.v
memctrl/cmd_encod_tiled_rw.v
+117
-0
mcntrl393.v
memctrl/mcntrl393.v
+754
-623
mcntrl393_test01.v
memctrl/mcntrl393_test01.v
+74
-72
mcntrl_linear_rw.v
memctrl/mcntrl_linear_rw.v
+44
-40
mcntrl_ps_pio.v
memctrl/mcntrl_ps_pio.v
+77
-88
mcntrl_tiled_rw.v
memctrl/mcntrl_tiled_rw.v
+53
-32
memctrl16.v
memctrl/memctrl16.v
+231
-269
mcontr_sequencer.v
memctrl/phy/mcontr_sequencer.v
+19
-3
mcont_common_chnbuf_reg.v
util_modules/mcont_common_chnbuf_reg.v
+8
-3
mcont_from_chnbuf_reg.v
util_modules/mcont_from_chnbuf_reg.v
+8
-4
x393.v
x393.v
+59
-41
x393_testbench01.sav
x393_testbench01.sav
+65
-100
x393_testbench01.tf
x393_testbench01.tf
+552
-280
No files found.
.editor_defines.vh
View file @
ad0351ef
...
...
@@ -2,41 +2,50 @@
// TODO: Fix VDT - without IVERILOG defined, closure does not include modules needed for Icarus
`define IVERILOG 1
`undef DEBUG_FIFO
`define USE_CMD_ENCOD_TILED_32_RD 1
// It can be used to check different `ifdef branches
//`define XIL_TIMING //Simprim
`define den4096Mb 1
// `define IVERILOG
// defines for memory channels
// chn 0 is read from memory
// chn 0 is read from memory
and write to memory
`define def_enable_mem_chn0
`define def_read_mem_chn0
`define def_write_mem_chn0
`undef def_scanline_chn0
`undef def_tiled_chn0
// chn 1 is write to memory
`define def_enable_mem_chn1
`undef def_read_mem_chn1
`undef def_scanline_chn1
// chn 1 is scanline r+w
`define def_enable_mem_chn1
`define def_read_mem_chn1
`define def_write_mem_chn1
`define def_scanline_chn1
`undef def_tiled_chn1
// chn 2 is read from memory
`define def_enable_mem_chn2
`define def_read_mem_chn2
`define def_scanline_chn2
// chn 2 is tiled r+w
`define def_enable_mem_chn2
`define def_read_mem_chn2
`define def_write_mem_chn2
`undef def_scanline_chn2
`define def_tiled_chn2
// chn 3 is write to memory
`define def_enable_mem_chn3
`undef def_read_mem_chn3
`define def_scanline_chn3
// chn 3 is scanline r+w (reuse later)
`define def_enable_mem_chn3
`define def_read_mem_chn3
`define def_write_mem_chn3
`define def_scanline_chn3
`undef def_tiled_chn3
// chn 4 is enabled
`define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_tiled_chn4
// chn 4 is tiled r+w (reuse later)
`define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_write_mem_chn4
`undef def_scanline_chn4
`define def_tiled_chn4
// chn 5 is enabled
`define def_enable_mem_chn5
`undef def_read_mem_chn5
`define def_tiled_chn5
// chn 5 is disabled
`undef def_enable_mem_chn5
// chn 6 is disabled
`undef def_enable_mem_chn6
...
...
address_map.txt
View file @
ad0351ef
...
...
@@ -142,9 +142,10 @@
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0,//8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1,//8 or less bits: status register address to use for memory controller
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR='h4,
parameter MCNTRL_TILED_STATUS_REG_CHN2_ADDR= 'h5,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h6,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h7,
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
...
...
axi/axibram_write.v
View file @
ad0351ef
...
...
@@ -20,6 +20,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
//`define DEBUG_FIFO 1
`undef
DEBUG_FIFO
module
axibram_write
#(
parameter
ADDRESS_BITS
=
10
// number of memory address bits
)(
...
...
includes/x393_parameters.vh
View file @
ad0351ef
...
...
@@ -23,11 +23,20 @@
parameter MCONTR_CMD_WR_ADDR = 'h0000, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h0400, // AXI read address from buffer 0 (PS sequence, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
// parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
// parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
// parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
// parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
// parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
parameter MCONTR_BUF1_RD_ADDR = 'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write)
parameter MCONTR_BUF2_RD_ADDR = 'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
parameter MCONTR_BUF2_WR_ADDR = 'h0c00, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
parameter MCONTR_BUF3_RD_ADDR = 'h0800, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF
5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline
, memory write)
parameter MCONTR_BUF
4_WR_ADDR = 'h0c00, // AXI write address to buffer 4 (PL sequence, tiles
, memory write)
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
...
...
@@ -181,7 +190,7 @@
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_SCANLINE_CHN
2
_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN
1
_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
...
...
@@ -194,17 +203,18 @@
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_CHN
2
_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h
5
,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN
1
_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h
6
,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN2_ADDR= 'h140,
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_CHN5_ADDR= 'h150,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
...
...
@@ -217,7 +227,8 @@
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WHS= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
parameter MCNTRL_TILED_STATUS_REG_CHN2_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h7,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
...
...
@@ -228,16 +239,16 @@
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h3f0,
parameter MCNTRL_TEST01_CHN1_MODE= 'h2, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN1_STATUS_CNTRL= 'h3, // control status reporting for channel 5
parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_CHN5_MODE= 'ha, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN5_STATUS_CNTRL= 'hb, // control status reporting for channel 5
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN1_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f // status/readback register for channel 4
\ No newline at end of file
includes/x393_tasks01.vh
View file @
ad0351ef
...
...
@@ -20,8 +20,10 @@
*******************************************************************************/
// Low-level tasks
// alternative way to check for empty read queue (without a separate counter)
task write_contol_register;
input [29:0] reg_addr;
// input integer reg_addr;
input [31:0] data;
begin
axi_write_single_w(CONTROL_ADDR+reg_addr, data);
...
...
includes/x393_tasks_mcntrl_buffers.vh
View file @
ad0351ef
...
...
@@ -31,11 +31,11 @@ task write_block_scanline_chn; // S uppressThisWarning VEditor : may be unused
begin
$display("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%d @%t", chn, page, startX, startY,num_words, $time);
case (chn)
1: start_addr=MCONTR_BUF
1
_WR_ADDR + (page << 8);
1: start_addr=MCONTR_BUF
0
_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for write_block_scanline_chn = %d @%t", chn, $time);
start_addr = MCONTR_BUF
1
_WR_ADDR+ (page << 8);
start_addr = MCONTR_BUF
0
_WR_ADDR+ (page << 8);
end
endcase
// write_block_incremtal (start_addr, num_words, (startX<<2) + (startY<<16)); // 1 of startX is 8x16 bit, 16 bytes or 4 32-bit words
...
...
@@ -84,12 +84,14 @@ task write_block_buf_chn; // S uppressThisWarning VEditor : may be unused
reg [29:0] start_addr;
begin
case (chn)
0: start_addr=MCONTR_BUF0_WR_ADDR + (page << 8);
1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
2: start_addr=MCONTR_BUF2_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
5: start_addr=MCONTR_BUF5
_WR_ADDR + (page << 8);
4: start_addr=MCONTR_BUF4
_WR_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for write buffer = %d @%t", chn, $time);
start_addr = MCONTR_BUF
1
_WR_ADDR+ (page << 8);
start_addr = MCONTR_BUF
0
_WR_ADDR+ (page << 8);
end
endcase
write_block_buf (start_addr, num_words);
...
...
@@ -106,7 +108,7 @@ task write_block_buf;
axi_write_addr_data(
i, // id
{start_word_address,2'b0}+( i << 2),
// (MCONTR_BUF
1
_WR_ADDR + (page <<8)+ i) << 2, // addr
// (MCONTR_BUF
0
_WR_ADDR + (page <<8)+ i) << 2, // addr
i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24),
4'hf, // len
1, // burst type - increment
...
...
@@ -131,7 +133,8 @@ endtask
// read memory
task read_block_buf_chn; // S uppressThisWarning VEditor : may be unused
input integer chn; // buffer channel
// input integer chn; // buffer channel
input [3:0] chn; // buffer channel
input [1:0] page;
input integer num_read; // number of words to read (will be rounded up to multiple of 16)
input wait_done;
...
...
@@ -139,7 +142,9 @@ task read_block_buf_chn; // S uppressThisWarning VEditor : may be unused
begin
case (chn)
0: start_addr=MCONTR_BUF0_RD_ADDR + (page << 8);
1: start_addr=MCONTR_BUF1_RD_ADDR + (page << 8);
2: start_addr=MCONTR_BUF2_RD_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_RD_ADDR + (page << 8);
4: start_addr=MCONTR_BUF4_RD_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for read buffer = %d @%t", chn, $time);
...
...
includes/x393_tasks_mcntrl_en_dis_priority.vh
View file @
ad0351ef
...
...
@@ -57,10 +57,25 @@ endtask
task enable_memcntrl_channels;
input [15:0] chnen; // bit-per-channel, 1 - enable;
begin
ENABLED_CHANNELS = chnen; // currently enabled memory channels
write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,chnen});
end
endtask
task enable_memcntrl_en_dis;
input [3:0] chn;
input en;
begin
if (en) begin
ENABLED_CHANNELS = ENABLED_CHANNELS | (1<<chn);
end else begin
ENABLED_CHANNELS = ENABLED_CHANNELS & ~(1<<chn);
end
write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,ENABLED_CHANNELS});
end
endtask
task configure_channel_priority;
input [ 3:0] chn;
input [15:0] priority; // (higher is more important)
...
...
includes/x393_tasks_status.vh
View file @
ad0351ef
...
...
@@ -60,13 +60,14 @@ endtask
read_and_wait_status (MCONTR_PHY_STATUS_REG_ADDR);
read_and_wait_status (MCONTR_TOP_STATUS_REG_ADDR);
read_and_wait_status (MCNTRL_PS_STATUS_REG_ADDR);
read_and_wait_status (MCNTRL_SCANLINE_STATUS_REG_CHN
2
_ADDR);
read_and_wait_status (MCNTRL_SCANLINE_STATUS_REG_CHN
1
_ADDR);
read_and_wait_status (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR);
read_and_wait_status (MCNTRL_TILED_STATUS_REG_CHN2_ADDR);
read_and_wait_status (MCNTRL_TILED_STATUS_REG_CHN4_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN1_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN5_ADDR);
end
endtask
...
...
@@ -86,14 +87,14 @@ endtask
program_status (MCONTR_PHY_16BIT_ADDR, MCONTR_PHY_STATUS_CNTRL, mode,seq_num); //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
program_status (MCONTR_TOP_16BIT_ADDR, MCONTR_TOP_16BIT_STATUS_CNTRL, mode,seq_num); //MCONTR_TOP_STATUS_REG_ADDR= 'h1,
program_status (MCNTRL_PS_ADDR, MCNTRL_PS_STATUS_CNTRL, mode,seq_num); //MCNTRL_PS_STATUS_REG_ADDR= 'h2,
program_status (MCNTRL_SCANLINE_CHN
2
_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
program_status (MCNTRL_SCANLINE_CHN
1
_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
program_status (MCNTRL_TILED_CHN2_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TILED_CHN4_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_T
ILED_CHN5_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6
,
program_status (MCNTRL_T
EST01_ADDR, MCNTRL_TEST01_CHN1_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c
,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN5_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f,
end
endtask
...
...
memctrl/cmd_encod_4mux.v
0 → 100644
View file @
ad0351ef
/*******************************************************************************
* Module: cmd_encod_4mux
* Date:2015-02-21
* Author: andrey
* Description: 4-to-1 mux to cmbine memory sequences sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmd_encod_4mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmd_encod_4mux.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
cmd_encod_4mux
(
input
rst
,
input
clk
,
input
start0
,
// this channel was started
input
[
31
:
0
]
enc_cmd0
,
// encoded commnad
input
enc_wr0
,
// write encoded command
input
enc_done0
,
// encoding finished
input
start1
,
// this channel was started
input
[
31
:
0
]
enc_cmd1
,
// encoded commnad
input
enc_wr1
,
// write encoded command
input
enc_done1
,
// encoding finished
input
start2
,
// this channel was started
input
[
31
:
0
]
enc_cmd2
,
// encoded commnad
input
enc_wr2
,
// write encoded command
input
enc_done2
,
// encoding finished
input
start3
,
// this channel was started
input
[
31
:
0
]
enc_cmd3
,
// encoded commnad
input
enc_wr3
,
// write encoded command
input
enc_done3
,
// encoding finished
output
reg
start
,
// combined output was started (1 clk from |start*)
output
reg
[
31
:
0
]
enc_cmd
,
// encoded commnad
output
reg
enc_wr
,
// write encoded command
output
reg
enc_done
// encoding finished
)
;
reg
[
3
:
0
]
select
;
wire
start_w
=
start0
|
start1
|
start2
|
start3
;
always
@
(
posedge
rst
or
posedge
clk
)
begin
if
(
rst
)
start
<=
0
;
else
start
<=
start_w
;
if
(
rst
)
select
<=
0
;
else
if
(
start_w
)
select
<={
// normally should be no simultaneous starts, so priority is not needed
start3
&
~
start2
&
~
start1
&
~
start0
,
start2
&
~
start1
&
~
start0
,
start1
&
~
start0
,
start0
};
end
always
@
(
posedge
clk
)
begin
enc_cmd
<=
(
{
32
{
select
[
0
]
}}
&
enc_cmd0
)
|
(
{
32
{
select
[
1
]
}}
&
enc_cmd1
)
|
(
{
32
{
select
[
2
]
}}
&
enc_cmd2
)
|
(
{
32
{
select
[
3
]
}}
&
enc_cmd3
)
;
enc_wr
<=
(
select
[
0
]
&
enc_wr0
)
|
(
select
[
1
]
&
enc_wr1
)
|
(
select
[
2
]
&
enc_wr2
)
|
(
select
[
3
]
&
enc_wr3
)
;
enc_done
<=
(
select
[
0
]
&
enc_done0
)
|
(
select
[
1
]
&
enc_done1
)
|
(
select
[
2
]
&
enc_done2
)
|
(
select
[
3
]
&
enc_done3
)
;
end
endmodule
memctrl/cmd_encod_linear_mux.v
View file @
ad0351ef
This diff is collapsed.
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memctrl/cmd_encod_linear_rw.v
0 → 100644
View file @
ad0351ef
/*******************************************************************************
* Module: cmd_encod_linear_rw
* Date:2015-02-21
* Author: andrey
* Description: Combining 2 modules:cmd_encod_linear_rd and cmd_encod_linear_wr
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmd_encod_linear_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmd_encod_linear_rw.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
cmd_encod_linear_rw
#(
// parameter BASEADDR = 0,
parameter
ADDRESS_NUMBER
=
15
,
parameter
COLADDR_NUMBER
=
10
,
parameter
NUM_XFER_BITS
=
6
,
// number of bits to specify transfer length
parameter
CMD_PAUSE_BITS
=
10
,
parameter
CMD_DONE_BIT
=
10
// VDT BUG: CMD_DONE_BIT is used in a function call parameter!
)
(
input
rst
,
input
clk
,
// programming interface
// input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
// input cmd_stb, // strobe (with first byte) for the command a/d
input
[
2
:
0
]
bank_in
,
// bank address
input
[
ADDRESS_NUMBER
-
1
:
0
]
row_in
,
// memory row
input
[
COLADDR_NUMBER
-
4
:
0
]
start_col
,
// start memory column in 8-bursts
input
[
NUM_XFER_BITS
-
1
:
0
]
num128_in
,
// number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input
skip_next_page_in
,
// do not reset external buffer (continue)
input
start_rd
,
// start generating commands by cmd_encod_linear_rd
input
start_wr
,
// start generating commands by cmd_encod_linear_wr
output
reg
start
,
// this channel was started (1 clk from start_rd || start_wr
output
reg
[
31
:
0
]
enc_cmd
,
// encoded commnad
output
reg
enc_wr
,
// write encoded command
output
reg
enc_done
// encoding finished
)
;
wire
[
31
:
0
]
enc_cmd_rd
;
// encoded commnad
wire
enc_wr_rd
;
// write encoded command
wire
enc_done_rd
;
// encoding finished
wire
[
31
:
0
]
enc_cmd_wr
;
// encoded commnad
wire
enc_wr_wr
;
// write encoded command
wire
enc_done_wr
;
// encoding finished
reg
select_wr
;
cmd_encod_linear_rd
#(
.
ADDRESS_NUMBER
(
ADDRESS_NUMBER
)
,
.
COLADDR_NUMBER
(
COLADDR_NUMBER
)
,
.
NUM_XFER_BITS
(
NUM_XFER_BITS
)
,
.
CMD_PAUSE_BITS
(
CMD_PAUSE_BITS
)
,
.
CMD_DONE_BIT
(
CMD_DONE_BIT
)
)
cmd_encod_linear_rd_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
bank_in
(
bank_in
)
,
// input[2:0]
.
row_in
(
row_in
)
,
// input[14:0]
.
start_col
(
start_col
)
,
// input[6:0]
.
num128_in
(
num128_in
)
,
// input[5:0]
.
skip_next_page_in
(
skip_next_page_in
)
,
// input
.
start
(
start_rd
)
,
// input
.
enc_cmd
(
enc_cmd_rd
)
,
// output[31:0] reg
.
enc_wr
(
enc_wr_rd
)
,
// output reg
.
enc_done
(
enc_done_rd
)
// output reg
)
;
cmd_encod_linear_wr
#(
.
ADDRESS_NUMBER
(
ADDRESS_NUMBER
)
,
.
COLADDR_NUMBER
(
COLADDR_NUMBER
)
,
.
NUM_XFER_BITS
(
NUM_XFER_BITS
)
,
.
CMD_PAUSE_BITS
(
CMD_PAUSE_BITS
)
,
.
CMD_DONE_BIT
(
CMD_DONE_BIT
)
)
cmd_encod_linear_wr_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
bank_in
(
bank_in
)
,
// input[2:0]
.
row_in
(
row_in
)
,
// input[14:0]
.
start_col
(
start_col
)
,
// input[6:0]
.
num128_in
(
num128_in
)
,
// input[5:0]
.
skip_next_page_in
(
skip_next_page_in
)
,
// input
.
start
(
start_wr
)
,
// input
.
enc_cmd
(
enc_cmd_wr
)
,
// output[31:0] reg
.
enc_wr
(
enc_wr_wr
)
,
// output reg
.
enc_done
(
enc_done_wr
)
// output reg
)
;
always
@
(
posedge
rst
or
posedge
clk
)
begin
if
(
rst
)
start
<=
0
;
else
start
<=
start_rd
||
start_wr
;
if
(
rst
)
select_wr
<=
0
;
else
if
(
start_rd
)
select_wr
<=
0
;
else
if
(
start_wr
)
select_wr
<=
1
;
end
always
@
(
posedge
clk
)
begin
enc_cmd
<=
select_wr
?
enc_cmd_wr
:
enc_cmd_rd
;
enc_wr
<=
select_wr
?
enc_wr_wr
:
enc_wr_rd
;
enc_done
<=
select_wr
?
enc_done_wr
:
enc_done_rd
;
end
endmodule
memctrl/cmd_encod_tiled_32_rw.v
0 → 100644
View file @
ad0351ef
/*******************************************************************************
* Module: cmd_encod_tiled_32_rw
* Date:2015-02-21
* Author: andrey
* Description: Combines cmd_encod_tiled_32_rd and cmd_encod_tiled_32_wr modules
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmd_encod_tiled_32_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmd_encod_tiled_32_rw.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
cmd_encod_tiled_32_rw
#(
parameter
ADDRESS_NUMBER
=
15
,
parameter
COLADDR_NUMBER
=
10
,
parameter
CMD_PAUSE_BITS
=
10
,
parameter
CMD_DONE_BIT
=
10
,
// VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter
FRAME_WIDTH_BITS
=
13
// Maximal frame width - 8-word (16 bytes) bursts
)
(
input
rst
,
input
clk
,
// programming interface
input
[
2
:
0
]
start_bank
,
// bank address
input
[
ADDRESS_NUMBER
-
1
:
0
]
start_row
,
// memory row
input
[
COLADDR_NUMBER
-
4
:
0
]
start_col
,
// start memory column in 8-bit bursts
input
[
FRAME_WIDTH_BITS
:
0
]
rowcol_inc_in
,
// increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input
[
5
:
0
]
num_rows_in_m1
,
// number of rows to read minus 1
input
[
5
:
0
]
num_cols_in_m1
,
// number of 16-pixel columns to read (rows first, then columns) - 1
input
keep_open_in
,
// keep banks open (for <=8 banks only
input
skip_next_page_in
,
// do not reset external buffer (continue)
input
start_rd
,
// start generating commands by cmd_encod_linear_rd
input
start_wr
,
// start generating commands by cmd_encod_linear_wr
output
reg
start
,
// this channel was started (1 clk from start_rd || start_wr
output
reg
[
31
:
0
]
enc_cmd
,
// encoded commnad
output
reg
enc_wr
,
// write encoded command
output
reg
enc_done
// encoding finished
)
;
wire
[
31
:
0
]
enc_cmd_rd
;
// encoded commnad
wire
enc_wr_rd
;
// write encoded command
wire
enc_done_rd
;
// encoding finished
wire
[
31
:
0
]
enc_cmd_wr
;
// encoded commnad
wire
enc_wr_wr
;
// write encoded command
wire
enc_done_wr
;
// encoding finished
reg
select_wr
;
cmd_encod_tiled_32_rd
#(
.
ADDRESS_NUMBER
(
ADDRESS_NUMBER
)
,
.
COLADDR_NUMBER
(
COLADDR_NUMBER
)
,
.
CMD_PAUSE_BITS
(
CMD_PAUSE_BITS
)
,
.
CMD_DONE_BIT
(
CMD_DONE_BIT
)
)
cmd_encod_tiled_rd_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
start_bank
(
start_bank
)
,
// input[2:0]
.
start_row
(
start_row
)
,
// input[14:0]
.
start_col
(
start_col
)
,
// input[6:0]
.
rowcol_inc_in
(
rowcol_inc_in
)
,
// input[13:0] // [21:0]
.
num_rows_in_m1
(
num_rows_in_m1
)
,
// input[5:0]
.
num_cols_in_m1
(
num_cols_in_m1
)
,
// input[5:0]
.
keep_open_in
(
keep_open_in
)
,
// input
.
skip_next_page_in
(
skip_next_page_in
)
,
// input
.
start
(
start_rd
)
,
// input
.
enc_cmd
(
enc_cmd_rd
)
,
// output[31:0] reg
.
enc_wr
(
enc_wr_rd
)
,
// output reg
.
enc_done
(
enc_done_rd
)
// output reg
)
;
cmd_encod_tiled_32_wr
#(
.
ADDRESS_NUMBER
(
ADDRESS_NUMBER
)
,
.
COLADDR_NUMBER
(
COLADDR_NUMBER
)
,
.
CMD_PAUSE_BITS
(
CMD_PAUSE_BITS
)
,
.
CMD_DONE_BIT
(
CMD_DONE_BIT
)
)
cmd_encod_tiled_wr_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
start_bank
(
start_bank
)
,
// input[2:0]
.
start_row
(
start_row
)
,
// input[14:0]
.
start_col
(
start_col
)
,
// input[6:0]
.
rowcol_inc_in
(
rowcol_inc_in
)
,
// input[13:0] // [21:0]
.
num_rows_in_m1
(
num_rows_in_m1
)
,
// input[5:0]
.
num_cols_in_m1
(
num_cols_in_m1
)
,
// input[5:0]
.
keep_open_in
(
keep_open_in
)
,
// input
.
skip_next_page_in
(
skip_next_page_in
)
,
// input
.
start
(
start_wr
)
,
// input
.
enc_cmd
(
enc_cmd_wr
)
,
// output[31:0] reg
.
enc_wr
(
enc_wr_wr
)
,
// output reg
.
enc_done
(
enc_done_wr
)
// output reg
)
;
always
@
(
posedge
rst
or
posedge
clk
)
begin
if
(
rst
)
start
<=
0
;
else
start
<=
start_rd
||
start_wr
;
if
(
rst
)
select_wr
<=
0
;
else
if
(
start_rd
)
select_wr
<=
0
;
else
if
(
start_wr
)
select_wr
<=
1
;
end
always
@
(
posedge
clk
)
begin
enc_cmd
<=
select_wr
?
enc_cmd_wr
:
enc_cmd_rd
;
enc_wr
<=
select_wr
?
enc_wr_wr
:
enc_wr_rd
;
enc_done
<=
select_wr
?
enc_done_wr
:
enc_done_rd
;
end
endmodule
memctrl/cmd_encod_tiled_mux.v
View file @
ad0351ef
This diff is collapsed.
Click to expand it.
memctrl/cmd_encod_tiled_rw.v
0 → 100644
View file @
ad0351ef
/*******************************************************************************
* Module: cmd_encod_tiled_rw
* Date:2015-02-21
* Author: andrey
* Description: Combines cmd_encod_tiled_rd and cmd_encod_tiled_wr modules
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmd_encod_tiled_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmd_encod_tiled_rw.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
cmd_encod_tiled_rw
#(
parameter
ADDRESS_NUMBER
=
15
,
parameter
COLADDR_NUMBER
=
10
,
parameter
CMD_PAUSE_BITS
=
10
,
parameter
CMD_DONE_BIT
=
10
,
// VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter
FRAME_WIDTH_BITS
=
13
// Maximal frame width - 8-word (16 bytes) bursts
)
(
input
rst
,
input
clk
,
// programming interface
input
[
2
:
0
]
start_bank
,
// bank address
input
[
ADDRESS_NUMBER
-
1
:
0
]
start_row
,
// memory row
input
[
COLADDR_NUMBER
-
4
:
0
]
start_col
,
// start memory column in 8-bit bursts
input
[
FRAME_WIDTH_BITS
:
0
]
rowcol_inc_in
,
// increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input
[
5
:
0
]
num_rows_in_m1
,
// number of rows to read minus 1
input
[
5
:
0
]
num_cols_in_m1
,
// number of 16-pixel columns to read (rows first, then columns) - 1
input
keep_open_in
,
// keep banks open (for <=8 banks only
input
skip_next_page_in
,
// do not reset external buffer (continue)
input
start_rd
,
// start generating commands by cmd_encod_linear_rd
input
start_wr
,
// start generating commands by cmd_encod_linear_wr
output
reg
start
,
// this channel was started (1 clk from start_rd || start_wr
output
reg
[
31
:
0
]
enc_cmd
,
// encoded commnad
output
reg
enc_wr
,
// write encoded command
output
reg
enc_done
// encoding finished
)
;
wire
[
31
:
0
]
enc_cmd_rd
;
// encoded commnad
wire
enc_wr_rd
;
// write encoded command
wire
enc_done_rd
;
// encoding finished
wire
[
31
:
0
]
enc_cmd_wr
;
// encoded commnad
wire
enc_wr_wr
;
// write encoded command
wire
enc_done_wr
;
// encoding finished
reg
select_wr
;
cmd_encod_tiled_rd
#(
.
ADDRESS_NUMBER
(
ADDRESS_NUMBER
)
,
.
COLADDR_NUMBER
(
COLADDR_NUMBER
)
,
.
CMD_PAUSE_BITS
(
CMD_PAUSE_BITS
)
,
.
CMD_DONE_BIT
(
CMD_DONE_BIT
)
)
cmd_encod_tiled_rd_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
start_bank
(
start_bank
)
,
// input[2:0]
.
start_row
(
start_row
)
,
// input[14:0]
.
start_col
(
start_col
)
,
// input[6:0]
.
rowcol_inc_in
(
rowcol_inc_in
)
,
// input[13:0] // [21:0]
.
num_rows_in_m1
(
num_rows_in_m1
)
,
// input[5:0]
.
num_cols_in_m1
(
num_cols_in_m1
)
,
// input[5:0]
.
keep_open_in
(
keep_open_in
)
,
// input
.
skip_next_page_in
(
skip_next_page_in
)
,
// input
.
start
(
start_rd
)
,
// input
.
enc_cmd
(
enc_cmd_rd
)
,
// output[31:0] reg
.
enc_wr
(
enc_wr_rd
)
,
// output reg
.
enc_done
(
enc_done_rd
)
// output reg
)
;
cmd_encod_tiled_wr
#(
.
ADDRESS_NUMBER
(
ADDRESS_NUMBER
)
,
.
COLADDR_NUMBER
(
COLADDR_NUMBER
)
,
.
CMD_PAUSE_BITS
(
CMD_PAUSE_BITS
)
,
.
CMD_DONE_BIT
(
CMD_DONE_BIT
)
)
cmd_encod_tiled_wr_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
start_bank
(
start_bank
)
,
// input[2:0]
.
start_row
(
start_row
)
,
// input[14:0]
.
start_col
(
start_col
)
,
// input[6:0]
.
rowcol_inc_in
(
rowcol_inc_in
)
,
// input[13:0] // [21:0]
.
num_rows_in_m1
(
num_rows_in_m1
)
,
// input[5:0]
.
num_cols_in_m1
(
num_cols_in_m1
)
,
// input[5:0]
.
keep_open_in
(
keep_open_in
)
,
// input
.
skip_next_page_in
(
skip_next_page_in
)
,
// input
.
start
(
start_wr
)
,
// input
.
enc_cmd
(
enc_cmd_wr
)
,
// output[31:0] reg
.
enc_wr
(
enc_wr_wr
)
,
// output reg
.
enc_done
(
enc_done_wr
)
// output reg
)
;
always
@
(
posedge
rst
or
posedge
clk
)
begin