Commits · db53f38f89bceebed439f396cea9425ae1bfa020 · Elphel / x393

03 Nov, 2015 1 commit
- testing and simulating, improving timing · db53f38f
  Andrey Filippov authored 9 years ago
  
  db53f38f
22 Oct, 2015 1 commit
- modifying histograms module to avoid use of the double pixel frequency clock · cfdcac60
  Andrey Filippov authored 9 years ago
  
  cfdcac60
18 Oct, 2015 1 commit
- simulating/bug fixing · 75f18826
  Andrey Filippov authored 9 years ago
  
  75f18826
16 Oct, 2015 1 commit
- more on hispi code · ae549ed4
  Andrey Filippov authored 9 years ago
  
  ae549ed4
23 Aug, 2015 1 commit
- simulating multiple simultanerous sesnor/compressor channels · 225fccd0
  Andrey Filippov authored 9 years ago
  
  225fccd0
19 Aug, 2015 1 commit

Finished simulation/testing of a single-channel... · a500d197

Andrey Filippov authored 9 years ago

Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation

a500d197

15 Aug, 2015 1 commit
- continiuing co-simulation with 353 code, verified martching data to the compressor input · de641880
  Andrey Filippov authored 9 years ago
  
  de641880
01 Aug, 2015 1 commit
- making previous simulation tasks run on the full x393 code · 3af47156
  Andrey Filippov authored 9 years ago
  
  3af47156
30 Jul, 2015 1 commit
- copied CVC-related changes from master branch · 912f47b4
  Andrey Filippov authored 9 years ago
  
  912f47b4
25 Jul, 2015 2 commits
- Simulator-dependent defines added · f3df44ab
  Alexey Grebenkin authored 9 years ago
  
  f3df44ab
- CVC defines set, part2 · dc5c25e2
  Alexey Grebenkin authored 9 years ago
  
  dc5c25e2
24 Jul, 2015 1 commit
- adjusting constraint attributes in the source · 64ff56ce
  Andrey Filippov authored 9 years ago
  
  64ff56ce
23 Jul, 2015 3 commits
- added ifndef wrappers for attributes · e19ac0d8
  Alexey Grebenkin authored 9 years ago
  
  e19ac0d8
- made tools run successfully, no timing errors · 8b0a0f11
  Andrey Filippov authored 9 years ago
  
  8b0a0f11
- Added wrapper for latch primitive as tools do not recognise global clock as G if inferred · 8e80a731
  Andrey Filippov authored 9 years ago
  
  8e80a731
22 Jul, 2015 1 commit
- More editing, trying to run Xilinx tools · 0cfebd24
  Andrey Filippov authored 9 years ago
  
  0cfebd24
20 Jul, 2015 2 commits
- continue fighting with Vivado tools · 0524b747
  Andrey Filippov authored 9 years ago
  
  0524b747
- fixed a bug caused by a counter-intuitive CLKINSEL in MMCME2_ADV · f026775f
  Andrey Filippov authored 9 years ago
  
  f026775f
19 Jul, 2015 1 commit
- working on synthesis errors · 48b08174
  Andrey Filippov authored 9 years ago
  
  48b08174
18 Jul, 2015 2 commits
- Trying synthesis, fixing revealed bugs · bf7c096d
  Andrey Filippov authored 9 years ago
  
  bf7c096d
- Implemented clock management, entered pads physical constraints · 16513305
  Andrey Filippov authored 9 years ago
  
  16513305
12 Jul, 2015 1 commit
- Changed 'author' to full name · 41babf8a
  Andrey Filippov authored 9 years ago
  
  41babf8a
06 Jul, 2015 1 commit
- Fixed teplate error in the headers · 93e8aa42
  Andrey Filippov authored 9 years ago
  
  93e8aa42
16 Jun, 2015 1 commit
- ported xdct module, added to compressor chain · 3bccc0bb
  Andrey Filippov authored 9 years ago
  
  3bccc0bb
13 Jun, 2015 1 commit
- Working on compressors interaction with external memory buffer · 8b1599eb
  Andrey Filippov authored 9 years ago
  
  8b1599eb
07 Jun, 2015 1 commit
- Fixing error in comments · 1f464a83
  Andrey Filippov authored 9 years ago
  
  1f464a83
03 Jun, 2015 1 commit
- converting gamma tables to multi-sensor for each sesnor port, adding... · 0fec497c
  Andrey Filippov authored 9 years ago
```
converting gamma tables to multi-sensor for each sesnor port, adding buffered/non-buffered parameter option
```
  0fec497c
01 Jun, 2015 1 commit
- working on histograms · f21c367f
  Andrey Filippov authored 9 years ago
  
  f21c367f
30 May, 2015 2 commits
- changed mode to TDP for <64/ <64 widths · c5020610
  Andrey Filippov authored 9 years ago
  
  c5020610
- added wrappers for block RAM in TDP mode (each port with R+W) · c505535c
  Andrey Filippov authored 9 years ago
  
  c505535c
29 May, 2015 1 commit
- parametrized (9-36 bit wide) module wrapper utilizing parity bits to extend data width · b6281d7d
  Andrey Filippov authored 9 years ago
  
  b6281d7d
19 May, 2015 1 commit
- working on sensor channel · 6021159e
  Andrey Filippov authored 9 years ago
  
  6021159e
15 May, 2015 1 commit
- working on files realted to sensor channels, added frame sequences to... · 6b2c4c47
  Andrey Filippov authored 9 years ago
```
working on files realted to sensor channels, added frame sequences to mcntrl_linear_rw.v and mcntrl_tiled_rw.v
```
  6b2c4c47
27 Apr, 2015 1 commit
- added missing files · bb5c2299
  Andrey Filippov authored 9 years ago
  
  bb5c2299
22 Apr, 2015 1 commit
- Modified write module to support variable 'sel' input, adjustedg hardware to simulation timing · c8b52324
  Andrey Filippov authored 9 years ago
  
  c8b52324
21 Apr, 2015 1 commit
- modulte to adjust timing to actual hadrware · ea23bda4
  Andrey Filippov authored 9 years ago
  
  ea23bda4
11 Jun, 2014 1 commit
- working with hardware · f2c019cd
  Andrey Filippov authored 10 years ago
  
  f2c019cd
08 Jun, 2014 1 commit
- organized new/debug files · 7e44243b
  Andrey Filippov authored 10 years ago
  
  7e44243b
07 Jun, 2014 1 commit
- troubleshooting lack of DONE during loading of the bitfile · cd3ccb58
  Andrey Filippov authored 10 years ago
  
  cd3ccb58
01 Jun, 2014 1 commit
- added configuration for ISE, timing constraints for Vivado · 46cf253d
  Andrey Filippov authored 10 years ago
  
  46cf253d