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dci_reset.v organized new/debug files
ddr3_wrap.v Changed 'author' to full name
ibuf_ibufg.v Implemented clock management, entered pads physical constraints
ibufds_ibufgds.v Trying synthesis, fixing revealed bugs
idelay_ctrl.v adjusting constraint attributes in the source
idelay_fine_pipe.v simulating multiple simultanerous sesnor/compressor channels
idelay_nofine.v adjusting constraint attributes in the source
iobuf.v Changed 'author' to full name
iserdes_mem.v simulating/bug fixing
latch_g_ce.v Added wrapper for latch primitive as tools do not recognise global clock as G if inferred
mmcm_adv.v more on hispi code
mmcm_phase_cntr.v more on hispi code
mpullup.v Changed 'author' to full name
obuf.v debugging, next snapshot
obufds.v more on hispi code
oddr.v moved files
oddr_ds.v working on sensor channel
oddr_ss.v Changed 'author' to full name
odelay_fine_pipe.v simulating multiple simultanerous sesnor/compressor channels
odelay_pipe.v adjusting constraint attributes in the source
oserdes_mem.v making previous simulation tasks run on the full x393 code
pll_base.v Implemented clock management, entered pads physical constraints
ram18_var_w_var_r.v Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
ram18p_var_w_var_r.v Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
ram18t_var_w_var_r.v modifying histograms module to avoid use of the double pixel frequency clock
ram18tp_var_w_var_r.v Loading commit data...
ram_1kx32_1kx32.v Loading commit data...
ram_1kx32w_512x64r.v Loading commit data...
ram_512x64w_1kx32r.v Loading commit data...
ram_var_w_var_r.v Loading commit data...
ramp_var_w_var_r.v Loading commit data...
ramt_var_w_var_r.v Loading commit data...
ramtp_var_w_var_r.v Loading commit data...