Commit f2c019cd authored by Andrey Filippov's avatar Andrey Filippov

working with hardware

parent 780f7359
......@@ -62,72 +62,72 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140610171311514.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140611121113006.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140610171311514.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140611121113006.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140610171311514.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140611121113006.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140610171311514.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140611121113006.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140610171311514.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140611121113006.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140610171311514.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140611121113006.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140610171153284.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140611121031786.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140610171311514.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140611121113006.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140610171311514.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140611121113006.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140610171311514.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140611121113006.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140610171311514.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140611121113006.log</location>
</link>
<link>
<name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140610171311514.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140611121113006.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-place.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140610171311514.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140611121113006.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-route.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140610171311514.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140611121113006.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-synth.dcp</name>
......
......@@ -19,7 +19,8 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
// minimizing total DQS in delay to match DQ (finedelay stage adds some?)
`define NOFINEDELAY_DQS 1
module byte_lane #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
......@@ -145,7 +146,11 @@ dm_single #(
.ld_odelay(ld_odly_dm) // clk_div synchronous set odealy value from loaded
);
`ifdef NOFINEDELAY_DQS
dqs_single_nofine #(
`else
dqs_single #(
`endif
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.IOSTANDARD(IOSTANDARD_DQS),
......
......@@ -22,6 +22,7 @@
module cmda_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter integer ODELAY_VALUE = 0,
parameter IOSTANDARD = "SSTL15",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
......@@ -58,7 +59,7 @@ oserdes_mem#(
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.DELAY_VALUE(ODELAY_VALUE),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
......
......@@ -23,6 +23,8 @@
`define USE_IOBUF 1
module dm_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
// parameter integer IDELAY_VALUE = 0,
parameter integer ODELAY_VALUE = 0,
parameter IBUF_LOW_PWR ="TRUE", //SuppressThisWarning VEditor not used in OBUF_DCIEN
parameter IOSTANDARD = "SSTL15_T_DCI",
parameter SLEW = "SLOW",
......@@ -58,7 +60,7 @@ oserdes_mem#(
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.DELAY_VALUE(ODELAY_VALUE),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dm_out_dly_i(
......
......@@ -22,6 +22,8 @@
module dq_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter integer IDELAY_VALUE = 0,
parameter integer ODELAY_VALUE = 0,
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD = "SSTL15_T_DCI",
parameter SLEW = "SLOW",
......@@ -68,7 +70,7 @@ oserdes_mem#(
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.DELAY_VALUE(ODELAY_VALUE),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dq_out_dly_i(
......@@ -96,7 +98,7 @@ IOBUF_DCIEN #(
idelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.DELAY_VALUE(IDELAY_VALUE),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dq_in_dly_i(
......
......@@ -21,6 +21,8 @@
`timescale 1ns/1ps
module dqs_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter integer IDELAY_VALUE = 0,
parameter integer ODELAY_VALUE = 0,
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD = "DIFF_SSTL15_T_DCI",
parameter SLEW = "SLOW",
......@@ -64,7 +66,7 @@ oserdes_mem oserdes_i (
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.DELAY_VALUE(ODELAY_VALUE),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
......@@ -94,7 +96,7 @@ IOBUFDS_DCIEN #(
.T(dqs_tri));
idelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.DELAY_VALUE(IDELAY_VALUE),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_in_dly_i(
......
/*******************************************************************************
* Module: dqs_single_nofine
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Single-bit DDR3 DQS I/O
*
* Copyright (c) 2014 Elphel, Inc.
* dqs_single_nofine.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dqs_single_nofine.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module dqs_single_nofine #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter integer IDELAY_VALUE = 0, // same scale as for fine delay
parameter integer ODELAY_VALUE = 0,
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD = "DIFF_SSTL15_T_DCI",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
inout dqs,
inout ndqs,
input clk,
input clk_div,
input rst,
output dqs_received_dly,
// output dqs_di, // debugging:
//Input buffer ddrc_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_S (in ddrc_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i macro) has no loads. An input buffer must drive an internal load.
input dci_disable, // disable DCI termination during writes and idle
input [7:0] dly_data,
input [3:0] din,
input [3:0] tin,
input set_odelay,
input ld_odelay,
input set_idelay,
input ld_idelay
);
wire d_ser;
wire dqs_tri;
wire dqs_data_dly;
wire dqs_di;
oserdes_mem oserdes_i (
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(din[3:0]), // parallel data in
.tin(tin[3:0]), // parallel tri-state in
.dout_dly(d_ser), // data out to be connected to odelay input
.dout_iob(), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(ODELAY_VALUE),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_odelay),
.ld(ld_odelay),
.delay(dly_data[7:0]),
.data_in(d_ser),
.data_out(dqs_data_dly)
);
IOBUFDS_DCIEN #(
.DIFF_TERM("FALSE"),
.DQS_BIAS("TRUE"), // outputs 1'b0 when IOB is floating
.IBUF_LOW_PWR(IBUF_LOW_PWR), //
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.USE_IBUFDISABLE("FALSE")
) iobufs_dqs_i (
.O(dqs_di),
.IO(dqs),
.IOB(ndqs),
.DCITERMDISABLE(dci_disable),
.IBUFDISABLE(1'b0),
.I(dqs_data_dly), //dqs_data),
.T(dqs_tri));
idelay_nofine # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(IDELAY_VALUE>>3),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_in_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_idelay),
.ld(ld_idelay),
.delay(dly_data[7:3]),
.data_in(dqs_di),
.data_out(dqs_received_dly)
);
endmodule
......@@ -403,7 +403,8 @@ def encode_seq_skip(
# Set MR3, read nrep*8 words, save to buffer (port0). No ACTIVATE/PRECHARGE are needed/allowed
def set_read_pattern( # task set_read_pattern;
nrep, # input integer nrep;
npat):#trying pattern type (only 0 defined)
npat, #trying pattern type (only 0 defined)
scnd):#adjusting first/seccond
# reg [31:0] cmd_addr;
# reg [31:0] data;
# reg [17:0] mr3_norm;
......@@ -446,7 +447,7 @@ def set_read_pattern( # task set_read_pattern;
((0x2 & 0x7) << 11) | # 3'b010, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
......@@ -482,7 +483,7 @@ def set_read_pattern( # task set_read_pattern;
((0x2 & 0x7) << 11) | # 3'b010, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
......@@ -596,7 +597,8 @@ def set_read_pattern( # task set_read_pattern;
def set_read_block(
ba, # [ 2:0] bank address
ra, # [14:0] row address
ca): # [ 9:0] column address
ca, # [ 9:0] column address
scnd): # use second (delayed) clock for read command
# cmd_addr, # command address (bit 10 - auto/manual banks)
# data): # [31:0] - command data
global BASEADDR_CMD0, READ_BLOCK_OFFSET
......@@ -631,7 +633,7 @@ def set_read_block(
((0x2 & 0x7) << 11) | # 3'b010, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
......@@ -648,7 +650,7 @@ def set_read_block(
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
......@@ -667,7 +669,7 @@ def set_read_block(
((0x2 & 0x7) << 11) | # 3'b010, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
......@@ -684,7 +686,7 @@ def set_read_block(
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
......@@ -701,7 +703,7 @@ def set_read_block(
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
......@@ -718,7 +720,7 @@ def set_read_block(
((0x0 & 0x7) << 11) | # 3'b000, # phy_rcw_in[2:0], # {ras,cas,we}
((0 & 0x1) << 10) | # phy_odt_in
((0 & 0x1) << 9) | # phy_cke_inv # invert CKE
(( 1 & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((scnd & 0x1) << 8) | # phy_sel_in # first/second half-cycle, other will be nop (cke+odt applicable to both)
((0 & 0x1) << 7) | # phy_dq_en_in #phy_dq_tri_in, # tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 6) | # phy_dqs_en_in #phy_dqs_tri_in, # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
((0 & 0x1) << 5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern
......@@ -1545,7 +1547,7 @@ def set_all_sequences(): # task set_all_sequences;
print("SET WRITE LEVELING")
set_write_lev(16) # write leveling, 16 times (full buffer - 128)
print("SET READ PATTERN")
set_read_pattern(8,0) # 8x2*64 bits, 32x32 bits to read (second 0 - pattern type, only 0 defined)
set_read_pattern(8,0,1) # 8x2*64 bits, 32x32 bits to read (second 0 - pattern type, only 0 defined)
print("SET WRITE BLOCK")
set_write_block(
5, # 3'h5, # bank
......@@ -1556,7 +1558,8 @@ def set_all_sequences(): # task set_all_sequences;
set_read_block(
5, # 3'h5, # bank
0x1234, # 15'h1234, # row address
0x100 # 10'h100 # column address
0x100, # 10'h100 # column address
1 # use second clock for read commands
)
def set_up(): # task set_up;
......@@ -1657,13 +1660,13 @@ elif command=="read_buf":
read_buf(args[0])
print("read_buf() OK")
elif command=="set_read_pattern":
check_args(2,command,args)
set_read_pattern(args[0],args[1])
print("set_read_pattern(0x%x) OK"%(args[0]))
elif command=="set_read_block":
check_args(3,command,args)
set_read_block(args[0],args[1],args[2])
print("set_read_block(0x%x,0x%x,0x%x) OK"%(args[0],args[1],args[2]))
set_read_pattern(args[0],args[1],args[2])
print("set_read_pattern(0x%x,0x%x,0x%x) OK"%(args[0],args[1],args[2]))
elif command=="set_read_block":
check_args(4,command,args)
set_read_block(args[0],args[1],args[2],args[3])
print("set_read_block(0x%x,0x%x,0x%x,0x%x) OK"%(args[0],args[1],args[2],args[3]))
elif command=="set_write_block":
check_args(3,command,args)
set_write_block(args[0],args[1],args[2])
......
/*******************************************************************************
* Module: idelay_nofine
* Date:2014-04-25
* Author: Andrey Filippov
* Description: IDELAYE2 wrapper without fine delay
* Copyright (c) 2014 Elphel, Inc.
* idelay_nofine.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* idelay_nofine.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module idelay_nofine
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter integer DELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
) (
input clk,
input rst,
input set,
input ld,
input [4:0] delay,
input data_in,
output data_out
);
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2
#(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
// .FINEDELAY("ADD_DLY"),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(DELAY_VALUE),
// .IS_C_INVERTED(1'b0), // ISE does not have this parameter
// .IS_DATAIN_INVERTED(1'b0), // ISE does not have this parameter
// .IS_IDATAIN_INVERTED(1'b0), // ISE does not have this parameter
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA")
)
idelay2_i(
.CNTVALUEOUT(),
.DATAOUT(data_out),
.C(clk),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(delay[4:0]),
.DATAIN(1'b0),
.IDATAIN(data_in),
// .IFDLY(fdly),
.INC(1'b0),
.LD(set),
.LDPIPEEN(ld),
.REGRST(rst)
);
endmodule
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