Commit 75f18826 authored by Andrey Filippov's avatar Andrey Filippov

simulating/bug fixing

parent ae549ed4
FPGA_project_0_SimulationTopFile=x393_testbench02.tf
FPGA_project_1_SimulationTopModule=x393_testbench02
FPGA_project_0_SimulationTopFile=x393_testbench03.tf
FPGA_project_1_SimulationTopModule=x393_testbench03
FPGA_project_2_ImplementationTopFile=x393.v
FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1
......
......@@ -429,11 +429,20 @@
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
//`ifdef HISPI
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
//`else
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
//`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
//`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
//`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
//`endif
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// SENSIO_JTAG register bits
......@@ -442,7 +451,9 @@
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
//`ifndef HISPI
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
//`endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
......@@ -466,10 +477,13 @@
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_SLEW = "SLOW",
//`ifndef HISPI
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 4'd5, // 7,
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 5, // 7,
//`endif
// other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_WIDTH = 8,
......@@ -504,16 +518,31 @@
parameter real SENS_REFCLK_FREQUENCY = 200.0,
`endif
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
//`ifdef HISPI
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4,
//`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
// parameters for the sensor-synchronous clock PLL
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`endif
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
......@@ -535,6 +564,18 @@
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
//`ifdef HISPI
parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT",
//`endif
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
......
......@@ -38,6 +38,15 @@
// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
`ifdef HISPI
parameter SENSOR12BITS_NGPL = 2, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
//parameter tDDO = 10; // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TMD = 1.2, //
parameter SENSOR12BITS_TDDO = 0.8, // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TDDO1 = 1.6, //
`else
parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
......@@ -45,6 +54,7 @@
parameter SENSOR12BITS_TMD = 4, //
parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TDDO1 = 5, //
`endif
// parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines
// parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat)
// parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18)
......
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This diff is collapsed.
......@@ -23,10 +23,11 @@
module sens_hispi_clock#(
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT_SENSOR = 4, // 220 MHz --> 880 MHz
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
......@@ -91,7 +92,7 @@ module sens_hispi_clock#(
// received from the sensor (may need to reset MMCM after resetting sensor)
mmcm_phase_cntr #(
.PHASE_WIDTH (SENS_PHASE_WIDTH),
.CLKIN_PERIOD (SENS_PCLK_PERIOD),
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), // 4
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
......@@ -101,8 +102,8 @@ module sens_hispi_clock#(
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_USE_FINE_PS ("TRUE"),
.CLKOUT1_USE_FINE_PS ("TRUE"),
.CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR), // 4 // 8.000),
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 2), //2 // 4),
.CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR * 2), // 6 // 8.000),
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR ), // 3 // 4),
.COMPENSATION ("ZHOLD"),
.REF_JITTER1 (SENS_REF_JITTER1),
.REF_JITTER2 (SENS_REF_JITTER2),
......
......@@ -53,7 +53,7 @@ module sens_hispi_din #(
generate
genvar i;
for (i=1; i < HISPI_NUMLANES; i=i+1) begin: din_block
for (i=0; i < HISPI_NUMLANES; i=i+1) begin: din_block
ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
......@@ -84,17 +84,18 @@ module sens_hispi_din #(
);
iserdes_mem #(
.DYN_CLKDIV_INV_EN("FALSE")
.DYN_CLKDIV_INV_EN ("FALSE"),
.MSB_FIRST (1) // MSB is received first
) iserdes_pxd_i (
.iclk(ipclk2x), // source-synchronous clock
.oclk(ipclk2x), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div(ipclk), // oclk divided by 2, front aligned
.inv_clk_div(1'b0), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst(irst), // reset
.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly(din_dly[i]), // serial input from idelay
.dout(dout[4*i +:4]), // parallel data out
.comb_out() // output
.iclk (ipclk2x), // source-synchronous clock
.oclk (ipclk2x), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div (ipclk), // oclk divided by 2, front aligned
.inv_clk_div (1'b0), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst (irst), // reset
.d_direct (1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly (din_dly[i]), // serial input from idelay
.dout (dout[4*i +:4]), // parallel data out
.comb_out() // output
);
end
......
......@@ -46,13 +46,13 @@ module sens_hispi_fifo#(
reg run_r;
assign run = run_r;
// TODO: generate early done by comparing ra with (wa-1) - separate counter
always @ (posedge ipclk) begin
if (irst ||sol) wa <= 0;
else if (we && line_run_ipclk) wa <= wa + 1;
if (we && line_run_ipclk) fifo_ram[wa] <= din;
if (we && line_run_ipclk) fifo_ram[wa[DATA_DEPTH-1:0]] <= din;
if (irst || eol) line_run_ipclk <= 0;
else if (sol) line_run_ipclk <= 1;
......@@ -68,7 +68,7 @@ module sens_hispi_fifo#(
if (prst ||line_start_pclk) ra <= 0;
else if (re) ra <= ra + 1;
if (re) dout <= fifo_ram[ra];
if (re) dout <= fifo_ram[ra[DATA_DEPTH-1:0]];
end
......
......@@ -79,7 +79,8 @@ module sens_hispi_lane#(
assign num_trail_1_w = (&din) ? 3'h4 : ((&din[2:0]) ? 3'h3 : ((&din[1:0]) ? 3'h2 :((&din[0]) ? 3'h1 : 3'h0)));
assign num_lead_1_w = (&din) ? 3'h4 : ((&din[3:1]) ? 3'h3 : ((&din[3:2]) ? 3'h2 :((&din[3]) ? 3'h1 : 3'h0)));
assign zero_after_ones_w = !((din[0] && !din[1]) || (din[1] && !din[2]) || (din[2] && !din[3]) || (d_r[3] && !din[0]));
// assign zero_after_ones_w = !((din[0] && !din[1]) || (din[1] && !din[2]) || (din[2] && !din[3]) || (d_r[3] && !din[0]));
assign zero_after_ones_w = !((din[0] && !din[1]) || (din[1] && !din[2]) || (din[2] && !din[3]) || (din[3] && !d_r[0]));
always @(posedge ipclk) begin
d_r <= din;
......@@ -100,7 +101,8 @@ module sens_hispi_lane#(
// Saturate number with 24 (5'h18), but only first transition from <24 to >=24 is used for sync
// detection.
if (irst || !num_running_ones[3]) num_running_zeros <= 0;
else if (!num_running_ones[2]) num_running_zeros <= {2'b0,num_trail_0_w};
// else if (!num_running_ones[2]) num_running_zeros <= {2'b0,num_trail_0_w};
else if (prev4ones) num_running_zeros <= {2'b0,num_trail_0_w};
else num_running_zeros <= (&num_running_zeros[4:3])? 5'h18 : num_running_zeros_w;
if (irst) got_sync <= 0;
......@@ -108,14 +110,17 @@ module sens_hispi_lane#(
// got_sync should also abort data run - delayed by 10 clocks
if (irst) shift_val <= 0;
else if (got_sync) shift_val <= num_first_zeros;
if (irst) shift_val <= 0;
// else if (got_sync) shift_val <= num_first_zeros;
else if (got_sync_w) shift_val <= num_first_zeros;
case (shift_val)
2'h0: barrel <= din;
2'h1: barrel <= {d_r[2:0], din[3]};
// 2'h1: barrel <= {d_r[2:0], din[3]};
2'h1: barrel <= {d_r[0], din[3:1]};
2'h2: barrel <= {d_r[1:0], din[3:2]};
2'h3: barrel <= {d_r[0], din[3:1]};
// 2'h3: barrel <= {d_r[0], din[3:1]};
2'h3: barrel <= {d_r[2:0], din[3]};
endcase
if (irst) sync_decode <= 0;
......@@ -174,7 +179,7 @@ module sens_hispi_lane#(
) dly_16_dout_i (
.clk (ipclk), // input
.rst (1'b0), // input
.dly (8), // input[3:0]
.dly (4'h8), // input[3:0]
.din (HISPI_MSB_FIRST ? barrel :{barrel[0],barrel[1],barrel[2],barrel[3]}), // input[0:0]
.dout (dout_w) // output[0:0]
);
......@@ -183,7 +188,7 @@ module sens_hispi_lane#(
) dly_16_pre_start_line_i (
.clk (ipclk), // input
.rst (1'b0), // input
.dly (7), // input[3:0]
.dly (4'h7), // input[3:0]
.din (start_line), // input[0:0]
.dout (start_line_d) // output[0:0]
);
......
......@@ -59,9 +59,10 @@ module sens_parallel12 #(
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
......@@ -642,7 +643,7 @@ module sens_parallel12 #(
// received from the sensor (may need to reset MMCM after resetting sensor)
mmcm_phase_cntr #(
.PHASE_WIDTH (SENS_PHASE_WIDTH),
.CLKIN_PERIOD (SENS_PCLK_PERIOD),
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR), // SENS_PCLK_PERIOD), assuming both sources have the same frequency!
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), //8
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
......
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This diff is collapsed.
......@@ -26,7 +26,7 @@ module par12_hispi_psp4l#(
parameter LANE0_DLY = 1.3,
parameter LANE1_DLY = 2.7,
parameter LANE2_DLY = 0.2,
parameter LANE3_DLY = 3.3,
parameter LANE3_DLY = 1.8,
parameter CLK_DLY = 2.3,
parameter EMBED_LINES = 2, // number of first lines containing embedded (non-image) data
parameter MSB_FIRST = 0,
......@@ -69,7 +69,9 @@ module par12_hispi_psp4l#(
vact_d <= vact;
hact_d <= hact;
pxd_d <= {pxd_d[35:0],pxd};
// pxd_d <= {pxd_d[35:0],pxd};
pxd_d <= {pxd, pxd_d[47:12]};
if (!vact) lane_pcntr <= 0;
else if (hact) lane_pcntr <= lane_pcntr + 1;
......
......@@ -48,7 +48,7 @@ module simul_clk_mult_div#(
sim_clk_div #(
.DIVISOR (DIVISOR)
) sim_clk_div_i (
.clk_in (clk_in), // input
.clk_in (clk_int), // input
.en (en), // input
.clk_out (clk_out) // output
);
......
......@@ -3,7 +3,7 @@
`define SYSTEM_DEFINES
`define PRELOAD_BRAMS
// if HISPI is not defined, parallel sensor interface is used for all channels
// `define HISPI
`define HISPI
// `define DEBUG_RING 1
`define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
......
......@@ -23,7 +23,8 @@
module iserdes_mem #
(
parameter DYN_CLKDIV_INV_EN="FALSE",
parameter IOBDELAY = "IFD" // "NONE", "IBUF", "IFD", "BOTH"
parameter IOBDELAY = "IFD", // "NONE", "IBUF", "IFD", "BOTH"
parameter MSB_FIRST = 0 // 0 - lowest bit is received first, 1 - highest is received first
) (
input iclk, // source-synchronous clock
input oclk, // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
......@@ -35,7 +36,8 @@ module iserdes_mem #
output [3:0] dout,
output comb_out // combinatorial output copies selected input to be used in the fabric
);
wire [3:0] dout_le;
assign dout = MSB_FIRST ? {dout_le[0], dout_le[1], dout_le[2], dout_le[3]} : dout_le;
`ifndef OPEN_SOURCE_ONLY // Not using simulator - instanciate actual ISERDESE2 (can not be simulated because of encrypted )
ISERDESE2 #(
.DATA_RATE ("DDR"),
......@@ -60,10 +62,10 @@ module iserdes_mem #
iserdes_i
(
.O (comb_out),
.Q1 (dout[3]),
.Q2 (dout[2]),
.Q3 (dout[1]),
.Q4 (dout[0]),
.Q1 (dout_le[3]),
.Q2 (dout_le[2]),
.Q3 (dout_le[1]),
.Q4 (dout_le[0]),
.Q5 (),
.Q6 (),
.Q7 (),
......@@ -111,10 +113,10 @@ module iserdes_mem #
iserdes_i
(
.O (comb_out),
.Q1 (dout[3]),
.Q2 (dout[2]),
.Q3 (dout[1]),
.Q4 (dout[0]),
.Q1 (dout_le[3]),
.Q2 (dout_le[2]),
.Q3 (dout_le[1]),
.Q4 (dout_le[0]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
......
......@@ -1487,11 +1487,20 @@ assign axi_grst = axi_rst_pre;
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`ifdef HISPI
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
`else
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
`endif
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
`ifdef HISPI
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
`else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
`endif
.SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
......@@ -1499,7 +1508,9 @@ assign axi_grst = axi_rst_pre;
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
`ifndef HISPI
.SENSIO_WIDTH (SENSIO_WIDTH),
`endif
.SENSIO_DELAYS (SENSIO_DELAYS),
.SENSI2C_ABS_RADDR (SENSI2C_ABS_RADDR),
.SENSI2C_REL_RADDR (SENSI2C_REL_RADDR),
......@@ -1515,9 +1526,11 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW),
`ifndef HISPI
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
`endif
.HIST_SAXI_ADDR_MASK (HIST_SAXI_ADDR_MASK),
.HIST_SAXI_MODE_WIDTH (HIST_SAXI_MODE_WIDTH),
.HIST_SAXI_EN (HIST_SAXI_EN),
......@@ -1538,9 +1551,15 @@ assign axi_grst = axi_rst_pre;
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
`ifdef HISPI
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`endif
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
......@@ -1559,6 +1578,17 @@ assign axi_grst = axi_rst_pre;
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
`ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
`endif
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
......
......@@ -250,7 +250,7 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
localparam HISPI_CLK_MULT = 10; // from pixel clock to serial output pixel rate TODO: Set real ones, adjsut sensor clock too
localparam HISPI_EMBED_LINES = 2; // first lines will be marked as "embedded" (non-image data)
localparam HISPI_MSB_FIRST = 2; // 0 - serialize LSB first, 1 - MSB first
// localparam HISPI_MSB_FIRST = 0; // 0 - serialize LSB first, 1 - MSB first
localparam HISPI_FIFO_LOGDEPTH = 12; // 49-bit wide FIFO address bits (>log (line_length + 2)
`endif
......@@ -2096,7 +2096,7 @@ simul_axi_hp_wr #(
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (3.3),
.LANE3_DLY (1.8),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
......@@ -2119,7 +2119,7 @@ simul_axi_hp_wr #(
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (3.3),
.LANE3_DLY (1.8),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
......@@ -2142,7 +2142,7 @@ simul_axi_hp_wr #(
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (3.3),
.LANE3_DLY (1.8),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
......@@ -2165,7 +2165,7 @@ simul_axi_hp_wr #(
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (3.3),
.LANE3_DLY (1.8),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
......
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