Added modules to convert 32-bit parallel writes to two registers to 8-bit wide network for writing consecutive locations in block memories

Added modules to convert 32-bit parallel writes to two registers to 8-bit wide network for writing consecutive locations in block memories

working on files realted to sensor channels, added frame sequences to mcntrl_linear_rw.v and mcntrl_tiled_rw.v

Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded