Continue re-organizing memory controller for x393

.editor_defines

   // This file may be used to define same pre-processor macros to be included into each parsed file
   // It can be used to check different `ifdef branches
   //`define XIL_TIMING //Simprim 
-  `define IVERILOG
\ No newline at end of file
+  `define IVERILOG
+  // defines for memory channels
+  // chn 0 is read from memory
+ `define def_enable_mem_chn0
+ `define def_read_mem_chn0
+ 
+  // chn 1 is write to memory
+ `define def_enable_mem_chn1
+ `undef  def_read_mem_chn1
+
+  // chn 2 is read from memory
+ `define def_enable_mem_chn2
+ `define def_read_mem_chn2
+
+  // chn 3 is write to memory
+ `define def_enable_mem_chn3
+ `undef  def_read_mem_chn3
+
+  // chn 4 is disabled
+ `undef  def_enable_mem_chn4
+
+  // chn 5 is disabled
+ `undef  def_enable_mem_chn5
+
+  // chn 6 is disabled
+ `undef  def_enable_mem_chn6
+ 
+  // chn 7 is disabled
+ `undef  def_enable_mem_chn7
+ 
+  // chn 8 is disabled
+ `undef  def_enable_mem_chn8
+ 
+  // chn 9 is disabled
+ `undef  def_enable_mem_chn9
+ 
+  // chn 10 is disabled
+ `undef  def_enable_mem_chn10
+ 
+  // chn 11 is disabled
+ `undef  def_enable_mem_chn11
+ 
+  // chn 12 is disabled
+ `undef  def_enable_mem_chn12
+ 
+  // chn 13 is disabled
+ `undef  def_enable_mem_chn13
+ 
+  // chn 14 is disabled
+ `undef  def_enable_mem_chn14
+ 
+  // chn 15 is disabled
+ `undef  def_enable_mem_chn15
+ 
+ 
\ No newline at end of file

address_map.txt

+0x1000..103f - 0- bit data (set/reset)
+    parameter MCONTR_PHY_0BIT_ADDR =           'h020,  // address to set sequnecer channel and  run (4 LSB-s - channel)
+    parameter MCONTR_PHY_0BIT_ADDR_MASK =      'h3f0,  // address mask to generate sequencer channel/run
+  0x1020       - DLY_SET      // 0 bits -set pre-programmed delays 
+  0x1024..1025 - CMDA_EN      // 0 bits - enable/disable command/address outputs 
+  0x1026..1027 - SDRST_ACT    // 0 bits - enable/disable active-low reset signal to DDR3 memory
+  0x1028..1029 - CKE_EN       // 0 bits - enable/disable CKE signal to memory 
+  0x102a..102b - DCI_RST      // 0 bits - enable/disable CKE signal to memory 
+  0x102c..102d - DLY_RST      // 0 bits - enable/disable CKE signal to memory
+    parameter MCONTR_PHY_0BIT_DLY_SET =        'h0,    // set pre-programmed delays 
+    parameter MCONTR_PHY_0BIT_CMDA_EN =        'h4,    // enable/disable command/address outputs 
+    parameter MCONTR_PHY_0BIT_SDRST_ACT =      'h6,    // enable/disable active-low reset signal to DDR3 memory
+    parameter MCONTR_PHY_0BIT_CKE_EN =         'h8,    // enable/disable CKE signal to memory 
+    parameter MCONTR_PHY_0BIT_DCI_RST =        'ha,    // enable/disable CKE signal to memory 
+    parameter MCONTR_PHY_0BIT_DLY_RST =        'hc,    // enable/disable CKE signal to memory 
+
+0x1040..107f - 16-bit data
+  0x1050..1057: MCONTR_PHY16
+    parameter MCONTR_PHY_16BIT_ADDR =           'h050,  // address to set sequnecer channel and  run (4 LSB-s - channel)
+    parameter MCONTR_PHY_16BIT_ADDR_MASK =      'h3f8,  // address mask to generate sequencer channel/run
+  0x1050       - PATTERNS     // 16 bits
+  0x1051       - PATTERNS_TRI // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each 
+  0x1052       - WBUF_DELAY   // 4 bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
+  0x1053       - EXTRA_REL    // 1 bit - set extra parameters (currently just inv_clk_div)
+  0x1054       - STATUS_CNTRL // 8 bits - write to status control
+    parameter MCONTR_PHY_16BIT_PATTERNS =       'h0,    // set DQM and DQS patterns (16'h0055)
+    parameter MCONTR_PHY_16BIT_PATTERNS_TRI =   'h1,    // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each 
+    parameter MCONTR_PHY_16BIT_WBUF_DELAY =     'h2,    // 4 bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
+    parameter MCONTR_PHY_16BIT_EXTRA_REL =      'h3,    // 1 bit - set extra parameters (currently just inv_clk_div)
+    parameter MCONTR_PHY_STATUS_CNTRL =         'h4,    // 8 bits - write to status control
+// Status read address
+    parameter STATUS_ADDR =         'h1400, // AXI write address of status read registers
+    parameter STATUS_ADDR_MASK =    'h1400, // AXI write address of status registers
+    parameter STATUS_DEPTH=         8,  // 256 cells, maybe just 16..64 are enough?
+    parameter MCONTR_PHY_STATUS_REG_ADDR=      'h0,    // 8 or less bits: status register address to use for memory controller phy
+
+================================ OLD =======================================================
+ Control addresses (in original ddrc_test01)
+0x1000..100f - RUN_CHN      // address to set sequnecer channel and  run (4 LSB-s - channel) - bits? 
+0x1020       - PATTERNS     // 16 bits
+0x1021       - PATTERNS_TRI // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each 
+0x1022       - WBUF_DELAY   // 4? bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
+0x1023       - PAGES        // will be removed! 8 bits - address to set buffer pages {port1_page[1:0], port1_int_page[1:0], port0_page[1:0], port0_int_page[1:0]}
+0x1024..1025 - CMDA_EN      // 0 bits - enable/disable command/address outputs 
+0x1026..1027 - SDRST_ACT    // 0 bits - enable/disable active-low reset signal to DDR3 memory
+0x1028..1029 - CKE_EN       // 0 bits - enable/disable CKE signal to memory 
+0x102a..102b - DCI_RST      // 0 bits - enable/disable CKE signal to memory 
+0x102c..102d - DLY_RST      // 0 bits - enable/disable CKE signal to memory 
+0x102e       - EXTRA_REL    // ? bits - set extra parameters (currently just inv_clk_div)
+0x102f - X
+0x1030..1031 - REFRESH_EN   // 0 bits - enable/disable DDR refresh
+0x1032       - REFRESH_PER  // 16? bits - refresh period in 32 x tCK
+0x1033       - REFRESH_ADDR // 16? bits - sequencer start address for DDR refresh
+0x1070       - DLY_SET  // 0 bits (set bit delays)
+0x1080..10ff - DLY_LD   // 8 bits :
+  0x1080..109f - set delay for SDD0-SDD7
+  0x10a0..10bf - set delay for SDD8-SDD15
+  0x10c0..10df - set delay for SD_CMDA
+  0x10e0       - set delay for MMCM
+ 
+ 
+    parameter WBUF_DELAY_REL_MASK =   'h3ff,  // address mask to set extra delay
+    parameter PAGES_REL =             'h023,  // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
+    parameter PAGES_REL_MASK =        'h3ff,  // address mask to set DQM and DQS patterns
+    parameter CMDA_EN_REL =           'h024,  // address to enable('h825)/disable('h824) command/address outputs  
+    parameter CMDA_EN_REL_MASK =      'h3fe,  // address mask for command/address outputs
+    parameter SDRST_ACT_REL =         'h026,  // address to activate('h827)/deactivate('h826) active-low reset signal to DDR3 memory  
+    parameter SDRST_ACT_REL_MASK =    'h3fe,  // address mask for reset DDR3
+    parameter CKE_EN_REL =            'h028,  // address to enable('h829)/disable('h828) CKE signal to memory   
+    parameter CKE_EN_REL_MASK =       'h3fe,  // address mask for command/address outputs
+    parameter DCI_RST_REL =           'h02a,  // address to activate('h82b)/deactivate('h82a) Zynq DCI calibrate circuitry  
+    parameter DCI_RST_REL_MASK =      'h3fe,  // address mask for DCI calibrate circuitry
+    parameter DLY_RST_REL =           'h02c,  // address to activate('h82d)/deactivate('h82c) delay calibration circuitry  
+    parameter DLY_RST_REL_MASK =      'h3fe,  // address mask for delay calibration circuitry
+    parameter EXTRA_REL =             'h02e,  // address to set extra parameters (currently just inv_clk_div)
+    parameter EXTRA_REL_MASK =        'h3ff,  // address mask for extra parameters
+    parameter REFRESH_EN_REL =        'h030,  // address to enable('h31) and disable ('h30) DDR refresh
+    parameter REFRESH_EN_REL_MASK =   'h3fe,  // address mask to enable/disable DDR refresh
+    parameter REFRESH_PER_REL =       'h032,  // address to set refresh period in 32 x tCK
+    parameter REFRESH_PER_REL_MASK =  'h3ff,  // address mask set refresh period
+    parameter REFRESH_ADDR_REL =      'h033,  // address to set sequencer start address for DDR refresh
+    parameter REFRESH_ADDR_REL_MASK = 'h3ff   // address mask set refresh sequencer address

ddrc_test01_testbench.tf

@@ -1689,7 +1689,6 @@ simul_axi_read simul_axi_read_i(
                 @(posedge CLK)
                 axi_write_single(cmd_addr, data);
                 cmd_addr <= cmd_addr + 4;
-
              end
              
 // nop

status_read.v

@@ -32,7 +32,7 @@ module  status_read#(
     parameter STATUS_ADDR =         'h1400, // AXI write address of status read registers
     parameter STATUS_ADDR_MASK =    'h1400, // AXI write address of status registers
     parameter AXI_RD_ADDR_BITS =    13,
-    parameter integer DATA_DEPTH=   8 // 256 cells, maybe just 16..64 are enough?
+    parameter integer STATUS_DEPTH=   8 // 256 cells, maybe just 16..64 are enough?
 )(
     input rst,
     input clk,
@@ -44,10 +44,10 @@ module  status_read#(
     input                        rq,               // request from sources to transfer status data
     output                       start             // acknowledge receiving of first byte (address), currently always ready
 );
-    localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
+    localparam integer DATA_2DEPTH=(1<<STATUS_DEPTH)-1;
     reg  [31:0] ram [0:DATA_2DEPTH];
-    reg         [DATA_DEPTH-1:0] waddr;
-    wire        [DATA_DEPTH-1:0] raddr;
+    reg         [STATUS_DEPTH-1:0] waddr;
+    wire        [STATUS_DEPTH-1:0] raddr;
     reg                          we;
     wire                         re;
     reg                  [31: 0] wdata;
@@ -55,7 +55,7 @@ module  status_read#(
     reg                   [3:0]  dstb;
     
     assign re= pre_stb && (((axi_pre_addr ^ STATUS_ADDR) & STATUS_ADDR_MASK) == 0);
-    assign raddr=axi_pre_addr[DATA_DEPTH-1:0];
+    assign raddr=axi_pre_addr[STATUS_DEPTH-1:0];
     assign start=rq && !rq_r;
     
     always @ (posedge rst or posedge clk) begin
@@ -70,7 +70,7 @@ module  status_read#(
         else            dstb <= {dstb[2:0],~rq_r};
         // byte 0 - address
         if (rst)        waddr <= 0;
-        else if (start) waddr <= ad[DATA_DEPTH-1:0];
+        else if (start) waddr <= ad[STATUS_DEPTH-1:0];
         
         // byte 1 - 2 payload bits and sequence number
         // 6 bits of the sequence number will go to bits 26.. 31

util_modules/mcont_from_chnbuf_reg.v

+/*******************************************************************************
+ * Module: mcont_from_chnbuf_reg
+ * Date:2015-01-19  
+ * Author: andrey     
+ * Description: Registering data from channel buffer to memory controller
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * mcont_from_chnbuf_reg.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  mcont_from_chnbuf_reg.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  mcont_from_chnbuf_reg #(
+    parameter CHN_NUMBER=0,
+    parameter CHN_LATENCY=0 // 0 - no extra latency in extrenal BRAM - data available next cycle after re (but prev. data)
+)(
+    input rst,
+    input clk,
+    input                       ext_buf_rd,
+    input                 [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
+    input                 [3:0] ext_buf_rchn,   // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
+    output reg           [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
+    output reg                  buf_rd_chn,
+    output reg            [6:0] buf_raddr_chn,
+    input                [63:0] buf_rdata_chn
+);
+    reg                 buf_chn_sel;
+    reg [CHN_LATENCY:0] latency_reg=0;
+    always @ (posedge rst or posedge clk) begin
+        if (rst) buf_chn_sel <= 0;
+        else  buf_chn_sel <= (ext_buf_rchn==CHN_NUMBER);
+        
+        if (rst) buf_rd_chn <= 0;
+        else buf_rd_chn <= buf_chn_sel && ext_buf_rd;
+        
+        if (rst) latency_reg<= 0;
+        else     latency_reg <= buf_rd_chn | (latency_reg << 1); 
+    end
+    always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
+    always @ (posedge clk) if (latency_reg[CHN_LATENCY])  ext_buf_rdata <= buf_rdata_chn;
+endmodule
+

util_modules/mcont_to_chnbuf_reg.v

+/*******************************************************************************
+ * Module: mcont_to_chnbuf_reg
+ * Date:2015-01-19  
+ * Author: andrey     
+ * Description: Registering data from memory controller to channel buffer
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * mcont_to_chnbuf_reg.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  mcont_to_chnbuf_reg.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  mcont_to_chnbuf_reg #(
+parameter CHN_NUMBER=0
+)(
+    input rst,
+    input clk,
+    input                       ext_buf_wr,
+    input                 [6:0] ext_buf_waddr,  // valid with ext_buf_wr
+    input                 [3:0] ext_buf_wchn,   // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
+    input                [63:0] ext_buf_wdata,   // valid with ext_buf_wr
+    output reg                  buf_wr_chn,
+    output reg            [6:0] buf_waddr_chn,
+    output reg           [63:0] buf_wdata_chn
+);
+    reg buf_chn_sel;
+    always @ (posedge rst or negedge clk) begin
+        if (rst) buf_chn_sel <= 0;
+        else buf_chn_sel <= (ext_buf_wchn==CHN_NUMBER);
+        if (rst) buf_wr_chn <= 0;
+        else buf_wr_chn <= buf_chn_sel && ext_buf_wr;
+    end
+    always @ (negedge clk) if (buf_chn_sel && ext_buf_wr) begin
+        buf_waddr_chn <= ext_buf_waddr;
+        buf_wdata_chn <= ext_buf_wdata;
+    end
+endmodule
+

util_modules/status_generate.v

@@ -39,7 +39,7 @@ module  status_generate #(
 */
     localparam NUM_BYTES=(PAYLOAD_BITS+21)>>3;
     localparam ALIGNED_STATUS_WIDTH=((NUM_BYTES-2)<<3)+2; // 2 ->2,
-    // ugly solution to avoid warnings in unused branch
+    // ugly solution to avoid warnings in unused "if" branch
     localparam ALIGNED_STATUS_BIT_2=(ALIGNED_STATUS_WIDTH>2)?2:0;
     reg                 [1:0] mode;
     reg                 [5:0] seq;