util_modules · 1e517e82e8b53bef125e2036e73dd0610267f784 · Elphel / x393 · GitLab

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Added modules to convert 32-bit parallel writes to two registers to 8-bit wide... · 1e517e82

Andrey Filippov authored Jun 19, 2015

Added modules to convert 32-bit parallel writes to two registers to 8-bit wide network for writing consecutive locations in block memories

1e517e82

Name	Last commit	Last update
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clk_to_clk2x.v		Loading commit data...
cmd_deser.v		Loading commit data...
dly01_16.v		Loading commit data...
dly_16.v		Loading commit data...
fifo_1cycle.v		Loading commit data...
fifo_2regs.v		Loading commit data...
fifo_cross_clocks.v		Loading commit data...
fifo_same_clock.v		Loading commit data...
fifo_same_clock_fill.v		Loading commit data...
index_max_16.v		Loading commit data...
masked_max_reg.v		Loading commit data...
mcont_common_chnbuf_reg.v		Loading commit data...
mcont_from_chnbuf_reg.v		Loading commit data...
mcont_to_chnbuf_reg.v		Loading commit data...
multipulse_cross_clock.v		Loading commit data...
pri1hot16.v		Loading commit data...
pulse_cross_clock.v		Loading commit data...
status_generate.v		Loading commit data...
status_router16.v		Loading commit data...
status_router2.v		Loading commit data...
status_router4.v		Loading commit data...
status_router8.v		Loading commit data...
table_ad_receive.v		Loading commit data...
table_ad_transmit.v		Loading commit data...