continue editing (0a580f98) · Commits · Elphel / x393

address_map.txt

+17 −1

Original line number	Diff line number	Diff line
		//0x1080..10ff - 8- bit data - to set various delay values
		parameter DLY_LD = 'h080, // address to generate delay load
		parameter DLY_LD_MASK = 'h380, // address mask to generate delay load

		0x1000..103f - 0- bit data (set/reset)
		parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
		parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h3f0, // address mask to generate sequencer channel/run
		@@ -53,6 +57,17 @@
		parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2, // 10 bits refresh address in the sequencer (PL) memory
		parameter MCONTR_TOP_16BIT_STATUS_CNTRL= 'h3, // 8 bits - write to status control (and debug?)

		0x1100..11ff - 16-bit per-channel memory control
		0x1100..110f - control of memory channels 0,1 - PS-controlled sequences
		parameter MCNTRL_PS_ADDR= 'h100,
		parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
		0x1100 - MCNTRL_PS_EN_RST
		0x1101 - MCNTRL_PS_CMD
		0x1102 - MCNTRL_PS_STATUS_CNTRL
		parameter MCNTRL_PS_EN_RST= 'h0,
		parameter MCNTRL_PS_CMD= 'h1,
		parameter MCNTRL_PS_STATUS_CNTRL= 'h2,


		// Status read address
		parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers
		@@ -60,6 +75,7 @@
		parameter STATUS_DEPTH= 8, // 256 cells, maybe just 16..64 are enough?
		parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy
		parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
		parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2

		================================ OLD =======================================================
		Control addresses (in original ddrc_test01)

memctrl/memctrl16.v

+86 −69

File changed.

Preview size limit exceeded, changes collapsed.

util_modules/fifo_same_clock.v

+27 −15

Original line number	Diff line number	Diff line
		@@ -19,7 +19,7 @@
		* along with this program. If not, see <http://www.gnu.org/licenses/> .
		*******************************************************************************/
		`timescale 1ns/1ps
		`define DEBUG_FIFO 1
		//`define DEBUG_FIFO 1
		module fifo_same_clock
		#(
		parameter integer DATA_WIDTH=16,
		@@ -28,6 +28,7 @@ module fifo_same_clock
		(
		input rst, // reset, active high
		input clk, // clock - positive edge
		input sync_rst, // synchronously reset fifo;
		input we, // write enable
		input re, // read enable
		input [DATA_WIDTH-1:0] data_in, // input data
		@@ -72,27 +73,38 @@ module fifo_same_clock

		always @ (posedge clk or posedge rst) begin
		if (rst) fill <= 0;
		else if (sync_rst) fill <= 0;
		else fill <= next_fill;

		if (rst) wem <= 0;
		else if (sync_rst) wem <= 0;
		else wem <= we;

		if (rst) ram_nempty <= 0;
		else if (sync_rst) ram_nempty <= 0;
		else ram_nempty <= (next_fill != 0);

		if (rst) wa <= 0;
		else if (sync_rst) wa <= 0;
		else if (wem) wa <= wa+1;

		if (rst) ra <= 0;
		else if (sync_rst) ra <= 0;
		else if (rem) ra <= ra+1;
		else if (!ram_nempty) ra <= wa; // Just recover from bit errors

		if (rst) out_full <= 0;
		else if (sync_rst) out_full <= 0;
		else if (rem && ~re) out_full <= 1;
		else if (re && ~rem) out_full <= 0;

		`ifdef DEBUG_FIFO
		if (rst) wcount <= 0;
		else if (sync_rst) wcount <= 0;
		else if (we) wcount <= wcount + 1;

		if (rst) rcount <= 0;
		else if (sync_rst) rcount <= 0;
		else if (re) rcount <= rcount + 1;
		`endif
		end

util_modules/mcont_from_chnbuf_reg.v

+9 −4

Original line number	Diff line number	Diff line
		@@ -29,6 +29,8 @@ module mcont_from_chnbuf_reg #(
		input ext_buf_rd,
		input [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
		input [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
		input seq_done, // sequence done
		output reg buf_done, // sequence done for the specified channel
		output reg [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
		output reg buf_rd_chn,
		output reg [6:0] buf_raddr_chn,
		@@ -45,6 +47,9 @@ module mcont_from_chnbuf_reg #(

		if (rst) latency_reg<= 0;
		else latency_reg <= buf_rd_chn \| (latency_reg << 1);

		if (rst) buf_done <= 0;
		else buf_done <= buf_chn_sel && seq_done;
		end
		always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
		always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;

util_modules/mcont_to_chnbuf_reg.v

+9 −2

Original line number	Diff line number	Diff line
		@@ -29,6 +29,8 @@ parameter CHN_NUMBER=0
		input [6:0] ext_buf_waddr, // valid with ext_buf_wr
		input [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
		input [63:0] ext_buf_wdata, // valid with ext_buf_wr
		input seq_done, // sequence done
		output reg buf_done, // sequence done for the specified channel
		output reg buf_wr_chn,
		output reg [6:0] buf_waddr_chn,
		output reg [63:0] buf_wdata_chn
		@@ -37,8 +39,13 @@ parameter CHN_NUMBER=0
		always @ (posedge rst or negedge clk) begin
		if (rst) buf_chn_sel <= 0;
		else buf_chn_sel <= (ext_buf_wchn==CHN_NUMBER);

		if (rst) buf_wr_chn <= 0;
		else buf_wr_chn <= buf_chn_sel && ext_buf_wr;

		if (rst) buf_done <= 0;
		else buf_done <= buf_chn_sel && seq_done;

		end
		always @ (negedge clk) if (buf_chn_sel && ext_buf_wr) begin
		buf_waddr_chn <= ext_buf_waddr;

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