debugging hardware (c57b67b8) · Commits · Elphel / x393

.project

+17 −17

Original line number	Original line	Diff line number	Diff line
	@@ -52,87 +52,87 @@
	<link>		<link>
	<name>ise_logs/ISExst.log</name>		<name>ise_logs/ISExst.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/ise_logs/ISExst-20140531140025056.log</location>		<location>/data/vdt/vdt-projects/eddr3/ise_logs/ISExst-20140607155721361.log</location>
	</link>		</link>
	<link>		<link>
	<name>ise_state/eddr3-synth.tgz</name>		<name>ise_state/eddr3-synth.tgz</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/ise_state/eddr3-synth-20140531140025056.tgz</location>		<location>/data/vdt/vdt-projects/eddr3/ise_state/eddr3-synth-20140607155721361.tgz</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoBitstream.log</name>		<name>vivado_logs/VivadoBitstream.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140606182315739.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140607160728042.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140606182315739.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140607160728042.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140606182315739.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140607160728042.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140606182315739.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140607160728042.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140606182315739.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140607160728042.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140606182315739.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140607160728042.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140606182054344.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140607160650782.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140606182315739.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140607160728042.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140606182315739.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140607160728042.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportImplemented.log</name>		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140606182315739.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140607160728042.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportSynthesis.log</name>		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140606182315739.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140607160728042.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/eddr3-opt-phys.dcp</name>		<name>vivado_state/eddr3-opt-phys.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140606182315739.dcp</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140607160728042.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/eddr3-place.dcp</name>		<name>vivado_state/eddr3-place.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140606182315739.dcp</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140607160728042.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/eddr3-route.dcp</name>		<name>vivado_state/eddr3-route.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140606182315739.dcp</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140607160728042.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/eddr3-synth.dcp</name>		<name>vivado_state/eddr3-synth.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140606171026321.dcp</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140607005118430.dcp</location>
	</link>		</link>
	</linkedResources>		</linkedResources>
	</projectDescription>		</projectDescription>

ddrc_test01.v

+45 −109

Original line number	Original line	Diff line number	Diff line
	@@ -91,7 +91,7 @@ module ddrc_test01 #(
	parameter CKE_EN_REL_MASK = 'h3fe, // address mask for command/address outputs		parameter CKE_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
	parameter DCI_RST_REL = 'h02a, // address to activate('h82b)/deactivate('h82a) Zynq DCI calibrate circuitry		parameter DCI_RST_REL = 'h02a, // address to activate('h82b)/deactivate('h82a) Zynq DCI calibrate circuitry
	parameter DCI_RST_REL_MASK = 'h3fe, // address mask for DCI calibrate circuitry		parameter DCI_RST_REL_MASK = 'h3fe, // address mask for DCI calibrate circuitry
	parameter DLY_RST_REL = 'h02a, // address to activate('h82d)/deactivate('h82c) delay calibration circuitry		parameter DLY_RST_REL = 'h02c, // address to activate('h82d)/deactivate('h82c) delay calibration circuitry
	parameter DLY_RST_REL_MASK = 'h3fe, // address mask for delay calibration circuitry		parameter DLY_RST_REL_MASK = 'h3fe, // address mask for delay calibration circuitry
	parameter EXTRA_REL = 'h02e, // address to set extra parameters (currently just inv_clk_div)		parameter EXTRA_REL = 'h02e, // address to set extra parameters (currently just inv_clk_div)
	parameter EXTRA_REL_MASK = 'h3ff, // address mask for extra parameters		parameter EXTRA_REL_MASK = 'h3ff, // address mask for extra parameters
	@@ -134,10 +134,10 @@ module ddrc_test01 #(


	// AXI write interface signals		// AXI write interface signals
	(* keep = "true" *)		//(* keep = "true" *)
	wire axi_aclk; // clock - should be buffered		wire axi_aclk; // clock - should be buffered
	// wire axi_aresetn; // reset, active low		// wire axi_aresetn; // reset, active low
	(* dont_touch = "true" *)		//(* dont_touch = "true" *)
	wire axi_rst; // reset, active high		wire axi_rst; // reset, active high
	// AXI Write Address		// AXI Write Address
	wire [31:0] axi_awaddr; // AWADDR[31:0], input		wire [31:0] axi_awaddr; // AWADDR[31:0], input
	@@ -290,16 +290,7 @@ module ddrc_test01 #(
	wire refresh_set;		wire refresh_set;

	assign port0_rd_match=(((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);		assign port0_rd_match=(((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
	// assign en_cmd0_wr= axiwr_bram_wen && (axiwr_bram_waddr[11:10]==2'h1);
	// assign en_port0_rd= axird_bram_ren && (axird_bram_raddr[11:10]==2'h0);
	// assign en_port0_regen= axird_bram_regen && (axird_bram_raddr[11:10]==2'h0);
	// assign en_port1_wr= axiwr_bram_wen && (axiwr_bram_waddr[11:10]==2'h0);


	assign en_cmd0_wr= axiwr_bram_wen && (((axiwr_bram_waddr ^ CMD0_ADDR) & CMD0_ADDR_MASK)==0);		assign en_cmd0_wr= axiwr_bram_wen && (((axiwr_bram_waddr ^ CMD0_ADDR) & CMD0_ADDR_MASK)==0);

	// assign en_port0_rd= axird_bram_ren && (((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
	// assign en_port0_regen= axird_bram_regen && (((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
	assign en_port0_rd= axird_bram_ren && port0_rd_match;		assign en_port0_rd= axird_bram_ren && port0_rd_match;
	assign en_port0_regen= axird_bram_regen && port0_rd_match_r;		assign en_port0_regen= axird_bram_regen && port0_rd_match_r;

	@@ -311,6 +302,19 @@ module ddrc_test01 #(
	assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed		assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed

	assign locked=locked_mmcm && locked_pll;		assign locked=locked_mmcm && locked_pll;

			// Clock and reset from PS
			wire comb_rst=~frst[0] \| frst[1];
			reg axi_rst_pre=1'b1;

			always @(posedge comb_rst or posedge axi_aclk) begin
			if (comb_rst) axi_rst_pre <= 1'b1;
			else axi_rst_pre <= 1'b0;
			end

			BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
			BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));

	always @ (posedge axi_aclk) begin		always @ (posedge axi_aclk) begin
	port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle		port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle
	end		end
	@@ -323,31 +327,6 @@ always @ (posedge axi_rst or posedge axi_aclk) begin

	end		end

	// Clock and reset from PS
	reg frst_inv;
	always @ (negedge frst[0] or posedge axi_aclk) begin
	if (!frst[0]) frst_inv <= 1'b1;
	else frst_inv <= 1'b0;
	end

	/* Instance template for module PULLDOWN */
	PULLDOWN PULLDOWN_i (
	.O(MEMCLK) // output
	);
	wire dbg_clk; // = fclk[1] ^ MEMCLK;
	//BUFG dbg_clk_ii (.O(dbg_clk),.I(fclk[1] ^ MEMCLK));
	BUFG dbg_clk_ii (.O(dbg_clk),.I(MEMCLK));
	//(* dont_touch = "true" *)
	reg [7:0] dbg_toggle;
	//always @ (posedge axi_rst or posedge axi_aclk) begin
	wire dbg_rst=frst[1] && !frst[0];
	always @ (posedge dbg_rst or posedge dbg_clk) begin
	//always @ (posedge axi_rst or posedge dbg_clk) begin
	//always @ (posedge fclk[1]) begin
	if (dbg_rst) dbg_toggle <= 8'ha5;
	else dbg_toggle <= dbg_toggle+1; //dbg_toggle+1;
	end

	/*		/*
	dly_addr[1],		dly_addr[1],
	dly_addr[0],		dly_addr[0],
	@@ -357,104 +336,63 @@ end
	rst_in,		rst_in,
	dci_rst,		dci_rst,
	dly_rst		dly_rst

	*/		*/



	//MEMCLK		//MEMCLK
	wire [63:0] gpio_in;		wire [63:0] gpio_in;
	assign gpio_in={		assign gpio_in={
	16'b0,		16'b0,
	1'b1, // 1		1'b1, // 1
	MEMCLK, // 1/0? - external clock		MEMCLK, // 1/0? - external clock
	dbg_rst, // 1		1'b0, //
	fclk[1] ^ MEMCLK, //dbg_clk, // 0/1		1'b0, //

	frst[1], // 1 (follows)		frst[1], // 0 (follows)
	fclk[1:0], // 2'bXX (toggle)		fclk[1:0], // 2'bXX (toggle)
	axird_dev_busy, // 0		axird_dev_busy, // 0

	{frst[2]?8'h5a:{		4'b0, // 4'b0
	dbg_toggle[7:4], // 4'b1111 -> 4'ha

	dbg_toggle[3:0]}}, // 4'b1111 -> 4'ha		4'b0, // 4'b0

	tmp_debug[7:4], // 4'b0111 -> 4'bx00x		tmp_debug[7:4], // 4'b0111 -> 4'bx00x
	// dly_addr[1],		// dly_addr[1], 0
	// dly_addr[0],		// dly_addr[0], 0
	// clkin_stopped_mmcm,		// clkin_stopped_mmcm, 0
	// clkfb_stopped_mmcm,		// clkfb_stopped_mmcm, 0

	tmp_debug[3:0], // 4'b1100 -> 4'bxx00		tmp_debug[3:0], // 4'b1100 -> 4'bxx00
	// ddr_rst,		// ddr_rst, 1 1 4000609c -> 0 , 40006098 -> 1
	// rst_in,		// rst_in, 0 0
	// dci_rst,		// dci_rst, 0 1
	// dly_rst		// dly_rst 0 1

			phy_locked_mmcm, // 1 1
			phy_locked_pll, // 1 1
			phy_dly_ready, // 1 0
			phy_dci_ready, // 1 0

	phy_locked_mmcm, // 0 1		locked_mmcm, // 1 1
	phy_locked_pll, // 0 1		locked_pll, // 1 1
	phy_dly_ready, // 0 1		dly_ready, // 1 0
	phy_dci_ready, // 1 1		dci_ready, // 1 0

	locked_mmcm, // 0 1
	locked_pll, // 0 1
	dly_ready, // 0 1
	dci_ready, // 0 1

	ps_out[7:4], // 4'b0 input[7:0] 4'b0		ps_out[7:4], // 4'b0 input[7:0] 4'b0

	ps_out[3:0], // 4'b0 input[7:0] 4'b0		ps_out[3:0], // 4'b0 input[7:0] 4'b0

	run_busy, // input // 0		run_busy, // input // 0
	locked, // input // 0		locked, // input // 1
	ps_rdy, // input // 0		ps_rdy, // input // 1
	axi_arready, // 1		axi_arready, // 1

	axi_awready, // 1		axi_awready, // 1
	axi_wready, // 1		axi_wready, // 1
	axi_aclk, // 0/1		fclk[0], // 0/1
	axi_rst // 0		axi_rst_pre //axi_rst // 0
	};
	/*
	assign tmp_debug ={
	1'b1,
	clkin_stopped_mmcm,
	clkfb_stopped_mmcm,
	clk_in, // dbg_reg3,
	dbg_reg2,
	dbg_reg1,
	rst_in,
	dly_rst
	};		};

	*/		assign DUMMY_TO_KEEP = 1'b0; // dbg_toggle[0];
	//assign DUMMY_TO_KEEP = ^gpio_in[63:0]; // to keep PS7 signals from "optimization"
	assign DUMMY_TO_KEEP = dbg_toggle[0];
	/*
	.rdata (status_rdata[31:0]), // output[31:0]
	.busy (axird_dev_busy), // output
	// .run_done (run_done), // input
	.run_busy (run_busy), // input
	.locked (locked), // input
	.ps_rdy (ps_rdy), // input
	.ps_out (ps_out[7:0]) // input[7:0]

	*/

	/*
	`ifndef IVERILOG
	(* dont_touch = "true" *)
	`endif
	wire frst_inv= ~frst[0];
	*/

	//BUFG bufg_axi_rst_i (.O(axi_rst),.I(~frst[0]));
	//assign axi_rst=~frst[0];
	assign axi_rst=~frst[0] \|\| frst[1]; // prevent releasing reset before explicit command
	//BUFG bufg_axi_rst_i (.O(axi_rst),.I(frst_inv));
	BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));

	axibram_write #(		axibram_write #(
	.ADDRESS_BITS(AXI_WR_ADDR_BITS)		.ADDRESS_BITS(AXI_WR_ADDR_BITS)
	@@ -633,13 +571,11 @@ run_busy
	.need (refresh_need), // output		.need (refresh_need), // output
	.grant (refresh_grant) // input		.grant (refresh_grant) // input
	);		);

	always @(posedge axi_rst or posedge mclk) begin		always @(posedge axi_rst or posedge mclk) begin
	if (axi_rst) refresh_grant <= 0;		if (axi_rst) refresh_grant <= 0;
	refresh_grant <= !refresh_grant && refresh_en && !run_busy && !axi_run_seq && (refresh_need \|\| (refresh_want && !run_seq_rq_gen));		else refresh_grant <= !refresh_grant && refresh_en && !run_busy && !axi_run_seq && (refresh_need \|\| (refresh_want && !run_seq_rq_gen));
	end		end


	ddrc_status		ddrc_status
	// #(		// #(
	// .AXI_RD_ADDR_BITS (AXI_RD_ADDR_BITS),		// .AXI_RD_ADDR_BITS (AXI_RD_ADDR_BITS),

ddrc_test01_testbench.sav

+194 −21

File changed.

Preview size limit exceeded, changes collapsed.

phy/cmd_addr.v

+13 −5

Original line number	Original line	Diff line number	Diff line
	@@ -19,7 +19,10 @@
	* along with this program. If not, see <http://www.gnu.org/licenses/> .		* along with this program. If not, see <http://www.gnu.org/licenses/> .
	*******************************************************************************/		*******************************************************************************/
	`timescale 1ns/1ps		`timescale 1ns/1ps
			/*
			Currently ddr3_a, ddr3_ba, ddr_cke and ddr_odt do not change inside a 2-clock command cycle, so half register
			bits are removed during optimization
			*/
	module cmd_addr #(		module cmd_addr #(
	parameter IODELAY_GRP = "IODELAY_MEMORY",		parameter IODELAY_GRP = "IODELAY_MEMORY",
	parameter IOSTANDARD = "SSTL15",		parameter IOSTANDARD = "SSTL15",
	@@ -62,7 +65,8 @@ reg in_tri_r=1'b1; // or tri-state on reset?
	(* keep = "true" *) reg set_r=0;		(* keep = "true" *) reg set_r=0;
	reg [7:0] ld_dly_cmd=8'b0;		reg [7:0] ld_dly_cmd=8'b0;
	reg [ADDRESS_NUMBER-1:0] ld_dly_addr=0;		reg [ADDRESS_NUMBER-1:0] ld_dly_addr=0;
	wire [ADDRESS_NUMBER-1:0] decode_addr;		//wire [ADDRESS_NUMBER-1:0] decode_addr;
			wire [23:0] decode_addr24;
	wire [7:0] decode_sel={		wire [7:0] decode_sel={
	(dly_addr[2:0]==7)?1'b1:1'b0,		(dly_addr[2:0]==7)?1'b1:1'b0,
	(dly_addr[2:0]==6)?1'b1:1'b0,		(dly_addr[2:0]==6)?1'b1:1'b0,
	@@ -72,7 +76,10 @@ wire [7:0] decode_sel={
	(dly_addr[2:0]==2)?1'b1:1'b0,		(dly_addr[2:0]==2)?1'b1:1'b0,
	(dly_addr[2:0]==1)?1'b1:1'b0,		(dly_addr[2:0]==1)?1'b1:1'b0,
	(dly_addr[2:0]==0)?1'b1:1'b0};		(dly_addr[2:0]==0)?1'b1:1'b0};
			assign decode_addr24={
			(dly_addr[4:3] == 2'h2)?decode_sel[7:0]:8'h0,
			(dly_addr[4:3] == 2'h1)?decode_sel[7:0]:8'h0,
			(dly_addr[4:3] == 2'h0)?decode_sel[7:0]:8'h0};
	always @ (posedge clk_div or posedge rst) begin		always @ (posedge clk_div or posedge rst) begin
	if (rst) begin		if (rst) begin
	in_a_r <= 0; in_ba_r <= 6'b0;		in_a_r <= 0; in_ba_r <= 6'b0;
	@@ -89,7 +96,8 @@ always @ (posedge clk_div or posedge rst) begin
	dly_data_r<=dly_data;		dly_data_r<=dly_data;
	set_r<=set;		set_r<=set;
	ld_dly_cmd <= {8 { dly_addr[4] & dly_addr[3] & ld_delay}} & decode_sel[7:0];		ld_dly_cmd <= {8 { dly_addr[4] & dly_addr[3] & ld_delay}} & decode_sel[7:0];
	ld_dly_addr <= {(ADDRESS_NUMBER) {ld_delay}} & decode_addr;		// ld_dly_addr <= {(ADDRESS_NUMBER) {ld_delay}} & decode_addr;
			ld_dly_addr <= {(ADDRESS_NUMBER) {ld_delay}} & decode_addr24[ADDRESS_NUMBER-1:0];
	end		end
	end		end

	@@ -97,7 +105,7 @@ end
	generate		generate
	genvar i;		genvar i;
	for (i=0; i<ADDRESS_NUMBER; i=i+1) begin: addr_block		for (i=0; i<ADDRESS_NUMBER; i=i+1) begin: addr_block
	assign decode_addr[i]=(ld_dly_addr[4:0] == i)?1'b1:1'b0;		// assign decode_addr[i]=(ld_dly_addr[4:0] == i)?1'b1:1'b0;
	cmda_single #(		cmda_single #(
	.IODELAY_GRP(IODELAY_GRP),		.IODELAY_GRP(IODELAY_GRP),
	.IOSTANDARD(IOSTANDARD),		.IOSTANDARD(IOSTANDARD),

phy/ddrc_sequencer.v

+1 −4

Original line number	Original line	Diff line number	Diff line
	@@ -364,7 +364,7 @@ module ddrc_sequencer #(
	.CMD_DONE_BIT (CMD_DONE_BIT) // bit number (address) to signal sequence done		.CMD_DONE_BIT (CMD_DONE_BIT) // bit number (address) to signal sequence done

	) phy_cmd_i (		) phy_cmd_i (
	.SDRST (SDRST), // output ****************		.SDRST (SDRST), // output
	.SDCLK (SDCLK), // output		.SDCLK (SDCLK), // output
	.SDNCLK (SDNCLK), // output		.SDNCLK (SDNCLK), // output
	.SDA (SDA[ADDRESS_NUMBER-1:0]), // output[14:0]		.SDA (SDA[ADDRESS_NUMBER-1:0]), // output[14:0]
	@@ -403,15 +403,12 @@ module ddrc_sequencer #(

	.ps_rdy (ps_rdy), // output		.ps_rdy (ps_rdy), // output
	.ps_out (ps_out[7:0]), // output[7:0]		.ps_out (ps_out[7:0]), // output[7:0]
	/// debugging
	// .phy_cmd_word (32'h0), //phy_cmd_word[31:0]), // input[31:0]
	.phy_cmd_word (phy_cmd_word[31:0]), // input[31:0]		.phy_cmd_word (phy_cmd_word[31:0]), // input[31:0]
	.phy_cmd_nop (phy_cmd_nop), // output		.phy_cmd_nop (phy_cmd_nop), // output
	.phy_cmd_add_pause (phy_cmd_add_pause), // one pause cycle (for 8-bursts)		.phy_cmd_add_pause (phy_cmd_add_pause), // one pause cycle (for 8-bursts)
	.add_pause (add_pause),		.add_pause (add_pause),
	.pause_len (pause_len), // output [CMD_PAUSE_BITS-1:0]		.pause_len (pause_len), // output [CMD_PAUSE_BITS-1:0]
	.sequence_done (sequence_done), // output		.sequence_done (sequence_done), // output
	// .buf_addr (buf_addr[6:0]), // output[6:0]
	.buf_wdata (buf_wdata[63:0]), // output[63:0]		.buf_wdata (buf_wdata[63:0]), // output[63:0]
	.buf_rdata (buf_rdata[63:0]), // input[63:0]		.buf_rdata (buf_rdata[63:0]), // input[63:0]
	.buf_wr (buf_wr_ndly), // output		.buf_wr (buf_wr_ndly), // output

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