Added modules to convert 32-bit parallel writes to two registers to 8-bit wide... (40c24bfb) · Commits · Elphel / x393

compressor_jp/focus_sharp393.v

+38 −18

Original line number	Original line	Diff line number	Diff line
	@@ -30,10 +30,10 @@
	module focus_sharp393(		module focus_sharp393(
	input clk, // pixel clock, posedge		input clk, // pixel clock, posedge
	input en, // enable (0 resets)		input en, // enable (0 resets)
	input sclk, // system clock: twe, ta,tdi - valid @negedge (ra, tdi - 2 cycles ahead)		input mclk, // system clock to write tables
	input twe, // enable write to a table		input tser_we, // enable write to a table
	input [ 9:0] ta, // [9:0] table address		input tser_a_not_d, // address/not data distributed to submodules
	input [15:0] tdi, // [15:0] table data in (8 LSBs - quantization data)		input [ 7:0] tser_d, // byte-wide serialized tables address/data to submodules
	input [ 1:0] mode, // focus mode (combine image with focus info) - 0 - none, 1 - replace, 2 - combine all, 3 - combine woi		input [ 1:0] mode, // focus mode (combine image with focus info) - 0 - none, 1 - replace, 2 - combine all, 3 - combine woi
	input firsti, // first macroblock		input firsti, // first macroblock
	input lasti, // last macroblock		input lasti, // last macroblock
	@@ -105,6 +105,11 @@ module focus_sharp393(
	reg luma_dc_acc; // 1 cycle ahead of the luma DC component out (always combined with the WOI)		reg luma_dc_acc; // 1 cycle ahead of the luma DC component out (always combined with the WOI)
	reg was_last_luma;		reg was_last_luma;
	reg copy_acc_frame;		reg copy_acc_frame;

			wire twe;
			wire [15:0] tdi;
			wire [22:0] ta;

	assign fdo_minus_max[12:0]= {1'b0,fdo[11:0]}-{1'b0,quant_dc_tdo[15:5]};		assign fdo_minus_max[12:0]= {1'b0,fdo[11:0]}-{1'b0,quant_dc_tdo[15:5]};
	assign combined_qf[12:0]=stren?({quant_d[12:0]}+{1'b0,fdo[11:0]}): //original image plus positive		assign combined_qf[12:0]=stren?({quant_d[12:0]}+{1'b0,fdo[11:0]}): //original image plus positive
	({quant_d[12],quant_d[12:1]}+ // half original		({quant_d[12],quant_d[12:1]}+ // half original
	@@ -120,7 +125,7 @@ module focus_sharp393(
	end		end

	// writing window parameters in the last bank of a table		// writing window parameters in the last bank of a table
	always @ (negedge sclk) begin		always @ (posedge mclk) begin
	if (twe) begin		if (twe) begin
	wnd_reg[11:0] <= tdi[11:0] ;		wnd_reg[11:0] <= tdi[11:0] ;
	wnd_a <= ta[2:0];		wnd_a <= ta[2:0];
	@@ -228,6 +233,21 @@ module focus_sharp393(
	{2'b0,quant_dc_tdo[15:5]} :		{2'b0,quant_dc_tdo[15:5]} :
	pre_do[12:0];		pre_do[12:0];
	end		end

			table_ad_receive #(
			.MODE_16_BITS (1),
			.NUM_CHN (1)
			) table_ad_receive_i (
			.clk (mclk), // input
			.a_not_d (tser_a_not_d), // input
			.ser_d (tser_d), // input[7:0]
			.dv (tser_we), // input
			.ta (ta), // output[22:0]
			.td (tdi), // output[15:0]
			.twe (twe) // output
			);


	/*		/*
	MULT18X18SIO #(		MULT18X18SIO #(
	.AREG(1), // Enable the input registers on the A port (1=on, 0=off)		.AREG(1), // Enable the input registers on the A port (1=on, 0=off)
	@@ -306,9 +326,9 @@ module focus_sharp393(
	.ren (1'b1), // input		.ren (1'b1), // input
	.regen (1'b1), // input		.regen (1'b1), // input
	.data_out (tdo[15:0]), // output[31:0]		.data_out (tdo[15:0]), // output[31:0]
	.wclk (!sclk), // input		.wclk (mclk), // input
	.waddr ({ta[9:0]}), // input[8:0]		.waddr (ta[9:0]), // input[8:0]
	.we (!sclk), // input		.we (twe), // input
	.web (4'hf), // input[3:0]		.web (4'hf), // input[3:0]
	.data_in (tdi[15:0]) // input[31:0]		.data_in (tdi[15:0]) // input[31:0]
	);		);

compressor_jp/jp_channel.v

+31 −16

Original line number	Original line	Diff line number	Diff line
	@@ -341,17 +341,6 @@ module jp_channel#(
	wire quant_start;		wire quant_start;
	dly_16 #(.WIDTH(1)) i_quant_start (.clk(xclk),.rst(1'b0), .dly(0), .din(dct_pre_first_out), .dout(quant_start)); // dly=0+1		dly_16 #(.WIDTH(1)) i_quant_start (.clk(xclk),.rst(1'b0), .dly(0), .din(dct_pre_first_out), .dout(quant_start)); // dly=0+1

	// TODO: Change interface (first are negedge, twhe - @poswedge mclk
	wire twqe;
	wire twce;
	wire twfe; // focusing table write enable

	wire twhe; // now @posedge mclk


	wire [9:0] ta; // some use [8:0]
	wire [15:0] tdi;

	reg [ 2:0] cmprs_qpage_this;		reg [ 2:0] cmprs_qpage_this;
	wire first_block_quant;		wire first_block_quant;
	wire [12:0] quant_do;		wire [12:0] quant_do;
	@@ -370,14 +359,40 @@ module jp_channel#(
	else if (dct_start && color_first && (color_tn[2:0]==3'b001)) dcc_en <=1'b1; // 3'b001 - closer to the first "start" in quantizator		else if (dct_start && color_first && (color_tn[2:0]==3'b001)) dcc_en <=1'b1; // 3'b001 - closer to the first "start" in quantizator
	end		end


			wire table_a_not_d; // writing table address /not data (a[0] from cmd_deser)
			wire table_we; // writing to tables (decoded stb from cmd_deser)
			wire [31:0] table_di; // 32-bit data to write to tables (LSB first) - from cmd_deser
			wire tser_a_not_d; // address/not data distributed to submodules
			wire [ 7:0] tser_d; // byte-wide serialized tables address/data to submodules
			wire tser_qe; // write serialized table data to quantizer
			wire tser_ce; // write serialized table data to coring
			wire tser_fe; // write serialized table data to focusing
			wire tser_he; // write serialized table data to Huffman

			table_ad_transmit #(
			.NUM_CHANNELS(4),
			.ADDR_BITS(3)
			) table_ad_transmit_i (
			.clk (mclk), // input @posedge
			.a_not_d_in (table_a_not_d), // input writing table address /not data (a[0] from cmd_deser)
			.we (table_we), // input writing to tables (decoded stb from cmd_deser)
			.din (table_di), // input[31:0] 32-bit data to serialize/write to tables (LSB first) - from cmd_deser
			.ser_d (tser_d), // output[7:0] byte-wide serialized tables address/data to submodules
			.a_not_d (tser_a_not_d), // output reg address/not data distributed to submodules
			.chn_en ({tser_he,tser_fe,tser_ce,tser_qe}) // output[0:0] reg - table 1-hot select outputs
			);



	quantizer393 quantizer393_i (		quantizer393 quantizer393_i (
	.clk (xclk), // input		.clk (xclk), // input
	.en (frame_en), // input		.en (frame_en), // input
	.sclk (mclk), // input system clock, twqe, twce, ta,tdi - valid @posedge (ra, tdi - 2 cycles ahead (was negedge)		.mclk (mclk), // input system clock, twqe, twce, ta,tdi - valid @posedge (ra, tdi - 2 cycles ahead (was negedge)
	.twqe (twqe), // input enable write to a quantization table		.tser_qe (tser_qe), // input - write to a quantization table
	.twce (twce), // input enable write to a coring table		.tser_ce (tser_ce), // input - write to a coring table
	.ta (ta[8:0]), // input[8:0] table address		.tser_a_not_d (tser_a_not_d), // input - address/not data to tables
	.tdi (tdi), // input[15:0] data in (8 LSBs - quantization data - obsolete?)		.tser_d (tser_d), // input[7:0] - byte-wide data to tables
	.ctypei (component_color), // input component type input (Y/C)		.ctypei (component_color), // input component type input (Y/C)
	.dci (yc_avr), // input[8:0] - average value in a block - subtracted before DCT. now normal signed number		.dci (yc_avr), // input[8:0] - average value in a block - subtracted before DCT. now normal signed number
	.first_stb (first_block_color), // input - this is first stb pulse in a frame		.first_stb (first_block_color), // input - this is first stb pulse in a frame

compressor_jp/quantizer393.v

+45 −32

Original line number	Original line	Diff line number	Diff line
	@@ -32,11 +32,11 @@
	module quantizer393(		module quantizer393(
	input clk, // pixel clock, posedge		input clk, // pixel clock, posedge
	input en, // enable (0 resets counter)		input en, // enable (0 resets counter)
	input sclk, // system clock, twqe, twce, ta,tdi - valid @posedge (ra, tdi - 2 cycles ahead (was negedge)		input mclk, // system clock to write tables
	input twqe, // enable write to a quantization table		input tser_qe, // enable write to a quantization table
	input twce, // enable write to a coring table		input tser_ce, // enable write to a coring table
	input [ 8:0] ta, // [8:0] table address		input tser_a_not_d, // address/not data distributed to submodules
	input [15:0] tdi, // [15:0] table data in (8 LSBs - quantization data)		input [ 7:0] tser_d, // byte-wide serialized tables address/data to submodules
	input ctypei, // component type input (Y/C)		input ctypei, // component type input (Y/C)
	input [ 8:0] dci, // [7:0] - average value in a block - subtracted before DCT. now normal signed number		input [ 8:0] dci, // [7:0] - average value in a block - subtracted before DCT. now normal signed number
	input first_stb, //this is first stb pulse in a frame		input first_stb, //this is first stb pulse in a frame
	@@ -101,8 +101,6 @@ module quantizer393(
	reg hfc_copy; // copy hfc_acc to dcc_acc		reg hfc_copy; // copy hfc_acc to dcc_acc
	wire [10:0] d2_dct; // 11 bits enough, convetred to positive (before - 0 was in the middle - pixel value 128) - dcc only		wire [10:0] d2_dct; // 11 bits enough, convetred to positive (before - 0 was in the middle - pixel value 128) - dcc only
	reg sel_satnum; // select saturation numbers - dcc only		reg sel_satnum; // select saturation numbers - dcc only
	reg twqe_d; //twqe delayed (write MSW)
	reg twce_d; //twce delayed (write MSW)
	reg [15:0] pre_dc_tdo;		reg [15:0] pre_dc_tdo;
	wire copy_dc_tdo;		wire copy_dc_tdo;

	@@ -230,10 +228,25 @@ module quantizer393(
	dcc_vld <= (dcc_run && dcc_stb && (ctype \|\| ctype_prev[0] \|\| sel_satnum)) \|\| hfc_copy;		dcc_vld <= (dcc_run && dcc_stb && (ctype \|\| ctype_prev[0] \|\| sel_satnum)) \|\| hfc_copy;
	end		end

	always @ (posedge sclk) begin		wire twqe;
	twqe_d <= twqe;		wire twce;
	twce_d <= twce;		wire [15:0] tdi;
	end		wire [22:0] ta;


			table_ad_receive #( // here may be changed to 8-bit from 16-bit
			.MODE_16_BITS (1),
			.NUM_CHN (2)
			) table_ad_receive_i (
			.clk (mclk), // input
			.a_not_d (tser_a_not_d), // input
			.ser_d (tser_d), // input[7:0]
			.dv ({tser_ce,tser_qe}), // input[1:0]
			.ta (ta), // output[22:0]
			.td (tdi), // output[15:0]
			.twe ({twce,twqe}) // output[1:0]
			);


	// SRL16 i_hfc_en (.Q(hfc_en), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(clk),		// SRL16 i_hfc_en (.Q(hfc_en), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(clk),
	// .D(((tba[2:0]>hfc_sel[2:0]) \|\| (tba[5:3]>hfc_sel[2:0])) && dcc_run && !ctype_prev[0])); // dly=1+1		// .D(((tba[2:0]>hfc_sel[2:0]) \|\| (tba[5:3]>hfc_sel[2:0])) && dcc_run && !ctype_prev[0])); // dly=1+1
	@@ -260,9 +273,9 @@ module quantizer393(
	.ren (1'b1), // input		.ren (1'b1), // input
	.regen (1'b1), // input		.regen (1'b1), // input
	.data_out (tdo[15:0]), // output[15:0]		.data_out (tdo[15:0]), // output[15:0]
	.wclk (sclk), // input		.wclk (mclk), // input
	.waddr ({ta[8:0],twqe_d}), // input[8:0]		.waddr (ta[9:0]), // input[8:0]
	.we (twqe \|\| twqe_d), // input		.we (twqe), // input
	.web (4'hf), // input[3:0]		.web (4'hf), // input[3:0]
	.data_in (tdi[15:0]) // input[15:0]		.data_in (tdi[15:0]) // input[15:0]
	);		);
	@@ -278,9 +291,9 @@ module quantizer393(
	.ren (1'b1), // input		.ren (1'b1), // input
	.regen (1'b1), // input		.regen (1'b1), // input
	.data_out (tdco[3:0]), // output[3:0]		.data_out (tdco[3:0]), // output[3:0]
	.wclk (sclk), // input		.wclk (mclk), // input
	.waddr ({ta[8:0],twce_d}), // input[9:0]		.waddr (ta[9:0]), // input[9:0]
	.we (twce \|\| twce_d), // input		.we (twce), // input
	.web (4'hf), // input[3:0]		.web (4'hf), // input[3:0]
	.data_in (tdi[15:0]) // input[15:0]		.data_in (tdi[15:0]) // input[15:0]
	);		);
	@@ -292,15 +305,15 @@ module quantizer393(
	.DUMMY (0)		.DUMMY (0)
	) i_zigzagbuf (		) i_zigzagbuf (
	.rclk (clk), // input		.rclk (clk), // input
	.raddr ({3'b0,rpage,zra[5:0]}), // input[8:0]		.raddr ({3'b0,rpage,zra[5:0]}), // input[9:0]
	.ren (next_dv), // input		.ren (next_dv), // input
	.regen (1'b1), // input		.regen (1'b1), // input
	.data_out (zigzag_q[15:0]), // output[31:0]		.data_out (zigzag_q[15:0]), // output[15:0]
	.wclk (clk), // input		.wclk (clk), // input
	.waddr ({3'b0,wpage,zwa[5:0]}), // input[8:0]		.waddr ({3'b0,wpage,zwa[5:0]}), // input[9:0]
	.we (zwe), // input		.we (zwe), // input
	.web (4'hf), // input[3:0]		.web (4'hf), // input[3:0]
	.data_in ({3'b0,qdo[12:0]}) // input[31:0]		.data_in ({3'b0,qdo[12:0]}) // input[15:0]
	);		);

util_modules/table_ad_receive.v

+4 −4

Original line number	Original line	Diff line number	Diff line
	@@ -22,12 +22,12 @@

	module table_ad_receive #(		module table_ad_receive #(
	parameter MODE_16_BITS = 1,		parameter MODE_16_BITS = 1,
	parameter NUM_CHN = 2		parameter NUM_CHN = 1
	)(		)(
	input clk, // posedge mclk		input clk, // posedge mclk
	input a_not_d, // receiving adderass / not data - valid during all bytes		input a_not_d, // receiving adderass / not data - valid during all bytes
	input [7:0] ser_d, // byte-wide address/data		input [7:0] ser_d, // byte-wide address/data
	input [NUM_CHN-1:0] en, // stb, // single-cycle strobe marking the first byte of adderss/data burst		input [NUM_CHN-1:0] dv, // data valid - active for each address or data bytes
	output [23-MODE_16_BITS:0] ta, // table address		output [23-MODE_16_BITS:0] ta, // table address
	output [(MODE_16_BITS?15:7):0] td, // 8/16 bit table data		output [(MODE_16_BITS?15:7):0] td, // 8/16 bit table data
	output [NUM_CHN-1:0] twe // table write enable		output [NUM_CHN-1:0] twe // table write enable
	@@ -43,8 +43,8 @@ module table_ad_receive #(

	always @(posedge clk) begin		always @(posedge clk) begin
	// twe_r <= en && !a_not_d;		// twe_r <= en && !a_not_d;
	twe_r <= a_not_d ? 0 : en;		twe_r <= a_not_d ? 0 : dv;
	if ((\|en) && a_not_d) addr_r[23:0] <= {ser_d,addr_r[23:8]};		if ((\|dv) && a_not_d) addr_r[23:0] <= {ser_d,addr_r[23:8]};
	else if (\|twe_r) addr_r[23:0] <= addr_r[23:0] + 1;		else if (\|twe_r) addr_r[23:0] <= addr_r[23:0] + 1;
	end		end
	generate		generate

util_modules/table_ad_transmit.v

+8 −8

Original line number	Original line	Diff line number	Diff line
	@@ -23,7 +23,8 @@
	`timescale 1ns/1ps		`timescale 1ns/1ps

	module table_ad_transmit#(		module table_ad_transmit#(
	parameter NUM_CHANNELS = 1		parameter NUM_CHANNELS = 1,
			parameter ADDR_BITS=4
	)(		)(
	input clk, // posedge mclk		input clk, // posedge mclk
	input a_not_d_in, // address/not data input (valid @ we)		input a_not_d_in, // address/not data input (valid @ we)
	@@ -31,12 +32,12 @@ module table_ad_transmit#(
	input [31:0] din, // 32 bit data to send or 8-bit channel select concatenated with 24-bit byte adderss (@we)		input [31:0] din, // 32 bit data to send or 8-bit channel select concatenated with 24-bit byte adderss (@we)
	output [ 7:0] ser_d, // 8-bit adderss/data to be sent to submodules that have table write port(s)		output [ 7:0] ser_d, // 8-bit adderss/data to be sent to submodules that have table write port(s)
	output reg a_not_d, // sending adderass / not data - valid during all bytes		output reg a_not_d, // sending adderass / not data - valid during all bytes
	output reg [NUM_CHANNELS-1:0] chn_stb // sending LSB (first) of address data (other bytes to follow)		output reg [NUM_CHANNELS-1:0] chn_en // sending address or data
	);		);
	wire [NUM_CHANNELS-1:0] sel;		wire [NUM_CHANNELS-1:0] sel;
	reg [31:0] d_r;		reg [31:0] d_r;
	reg any_en;		reg any_en;
	reg [7:0] sel_a;		reg [ADDR_BITS-1:0] sel_a;
	reg we_r;		reg we_r;
	wire we3;		wire we3;

	@@ -51,13 +52,12 @@ module table_ad_transmit#(
	we_r <= we && a_not_d_in;		we_r <= we && a_not_d_in;

	if ((we && !a_not_d_in) \|\| we_r) any_en <= 1;		if ((we && !a_not_d_in) \|\| we_r) any_en <= 1;
	// else if (we3) any_en <= 0;		else if (we3) any_en <= 0;
	else any_en <= 0;

	if ((we && !a_not_d_in) \|\| we_r) chn_stb <= sel;		if ((we && !a_not_d_in) \|\| we_r) chn_en <= sel;
	else if (we3) chn_stb <= 0;		else if (we3) chn_en <= 0;

	if (we && a_not_d_in) sel_a <= din[31:24];		if (we && a_not_d_in) sel_a <= din[24+:ADDR_BITS];

	end		end
	dly_16 #(.WIDTH(1)) i_end_burst(.clk(clk),.rst(1'b0), .dly(2), .din(we), .dout(we3)); // dly=2+1=3		dly_16 #(.WIDTH(1)) i_end_burst(.clk(clk),.rst(1'b0), .dly(2), .din(we), .dout(we3)); // dly=2+1=3

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