moved buffer adddress away from sequencer, continue ot memory controller top module (db31f7a9) · Commits · Elphel / x393

memctrl/cmd_encod_tiled_rd.v

+2 −0

Original line number	Diff line number	Diff line
		@@ -137,6 +137,8 @@ module cmd_encod_tiled_rd #(
		assign pre_act= rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE
		assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command

		//TODO:Add AUTOPRECHARGE + ACTIVATE when column crossed - No, caller should make sure there is no row address change in the same line

		always @ (posedge rst or posedge clk) begin
		if (rst) gen_run <= 0;
		else if (start) gen_run<= 1;

memctrl/mcntrl393.v

+54 −12

Original line number	Diff line number	Diff line
		@@ -297,7 +297,8 @@ module mcntrl393 #(
		wire seq_set0;
		wire seq_done0;
		wire buf_wr_chn0;
		wire [6:0] buf_waddr_chn0;
		wire buf_waddr_rst_chn0;
		// wire [6:0] buf_waddr_chn0;
		wire [63:0] buf_wdata_chn0;

		wire want_rq1;
		@@ -308,7 +309,8 @@ module mcntrl393 #(
		// wire seq_set1; // not used
		wire seq_done1;
		wire buf_rd_chn1;
		wire [6:0] buf_raddr_chn1;
		wire buf_raddr_rst_chn1;
		// wire [6:0] buf_raddr_chn1;
		wire [63:0] buf_rdata_chn1;

		wire want_rq2;
		@@ -319,7 +321,8 @@ module mcntrl393 #(
		wire seq_set2x; // may be shared with other channel
		wire seq_done2;
		wire buf_wr_chn2;
		wire [6:0] buf_waddr_chn2;
		wire buf_waddr_rst_chn2;
		// wire [6:0] buf_waddr_chn2;
		wire [63:0] buf_wdata_chn2;

		wire want_rq3;
		@@ -330,7 +333,8 @@ module mcntrl393 #(
		wire seq_set3x; // may be shared with other channel
		wire seq_done3;
		wire buf_rd_chn3;
		wire [6:0] buf_raddr_chn3;
		wire buf_raddr_rst_chn3;
		// wire [6:0] buf_raddr_chn3;
		wire [63:0] buf_rdata_chn3;

		wire want_rq4;
		@@ -341,7 +345,8 @@ module mcntrl393 #(
		wire seq_set4;
		wire seq_done4;
		wire buf_wr_chn4;
		wire [6:0] buf_waddr_chn4;
		wire buf_waddr_rst_chn4;
		// wire [6:0] buf_waddr_chn4;
		wire [63:0] buf_wdata_chn4;

		// Command tree - insert register layer if needed
		@@ -571,6 +576,7 @@ module mcntrl393 #(

		// Port memory buffer (4 pages each, R/W fixed, port 0 - AXI read from DDR, port 1 - AXI write to DDR
		// Port 2 (read DDR to AXI) buffer
		/*
		ram_512x64w_1kx32r #(
		.REGISTERS(1)
		) chn2_buf_i (
		@@ -585,8 +591,25 @@ module mcntrl393 #(
		.web (8'hff), // input[7:0]
		.data_in (buf_wdata_chn2) // input[63:0] @negedge mclk
		);
		*/
		/* Instance template for module mcntrl_1kx32r */
		mcntrl_1kx32r chn2_buf_i (
		.ext_clk (axi_clk), // input
		.ext_raddr (buf_raddr), // input[9:0]
		.ext_rd (buf2_rd), // input
		.ext_regen (buf2_regen), // input
		.ext_data_out (buf2_data), // output[31:0]
		.wclk (!mclk), // input
		.wpage (xfer_page2), // input[1:0]
		.waddr_reset (buf_waddr_rst_chn2), // input
		.skip_reset (1'b0), // input
		.we (buf_wr_chn2), // input
		.data_in (buf_wdata_chn2) // input[63:0]
		);


		// Port 3 (write DDR from AXI) buffer
		/*
		ram_1kx32w_512x64r #(
		.REGISTERS(1)
		) chn3_buf_i (
		@@ -601,6 +624,20 @@ module mcntrl393 #(
		.web (4'hf), // input[3:0]
		.data_in (buf_wdata) // input[31:0]
		);
		*/
		/* Instance template for module mcntrl_1kx32w */
		mcntrl_1kx32w chn3_buf_i (
		.ext_clk(axi_clk), // input
		.ext_waddr(buf_waddr), // input[9:0]
		.ext_we(buf3_we), // input
		.ext_data_in(buf_wdata), // input[31:0] buf_wdata - from AXI
		.rclk(mclk), // input
		.rpage(xfer_page3), // input[1:0]
		.raddr_reset(buf_raddr_rst_chn3), // input
		.skip_reset(1'b0), // input
		.rd(buf_rd_chn3), // input
		.data_out(buf_rdata_chn3) // output[63:0]
		);

		/* Instance template for module mcntrl_linear_rw */
		mcntrl_linear_rw #(
		@@ -790,7 +827,7 @@ module mcntrl393 #(
		.seq_set0 (seq_set0), // output
		.seq_done0 (seq_done0), // input
		.buf_wr_chn0 (buf_wr_chn0), // input @negedge mclk
		.buf_waddr_chn0 (buf_waddr_chn0), // input[6:0] @negedge mclk
		.buf_waddr_rst_chn0 (buf_waddr_rst_chn0), // input @negedge mclk
		.buf_wdata_chn0 (buf_wdata_chn0), // input[63:0]@negedge mclk

		.want_rq1 (want_rq1), // output reg
		@@ -798,7 +835,7 @@ module mcntrl393 #(
		.channel_pgm_en1 (channel_pgm_en1), // input
		.seq_done1 (seq_done1), // input
		.buf_rd_chn1 (buf_rd_chn1), // input
		.buf_raddr_chn1 (buf_raddr_chn1), // input[6:0]
		.buf_raddr_rst_chn1 (buf_raddr_rst_chn1), // input
		.buf_rdata_chn1 (buf_rdata_chn1) // output[63:0]
		);

		@@ -896,7 +933,8 @@ module mcntrl393 #(
		.seq_set0 (seq_set0), // input
		.seq_done0 (seq_done0), // output
		.buf_wr_chn0 (buf_wr_chn0), // output
		.buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
		.buf_waddr_rst_chn0 (buf_waddr_rst_chn0), // output
		// .buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
		.buf_wdata_chn0 (buf_wdata_chn0), // output[63:0]

		.want_rq1 (want_rq1), // input
		@@ -907,7 +945,8 @@ module mcntrl393 #(
		.seq_set1 (1'b0), // not used: seq_set1), // input
		.seq_done1 (seq_done1), // output
		.buf_rd_chn1 (buf_rd_chn1), // output
		.buf_raddr_chn1 (buf_raddr_chn1), // output[6:0]
		.buf_raddr_rst_chn1 (buf_raddr_rst_chn1), // output
		// .buf_raddr_chn1 (buf_raddr_chn1), // output[6:0]
		.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]

		.want_rq2 (want_rq2), // input
		@@ -918,7 +957,8 @@ module mcntrl393 #(
		.seq_set2 (seq_set2x), // input
		.seq_done2 (seq_done2), // output
		.buf_wr_chn2 (buf_wr_chn2), // output
		.buf_waddr_chn2 (buf_waddr_chn2), // output[6:0]
		.buf_waddr_rst_chn2 (buf_waddr_rst_chn2), // output
		// .buf_waddr_chn2 (buf_waddr_chn2), // output[6:0]
		.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]

		.want_rq3 (want_rq3), // input
		@@ -929,7 +969,8 @@ module mcntrl393 #(
		.seq_set3 (seq_set3x), // input
		.seq_done3 (seq_done3), // output
		.buf_rd_chn3 (buf_rd_chn3), // output
		.buf_raddr_chn3 (buf_raddr_chn3), // output[6:0]
		.buf_raddr_rst_chn3 (buf_raddr_rst_chn3), // output
		// .buf_raddr_chn3 (buf_raddr_chn3), // output[6:0]
		.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]

		.want_rq4 (want_rq4), // input
		@@ -940,7 +981,8 @@ module mcntrl393 #(
		.seq_set4 (seq_set4), // input
		.seq_done4 (seq_done4), // output
		.buf_wr_chn4 (buf_wr_chn4), // output
		.buf_waddr_chn4 (buf_waddr_chn4), // output[6:0]
		.buf_waddr_rst_chn4 (buf_waddr_rst_chn4), // output
		// .buf_waddr_chn4 (buf_waddr_chn4), // output[6:0]
		.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]

		.SDRST (SDRST), // output

memctrl/mcntrl_1kx32r.v

0 → 100644

+62 −0

Original line number	Diff line number	Diff line
		/*******************************************************************************
		* Module: mcntrl_1kx32r
		* Date:2015-02-03
		* Author: andrey
		* Description: Paged buffer for ddr3 controller read channel
		* with address autoincrement. 32 bit external data.
		*
		* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
		* mcntrl_1kx32r.v is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation, either version 3 of the License, or
		* (at your option) any later version.
		*
		* mcntrl_1kx32r.v is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program. If not, see <http://www.gnu.org/licenses/> .
		*******************************************************************************/
		`timescale 1ns/1ps

		module mcntrl_1kx32r(
		input ext_clk,
		input [ 9:0] ext_raddr, // read address
		input ext_rd, // read port enable
		input ext_regen, // output register enable
		output [31:0] ext_data_out, // data out

		input wclk, // !mclk (inverted)
		input [1:0] wpage, // will register to wclk, input OK with mclk
		input waddr_reset, // reset write buffer address (to page start), sync to wclk (!mclk)
		input skip_reset, // ignore waddr_reset (resync to wclk)
		input we, // write port enable (also increment write buffer address)
		input [63:0] data_in // data in
		);
		reg [1:0] wpage_wclk;
		reg skip_reset_wclk;
		reg [6:0] waddr;
		always @ (posedge wclk) begin
		wpage_wclk <= wpage;
		skip_reset_wclk <= skip_reset;
		if (waddr_reset && !skip_reset_wclk) waddr <= 0;
		else if (we) waddr <= waddr +1;
		end
		ram_512x64w_1kx32r #(
		.REGISTERS(1)
		) ram_512x64w_1kx32r_i (
		.rclk (ext_clk), // input
		.raddr (ext_raddr), // input[9:0]
		.ren (ext_rd), // input
		.regen (ext_regen), // input
		.data_out (ext_data_out), // output[31:0]
		.wclk (wclk), // input - OK, negedge mclk
		.waddr ({wpage_wclk,waddr}), // input[8:0] @negedge mclk
		.we (we), // input @negedge mclk
		.web (8'hff), // input[7:0]
		.data_in (data_in) // input[63:0] @negedge mclk
		);
		endmodule

memctrl/mcntrl_1kx32w.v

0 → 100644

+66 −0

Original line number	Diff line number	Diff line
		/*******************************************************************************
		* Module: mcntrl_1kx32w
		* Date:2015-02-03
		* Author: andrey
		* Description: Paged buffer for ddr3 controller write channel
		* with address autoincrement. 32 bit external data. Extends rd to regen
		*
		* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
		* mcntrl_1kx32w.v is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation, either version 3 of the License, or
		* (at your option) any later version.
		*
		* mcntrl_1kx32w.v is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program. If not, see <http://www.gnu.org/licenses/> .
		*******************************************************************************/
		`timescale 1ns/1ps

		module mcntrl_1kx32w(
		input ext_clk,
		input [ 9:0] ext_waddr, // external write address
		input ext_we, // external write enable
		input [31:0] ext_data_in, // data input

		input rclk, // mclk
		input [1:0] rpage, // will register to wclk, input OK with mclk
		input raddr_reset, // reset buffer read address (to page start)
		input skip_reset, // ignore waddr_reset (resync to wclk)
		input rd, // read buffer tomemory, increment read address (regester enable will be delayed)
		output [63:0] data_out // data out

		);
		reg skip_reset_rclk;
		reg [6:0] raddr;
		reg regen;
		always @ (posedge rclk) begin
		regen <= rd;

		skip_reset_rclk <= skip_reset;

		if (raddr_reset && !skip_reset_rclk) raddr <= 0;
		else if (rd) raddr <= raddr +1;
		end
		ram_1kx32w_512x64r #(
		.REGISTERS(1)
		)ram_1kx32w_512x64r_i (
		.rclk (rclk), // input
		.raddr ({rpage,raddr}), // input[8:0]
		.ren (rd), // input
		.regen (regen), // input
		.data_out (data_out), // output[63:0]
		.wclk (ext_clk), // input
		.waddr (ext_waddr), // input[9:0]
		.we (ext_we), // input
		.web (4'hf), // input[3:0]
		.data_in (ext_data_in) // input[31:0]
		);


		endmodule

memctrl/mcntrl_ps_pio.v

+35 −2

Original line number	Diff line number	Diff line
		@@ -61,7 +61,8 @@ module mcntrl_ps_pio#(
		output seq_set0,
		input seq_done0,
		input buf_wr_chn0,
		input [6:0] buf_waddr_chn0,
		input buf_waddr_rst_chn0,
		// input [6:0] buf_waddr_chn0,
		input [63:0] buf_wdata_chn0,
		// write port 1
		output reg want_rq1,
		@@ -72,7 +73,8 @@ module mcntrl_ps_pio#(
		// output seq_set1, // connect externally to seq_set0
		input seq_done1,
		input buf_rd_chn1,
		input [6:0] buf_raddr_chn1,
		input buf_raddr_rst_chn1,
		// input [6:0] buf_raddr_chn1,
		output [63:0] buf_rdata_chn1
		);
		localparam CMD_WIDTH=14;
		@@ -214,6 +216,7 @@ fifo_same_clock #(


		// Port 0 (read DDR to AXI) buffer
		/*
		ram_512x64w_1kx32r #(
		.REGISTERS(1)
		) port0_buf_i (
		@@ -228,8 +231,23 @@ fifo_same_clock #(
		.web (8'hff), // input[7:0]
		.data_in (buf_wdata_chn0) // input[63:0]
		);
		*/
		mcntrl_1kx32r chn0_buf_i (
		.ext_clk (port0_clk), // input
		.ext_raddr (port0_addr), // input[9:0]
		.ext_rd (port0_re), // input
		.ext_regen (port0_regen), // input
		.ext_data_out (port0_data), // output[31:0]
		.wclk (!mclk), // input
		.wpage (page), // input[1:0]
		.waddr_reset (buf_waddr_rst_chn0), // input
		.skip_reset (1'b0), // input
		.we (buf_wr_chn0), // input
		.data_in (buf_wdata_chn0) // input[63:0]
		);

		// Port 1 (write DDR from AXI) buffer
		/*
		ram_1kx32w_512x64r #(
		.REGISTERS(1)
		) port1_buf_i (
		@@ -244,5 +262,20 @@ fifo_same_clock #(
		.web (4'hf), // input[3:0]
		.data_in (port1_data) // input[31:0]
		);
		*/
		mcntrl_1kx32w chn1_buf_i (
		.ext_clk (port1_clk), // input
		.ext_waddr (port1_addr), // input[9:0]
		.ext_we (port1_we), // input
		.ext_data_in (port1_data), // input[31:0] buf_wdata - from AXI
		.rclk (mclk), // input
		.rpage (page), // input[1:0]
		.raddr_reset (buf_raddr_rst_chn1), // input
		.skip_reset (1'b0), // input
		.rd (buf_rd_chn1), // input
		.data_out (buf_rdata_chn1) // output[63:0]
		);


		endmodule

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