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Elphel
x393
Commits
94f77f4d
Commit
94f77f4d
authored
Feb 01, 2015
by
Andrey Filippov
Browse files
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Plain Diff
started top module for memory controller with channle buffers, added cascaded status multiplexers
parent
0adb43af
Changes
9
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Showing
9 changed files
with
1657 additions
and
29 deletions
+1657
-29
.editor_defines
.editor_defines
+4
-2
cmd_encod_linear_mux.v
memctrl/cmd_encod_linear_mux.v
+113
-26
cmd_encod_tiled_mux.v
memctrl/cmd_encod_tiled_mux.v
+380
-0
cmd_encod_tiled_rd.v
memctrl/cmd_encod_tiled_rd.v
+0
-1
mcntrl393.v
memctrl/mcntrl393.v
+577
-0
status_router16.v
util_modules/status_router16.v
+165
-0
status_router4.v
util_modules/status_router4.v
+94
-0
status_router8.v
util_modules/status_router8.v
+116
-0
x393.v
x393.v
+208
-0
No files found.
.editor_defines
View file @
94f77f4d
...
...
@@ -23,8 +23,10 @@
`undef def_read_mem_chn3
`define def_scanline_chn3
// chn 4 is disabled
`undef def_enable_mem_chn4
// chn 4 is enabled
`define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_tiled_chn4
// chn 5 is disabled
`undef def_enable_mem_chn5
...
...
memctrl/cmd_encod_linear_mux.v
View file @
94f77f4d
...
...
@@ -3,7 +3,7 @@
* Date:2015-01-31
* Author: andrey
* Description: Multiplex parameters from multiple channels sharing the same
* linear command encoder
(cmd_encod_linear_rd or
cmd_encod_linear_wr)
* linear command encoder
s (cmd_encod_linear_rd and
cmd_encod_linear_wr)
* Latency 1 clcok cycle
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
...
...
@@ -145,86 +145,173 @@ module cmd_encod_linear_mux#(
output
[
ADDRESS_NUMBER
-
1
:
0
]
row
,
// memory row
output
[
COLADDR_NUMBER
-
4
:
0
]
start_col
,
// start memory column in 8-bursts
output
[
5
:
0
]
num128
,
// number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
output
start
// start generating commands
output
start_rd
,
// start generating commands in cmd_encod_linear_rd
output
start_wr
// start generating commands in cmd_encod_linear_wr
)
;
reg
[
2
:
0
]
bank_r
;
// bank address
reg
[
ADDRESS_NUMBER
-
1
:
0
]
row_r
;
// memory row
reg
[
COLADDR_NUMBER
-
4
:
0
]
start_col_r
;
// start memory column in 8-bursts
reg
[
5
:
0
]
num128_r
;
// number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
reg
start_r
;
// start generating commands
reg
start_rd_r
;
// start generating commands
reg
start_wr_r
;
// start generating commands
wire
[
2
:
0
]
bank_w
;
// bank address
wire
[
ADDRESS_NUMBER
-
1
:
0
]
row_w
;
// memory row
wire
[
COLADDR_NUMBER
-
4
:
0
]
start_col_w
;
// start memory column in 8-bursts
wire
[
5
:
0
]
num128_w
;
// number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire
start_w
;
// start generating commands
wire
start_rd_w
;
// start generating commands
wire
start_wr_w
;
// start generating commands
localparam
PAR_WIDTH
=
3
+
ADDRESS_NUMBER
+
COLADDR_NUMBER
-
3
+
6
+
1
;
localparam
PAR_WIDTH
=
3
+
ADDRESS_NUMBER
+
COLADDR_NUMBER
-
3
+
6
+
2
;
localparam
[
PAR_WIDTH
-
1
:
0
]
PAR_DEFAULT
=
0
;
assign
bank
=
bank_r
;
assign
row
=
row_r
;
assign
start_col
=
start_col_r
;
assign
num128
=
num128_r
;
assign
start
=
start_r
;
assign
{
bank_w
,
row_w
,
start_col_w
,
num128_w
,
start_w
}
=
0
assign
start_rd
=
start_rd_r
;
assign
start_wr
=
start_wr_r
;
localparam
[
15
:
0
]
CHN_RD_MEM
={
`ifdef
def_read_mem_chn15
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn14
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn13
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn12
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn11
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn10
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn9
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn8
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn7
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn6
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn5
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn4
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn3
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn2
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn1
1'b1
,
`else
1'b0
,
`endif
`ifdef
def_read_mem_chn0
1'b1
};
`else
1'b0
};
`endif
assign
{
bank_w
,
row_w
,
start_col_w
,
num128_w
,
start_rd_w
,
start_wr_w
}
=
0
`ifdef
def_scanline_chn0
|
(
start0
?{
bank0
,
row0
,
start_col0
,
num128_0
,
1'b1
}:
PAR_DEFAULT
)
|
(
start0
?{
bank0
,
row0
,
start_col0
,
num128_0
,
CHN_RD_MEM
[
0
]
,~
CHN_RD_MEM
[
0
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn1
|
(
start1
?{
bank1
,
row1
,
start_col1
,
num128_1
,
1'b1
}:
PAR_DEFAULT
)
|
(
start1
?{
bank1
,
row1
,
start_col1
,
num128_1
,
CHN_RD_MEM
[
1
]
,~
CHN_RD_MEM
[
1
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn2
|
(
start2
?{
bank2
,
row2
,
start_col2
,
num128_2
,
1'b1
}:
PAR_DEFAULT
)
|
(
start2
?{
bank2
,
row2
,
start_col2
,
num128_2
,
CHN_RD_MEM
[
2
]
,~
CHN_RD_MEM
[
2
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn3
|
(
start3
?{
bank3
,
row3
,
start_col3
,
num128_3
,
1'b1
}:
PAR_DEFAULT
)
|
(
start3
?{
bank3
,
row3
,
start_col3
,
num128_3
,
CHN_RD_MEM
[
3
]
,~
CHN_RD_MEM
[
3
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn4
|
(
start4
?{
bank4
,
row4
,
start_col4
,
num128_4
,
1'b1
}:
PAR_DEFAULT
)
|
(
start4
?{
bank4
,
row4
,
start_col4
,
num128_4
,
CHN_RD_MEM
[
4
]
,~
CHN_RD_MEM
[
4
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn5
|
(
start5
?{
bank5
,
row5
,
start_col5
,
num128_5
,
1'b1
}:
PAR_DEFAULT
)
|
(
start5
?{
bank5
,
row5
,
start_col5
,
num128_5
,
CHN_RD_MEM
[
5
]
,~
CHN_RD_MEM
[
5
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn6
|
(
start6
?{
bank6
,
row6
,
start_col6
,
num128_6
,
1'b1
}:
PAR_DEFAULT
)
|
(
start6
?{
bank6
,
row6
,
start_col6
,
num128_6
,
CHN_RD_MEM
[
6
]
,~
CHN_RD_MEM
[
6
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn7
|
(
start7
?{
bank7
,
row7
,
start_col7
,
num128_7
,
1'b1
}:
PAR_DEFAULT
)
|
(
start7
?{
bank7
,
row7
,
start_col7
,
num128_7
,
CHN_RD_MEM
[
7
]
,~
CHN_RD_MEM
[
7
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn8
|
(
start8
?{
bank8
,
row8
,
start_col8
,
num128_8
,
1'b1
}:
PAR_DEFAULT
)
|
(
start8
?{
bank8
,
row8
,
start_col8
,
num128_8
,
CHN_RD_MEM
[
8
]
,~
CHN_RD_MEM
[
8
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn9
|
(
start9
?{
bank9
,
row9
,
start_col9
,
num128_9
,
1'b1
}:
PAR_DEFAULT
)
|
(
start9
?{
bank9
,
row9
,
start_col9
,
num128_9
,
CHN_RD_MEM
[
9
]
,~
CHN_RD_MEM
[
9
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn10
|
(
start10
?{
bank10
,
row10
,
start_col10
,
num128_10
,
1'b1
}:
PAR_DEFAULT
)
|
(
start10
?{
bank10
,
row10
,
start_col10
,
num128_10
,
CHN_RD_MEM
[
10
]
,~
CHN_RD_MEM
[
10
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn11
|
(
start11
?{
bank11
,
row11
,
start_col11
,
num128_11
,
1'b1
}:
PAR_DEFAULT
)
|
(
start11
?{
bank11
,
row11
,
start_col11
,
num128_11
,
CHN_RD_MEM
[
11
]
,~
CHN_RD_MEM
[
11
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn12
|
(
start12
?{
bank12
,
row12
,
start_col12
,
num128_12
,
1'b1
}:
PAR_DEFAULT
)
|
(
start12
?{
bank12
,
row12
,
start_col12
,
num128_12
,
CHN_RD_MEM
[
12
]
,~
CHN_RD_MEM
[
12
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn13
|
(
start13
?{
bank13
,
row13
,
start_col13
,
num128_13
,
1'b1
}:
PAR_DEFAULT
)
|
(
start13
?{
bank13
,
row13
,
start_col13
,
num128_13
,
CHN_RD_MEM
[
13
]
,~
CHN_RD_MEM
[
13
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn14
|
(
start14
?{
bank14
,
row14
,
start_col14
,
num128_14
,
1'b1
}:
PAR_DEFAULT
)
|
(
start14
?{
bank14
,
row14
,
start_col14
,
num128_14
,
CHN_RD_MEM
[
14
]
,~
CHN_RD_MEM
[
14
]
}:
PAR_DEFAULT
)
`endif
`ifdef
def_scanline_chn15
|
(
start15
?{
bank15
,
row15
,
start_col15
,
num128_15
,
1'b1
}:
PAR_DEFAULT
)
|
(
start15
?{
bank15
,
row15
,
start_col15
,
num128_15
,
CHN_RD_MEM
[
15
]
,~
CHN_RD_MEM
[
15
]
}:
PAR_DEFAULT
)
`endif
;
always
@
(
posedge
clk
)
begin
if
(
start_w
)
begin
if
(
start_
rd_w
||
start_wr_
w
)
begin
bank_r
<=
bank_w
;
row_r
<=
row_w
;
start_col_r
<=
start_col_w
;
num128_r
<=
num128_w
;
end
start_r
<=
start_w
;
start_rd_r
<=
start_rd_w
;
start_wr_r
<=
start_wr_w
;
end
...
...
memctrl/cmd_encod_tiled_mux.v
0 → 100644
View file @
94f77f4d
This diff is collapsed.
Click to expand it.
memctrl/cmd_encod_tiled_rd.v
View file @
94f77f4d
...
...
@@ -48,7 +48,6 @@ module cmd_encod_tiled_rd #(
input
[
5
:
0
]
num_rows_in_m1
,
// number of rows to read minus 1
input
[
5
:
0
]
num_cols_in_m1
,
// number of 16-pixel columns to read (rows first, then columns) - 1
input
keep_open_in
,
// keep banks open (for <=8 banks only
input
start
,
// start generating commands
output
reg
[
31
:
0
]
enc_cmd
,
// encoded commnad
output
reg
enc_wr
,
// write encoded command
...
...
memctrl/mcntrl393.v
0 → 100644
View file @
94f77f4d
This diff is collapsed.
Click to expand it.
util_modules/status_router16.v
0 → 100644
View file @
94f77f4d
/*******************************************************************************
* Module: status_router16
* Date:2015-01-31
* Author: andrey
* Description: Routes status data from 16 sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* status_router16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* status_router16.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
status_router16
(
input
rst
,
input
clk
,
// 4 input channels
input
[
7
:
0
]
db_in0
,
input
rq_in0
,
output
start_in0
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in1
,
input
rq_in1
,
output
start_in1
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in2
,
input
rq_in2
,
output
start_in2
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in3
,
input
rq_in3
,
output
start_in3
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in4
,
input
rq_in4
,
output
start_in4
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in5
,
input
rq_in5
,
output
start_in5
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in6
,
input
rq_in6
,
output
start_in6
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in7
,
input
rq_in7
,
output
start_in7
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in8
,
input
rq_in8
,
output
start_in8
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in9
,
input
rq_in9
,
output
start_in9
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in10
,
input
rq_in10
,
output
start_in10
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in11
,
input
rq_in11
,
output
start_in11
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in12
,
input
rq_in12
,
output
start_in12
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in13
,
input
rq_in13
,
output
start_in13
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in14
,
input
rq_in14
,
output
start_in14
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in15
,
input
rq_in15
,
output
start_in15
,
// only for the first cycle, combinatorial
// output (multiplexed) channel
output
[
7
:
0
]
db_out
,
output
rq_out
,
input
start_out
// only for the first cycle, combinatorial
)
;
wire
[
7
:
0
]
db_int
[
1
:
0
]
;
wire
[
1
:
0
]
rq_int
;
wire
[
1
:
0
]
start_int
;
// only for the first cycle, combinatorial
status_router2
status_router2_top_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
db_in0
(
db_int
[
0
])
,
// input[7:0]
.
rq_in0
(
rq_int
[
0
])
,
// input
.
start_in0
(
start_int
[
0
])
,
// output
.
db_in1
(
db_int
[
1
])
,
// input[7:0]
.
rq_in1
(
rq_int
[
1
])
,
// input
.
start_in1
(
start_int
[
1
])
,
// output
.
db_out
(
db_out
)
,
// output[7:0]
.
rq_out
(
rq_out
)
,
// output
.
start_out
(
start_out
)
// input
)
;
status_router8
status_router8_01234567_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
db_in0
(
db_in0
)
,
// input[7:0]
.
rq_in0
(
rq_in0
)
,
// input
.
start_in0
(
start_in0
)
,
// output
.
db_in1
(
db_in1
)
,
// input[7:0]
.
rq_in1
(
rq_in1
)
,
// input
.
start_in1
(
start_in1
)
,
// output
.
db_in2
(
db_in2
)
,
// input[7:0]
.
rq_in2
(
rq_in2
)
,
// input
.
start_in2
(
start_in2
)
,
// output
.
db_in3
(
db_in3
)
,
// input[7:0]
.
rq_in3
(
rq_in3
)
,
// input
.
start_in3
(
start_in3
)
,
// output
.
db_in4
(
db_in4
)
,
// input[7:0]
.
rq_in4
(
rq_in4
)
,
// input
.
start_in4
(
start_in4
)
,
// output
.
db_in5
(
db_in5
)
,
// input[7:0]
.
rq_in5
(
rq_in5
)
,
// input
.
start_in5
(
start_in5
)
,
// output
.
db_in6
(
db_in6
)
,
// input[7:0]
.
rq_in6
(
rq_in6
)
,
// input
.
start_in6
(
start_in6
)
,
// output
.
db_in7
(
db_in7
)
,
// input[7:0]
.
rq_in7
(
rq_in7
)
,
// input
.
start_in7
(
start_in7
)
,
// output
.
db_out
(
db_int
[
0
])
,
// output[7:0]
.
rq_out
(
rq_int
[
0
])
,
// output
.
start_out
(
start_int
[
0
])
// input
)
;
status_router8
status_router8_89abcdef_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
db_in0
(
db_in8
)
,
// input[7:0]
.
rq_in0
(
rq_in8
)
,
// input
.
start_in0
(
start_in8
)
,
// output
.
db_in1
(
db_in9
)
,
// input[7:0]
.
rq_in1
(
rq_in9
)
,
// input
.
start_in1
(
start_in9
)
,
// output
.
db_in2
(
db_in10
)
,
// input[7:0]
.
rq_in2
(
rq_in10
)
,
// input
.
start_in2
(
start_in10
)
,
// output
.
db_in3
(
db_in11
)
,
// input[7:0]
.
rq_in3
(
rq_in11
)
,
// input
.
start_in3
(
start_in11
)
,
// output
.
db_in4
(
db_in12
)
,
// input[7:0]
.
rq_in4
(
rq_in12
)
,
// input
.
start_in4
(
start_in12
)
,
// output
.
db_in5
(
db_in13
)
,
// input[7:0]
.
rq_in5
(
rq_in13
)
,
// input
.
start_in5
(
start_in13
)
,
// output
.
db_in6
(
db_in14
)
,
// input[7:0]
.
rq_in6
(
rq_in14
)
,
// input
.
start_in6
(
start_in14
)
,
// output
.
db_in7
(
db_in15
)
,
// input[7:0]
.
rq_in7
(
rq_in15
)
,
// input
.
start_in7
(
start_in15
)
,
// output
.
db_out
(
db_int
[
1
])
,
// output[7:0]
.
rq_out
(
rq_int
[
1
])
,
// output
.
start_out
(
start_int
[
1
])
// input
)
;
endmodule
util_modules/status_router4.v
0 → 100644
View file @
94f77f4d
/*******************************************************************************
* Module: status_router4
* Date:2015-01-31
* Author: andrey
* Description: Routes status data from 4 sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* status_router4.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* status_router4.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
status_router4
(
input
rst
,
input
clk
,
// 4 input channels
input
[
7
:
0
]
db_in0
,
input
rq_in0
,
output
start_in0
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in1
,
input
rq_in1
,
output
start_in1
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in2
,
input
rq_in2
,
output
start_in2
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in3
,
input
rq_in3
,
output
start_in3
,
// only for the first cycle, combinatorial
// output (multiplexed) channel
output
[
7
:
0
]
db_out
,
output
rq_out
,
input
start_out
// only for the first cycle, combinatorial
)
;
wire
[
7
:
0
]
db_int
[
1
:
0
]
;
wire
[
1
:
0
]
rq_int
;
wire
[
1
:
0
]
start_int
;
// only for the first cycle, combinatorial
status_router2
status_router2_top_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
db_in0
(
db_int
[
0
])
,
// input[7:0]
.
rq_in0
(
rq_int
[
0
])
,
// input
.
start_in0
(
start_int
[
0
])
,
// output
.
db_in1
(
db_int
[
1
])
,
// input[7:0]
.
rq_in1
(
rq_int
[
1
])
,
// input
.
start_in1
(
start_int
[
1
])
,
// output
.
db_out
(
db_out
)
,
// output[7:0]
.
rq_out
(
rq_out
)
,
// output
.
start_out
(
start_out
)
// input
)
;
status_router2
status_router2_01_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
db_in0
(
db_in0
)
,
// input[7:0]
.
rq_in0
(
rq_in0
)
,
// input
.
start_in0
(
start_in0
)
,
// output
.
db_in1
(
db_in1
)
,
// input[7:0]
.
rq_in1
(
rq_in1
)
,
// input
.
start_in1
(
start_in1
)
,
// output
.
db_out
(
db_int
[
0
])
,
// output[7:0]
.
rq_out
(
rq_int
[
0
])
,
// output
.
start_out
(
start_int
[
0
])
// input
)
;
status_router2
status_router2_23_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
db_in0
(
db_in2
)
,
// input[7:0]
.
rq_in0
(
rq_in2
)
,
// input
.
start_in0
(
start_in2
)
,
// output
.
db_in1
(
db_in3
)
,
// input[7:0]
.
rq_in1
(
rq_in3
)
,
// input
.
start_in1
(
start_in3
)
,
// output
.
db_out
(
db_int
[
1
])
,
// output[7:0]
.
rq_out
(
rq_int
[
1
])
,
// output
.
start_out
(
start_int
[
1
])
// input
)
;
endmodule
util_modules/status_router8.v
0 → 100644
View file @
94f77f4d
/*******************************************************************************
* Module: status_router8
* Date:2015-01-31
* Author: andrey
* Description: Routes status data from 8 sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* status_router8.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* status_router8.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
status_router8
(
input
rst
,
input
clk
,
// 4 input channels
input
[
7
:
0
]
db_in0
,
input
rq_in0
,
output
start_in0
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in1
,
input
rq_in1
,
output
start_in1
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in2
,
input
rq_in2
,
output
start_in2
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in3
,
input
rq_in3
,
output
start_in3
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in4
,
input
rq_in4
,
output
start_in4
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in5
,
input
rq_in5
,
output
start_in5
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in6
,
input
rq_in6
,
output
start_in6
,
// only for the first cycle, combinatorial
input
[
7
:
0
]
db_in7
,
input
rq_in7
,
output
start_in7
,
// only for the first cycle, combinatorial
// output (multiplexed) channel
output
[
7
:
0
]
db_out
,
output
rq_out
,
input
start_out
// only for the first cycle, combinatorial
)
;
//TODO: now just uses 3 of status_router2 (tree) - maybe make a dedicated 4-input one?
wire
[
7
:
0
]
db_int
[
1
:
0
]
;
wire
[
1
:
0
]
rq_int
;
wire
[
1
:
0
]
start_int
;
// only for the first cycle, combinatorial
status_router2
status_router2_top_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
db_in0
(
db_int
[
0
])
,
// input[7:0]
.
rq_in0
(
rq_int
[
0
])
,
// input
.
start_in0
(
start_int
[
0
])
,
// output
.
db_in1
(
db_int
[
1
])
,
// input[7:0]
.
rq_in1
(
rq_int
[
1
])
,
// input
.
start_in1
(
start_int
[
1
])
,
// output
.
db_out
(
db_out
)
,
// output[7:0]
.
rq_out
(
rq_out
)
,
// output
.
start_out
(
start_out
)
// input
)
;
status_router4
status_router4_0123_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
db_in0
(
db_in0
)
,
// input[7:0]
.
rq_in0
(
rq_in0
)
,
// input
.
start_in0
(
start_in0
)
,
// output
.
db_in1
(
db_in1
)
,
// input[7:0]
.
rq_in1
(
rq_in1
)
,
// input
.
start_in1
(
start_in1
)
,
// output
.
db_in2
(
db_in2
)
,
// input[7:0]
.
rq_in2
(
rq_in2
)
,
// input
.
start_in2
(
start_in2
)
,
// output
.
db_in3
(
db_in3
)
,
// input[7:0]
.
rq_in3
(
rq_in3
)
,
// input
.
start_in3
(
start_in3
)
,
// output
.
db_out
(
db_int
[
0
])
,
// output[7:0]
.
rq_out
(
rq_int
[
0
])
,
// output
.
start_out
(
start_int
[
0
])
// input
)
;
status_router4
status_router4_4567_i
(
.
rst
(
rst
)
,
// input
.
clk
(
clk
)
,
// input
.
db_in0
(
db_in4
)
,
// input[7:0]
.
rq_in0
(
rq_in4
)
,
// input
.
start_in0
(
start_in4
)
,
// output
.
db_in1
(
db_in5
)
,
// input[7:0]
.
rq_in1
(
rq_in5
)
,
// input
.
start_in1
(
start_in5
)
,
// output
.
db_in2
(
db_in6
)
,
// input[7:0]
.
rq_in2
(
rq_in6
)
,
// input
.
start_in2
(
start_in6
)
,
// output
.
db_in3
(
db_in7
)
,
// input[7:0]
.
rq_in3
(
rq_in7
)
,
// input
.
start_in3
(
start_in7
)
,
// output
.
db_out
(
db_int
[
1
])
,
// output[7:0]
.
rq_out
(
rq_int
[
1
])
,
// output
.
start_out
(
start_int
[
1
])
// input
)
;
endmodule
x393.v
View file @
94f77f4d
...
...
@@ -531,6 +531,17 @@ end
wire
[
6
:
0
]
buf_raddr_chn3
;
wire
[
63
:
0
]
buf_rdata_chn3
;
wire
want_rq4
;
wire
need_rq4
;
wire
channel_pgm_en4
;
wire
[
31
:
0
]
seq_data4
;
wire
seq_wr4
;
wire
seq_set4
;
wire
seq_done4
;
wire
buf_wr_chn4
;
wire
[
6
:
0
]
buf_waddr_chn4
;
wire
[
63
:
0
]
buf_wdata_chn4
;
// memory controller comamnd encoders interface
wire
[
2
:
0
]
encod_linear_rd_bank
;
wire
[
ADDRESS_NUMBER
-
1
:
0
]
encod_linear_rd_row
;
...
...
@@ -672,6 +683,191 @@ end
.
enc_done
(
encod_linear_wr_done
)
// output reg
)
;
// TODO: Create module mcntrl393, incuding all of the mcntrl* modules and related buffers (will; need optional cross-clock (or they can be external?
// TODO: program inter-chennel synchronization (a separate module inside mcntrl393
// All cross-clock - external, buffer I/O sync to external clock
// *********************************** Move to mcntrl393 *********************************************
/* Instance template for module mcntrl_linear_rw */
mcntrl_linear_rw
#(
.
ADDRESS_NUMBER
(
15
)
,
.
COLADDR_NUMBER
(
10
)
,
.
NUM_XFER_BITS
(
6
)
,
.
FRAME_WIDTH_BITS
(
13
)
,
.
FRAME_HEIGHT_BITS
(
16
)
,
.
MCNTRL_SCANLINE_ADDR
(
'h120
)
,
.
MCNTRL_SCANLINE_MASK
(
'h3f0
)
,
.
MCNTRL_SCANLINE_MODE
(
'h0
)
,
.
MCNTRL_SCANLINE_STATUS_CNTRL
(
'h1
)
,
.
MCNTRL_SCANLINE_STARTADDR
(
'h2
)
,
.
MCNTRL_SCANLINE_FRAME_FULL_WIDTH
(
'h3
)
,
.
MCNTRL_SCANLINE_WINDOW_WH
(
'h4
)
,
.
MCNTRL_SCANLINE_WINDOW_X0Y0
(
'h5
)
,
.
MCNTRL_SCANLINE_WINDOW_STARTXY
(
'h6
)
,
.
MCNTRL_SCANLINE_STATUS_REG_ADDR
(
'h4
)
,
.
MCNTRL_SCANLINE_PENDING_CNTR_BITS
(
2
)
)
mcntrl_linear_rw_chn2_i
(
.
rst
()
,
// input
.
mclk
()
,
// input
.
cmd_ad
()
,
// input[7:0]
.
cmd_stb
()
,
// input
.
status_ad
()
,
// output[7:0]
.
status_rq
()
,
// output
.
status_start
()
,
// input
.
frame_start
()
,
// input
.
next_page
()
,
// input
.
frame_done
()
,
// output
.
line_unfinished
()
,
// output[15:0]
.
suspend
()
,
// input
.
xfer_want
()
,
// output
.
xfer_need
()
,
// output
.
xfer_grant
()
,
// input
.
xfer_start
()
,
// output
.
xfer_bank
()
,
// output[2:0]
.
xfer_row
()
,
// output[14:0]
.
xfer_col
()
,
// output[6:0]
.
xfer_num128
()
,
// output[5:0]
.
xfer_done
()
,
// input
.
xfer_page
()
// output[1:0]
)
;
/* Instance template for module mcntrl_linear_rw */
mcntrl_linear_rw
#(
.
ADDRESS_NUMBER
(
15
)
,
.
COLADDR_NUMBER
(
10
)
,
.
NUM_XFER_BITS
(
6
)
,
.
FRAME_WIDTH_BITS
(
13
)
,
.
FRAME_HEIGHT_BITS
(
16
)
,
.
MCNTRL_SCANLINE_ADDR
(
'h120
)
,
.
MCNTRL_SCANLINE_MASK
(
'h3f0
)
,
.
MCNTRL_SCANLINE_MODE
(
'h0
)
,
.
MCNTRL_SCANLINE_STATUS_CNTRL
(
'h1
)
,
.
MCNTRL_SCANLINE_STARTADDR
(
'h2
)
,
.
MCNTRL_SCANLINE_FRAME_FULL_WIDTH
(
'h3
)
,
.
MCNTRL_SCANLINE_WINDOW_WH
(
'h4
)
,
.
MCNTRL_SCANLINE_WINDOW_X0Y0
(
'h5
)
,
.
MCNTRL_SCANLINE_WINDOW_STARTXY
(
'h6
)
,
.
MCNTRL_SCANLINE_STATUS_REG_ADDR
(
'h4
)
,
.
MCNTRL_SCANLINE_PENDING_CNTR_BITS
(
2
)
)
mcntrl_linear_rw_chn3_i
(
.
rst
()
,
// input
.
mclk
()
,
// input
.
cmd_ad
()
,
// input[7:0]
.
cmd_stb
()
,
// input
.
status_ad
()
,
// output[7:0]
.
status_rq
()
,
// output
.
status_start
()
,
// input
.
frame_start
()
,
// input
.
next_page
()
,
// input
.
frame_done
()
,
// output
.
line_unfinished
()
,
// output[15:0]
.
suspend
()
,
// input
.
xfer_want
()
,
// output
.
xfer_need
()
,
// output
.
xfer_grant
()
,
// input
.
xfer_start
()
,
// output
.
xfer_bank
()
,
// output[2:0]
.
xfer_row
()
,
// output[14:0]