Commits · 5a276ebb3481656ef881153f6264792cb54b62bf · Elphel / x393

11 Jun, 2015 1 commit
- started porting jpeg/jp4 compressor code · 72dc592d
  Andrey Filippov authored 9 years ago
  
  72dc592d
06 May, 2015 1 commit
- Debugging hardware, added functionality to detect cache-related problems · cdf97c98
  Andrey Filippov authored 9 years ago
  
  cdf97c98
05 May, 2015 2 commits
- Fixed handling AXI write responce channel - both in work and simulation... · 988095ef
  Andrey Filippov authored 9 years ago
```
Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
```
  988095ef
- Fixed ddr3 -> system memory transfer · 0fda102e
  Andrey Filippov authored 9 years ago
  
  0fda102e
04 May, 2015 1 commit
- made membridge work in system -> videobuffer mode · 59a577c9
  Andrey Filippov authored 9 years ago
  
  59a577c9
03 May, 2015 1 commit
- preparing for testing membridge module on the target system · bda74800
  Andrey Filippov authored 9 years ago
  
  bda74800
30 Apr, 2015 1 commit
- simulating/debugging · 8b79e3f7
  Andrey Filippov authored 9 years ago
  
  8b79e3f7
28 Apr, 2015 1 commit
- Working on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp · 7a0fa46b
  Andrey Filippov authored 9 years ago
  
  7a0fa46b
22 Apr, 2015 1 commit
- bug fixes in Verilog code · 286a6494
  Andrey Filippov authored 9 years ago
  
  286a6494
18 Mar, 2015 1 commit
- testing hardware, adding related code · 7a0b9347
  Andrey Filippov authored 10 years ago
  
  7a0b9347
15 Mar, 2015 1 commit
- porting delay scan/adjustment functions from the eddr3 Python code · 6ff31a13
  Andrey Filippov authored 10 years ago
  
  6ff31a13
12 Mar, 2015 1 commit
- working on hardware testing, added utility functions to load bitstream and use GPIO for debugging · 27a6599b
  Andrey Filippov authored 10 years ago
  
  27a6599b
01 Mar, 2015 1 commit
- working with Xilinx ISE/Vivado to synthesize and P&R the design · 0466926c
  Andrey Filippov authored 10 years ago
  
  0466926c
28 Feb, 2015 1 commit
- working on synthesis with Vivado tools · 05378ee7
  Andrey Filippov authored 10 years ago
  
  05378ee7
11 Jan, 2015 1 commit
- more changes to convert project · 56a59c77
  Andrey Filippov authored 10 years ago
  
  56a59c77
12 Jun, 2014 1 commit
- implemented read leveling, eye measurement for DDR3 on random data · 2ac46e21
  Andrey Filippov authored 10 years ago
  
  2ac46e21
11 Jun, 2014 2 commits
- working with hardware · f2c019cd
  Andrey Filippov authored 10 years ago
  
  f2c019cd
- debugging hardware · 5450474d
  Andrey Filippov authored 10 years ago
  
  5450474d
08 Jun, 2014 1 commit
- organized new/debug files · 7e44243b
  Andrey Filippov authored 10 years ago
  
  7e44243b
07 Jun, 2014 2 commits
- debugging hardware · c57b67b8
  Andrey Filippov authored 10 years ago
  
  c57b67b8
- troubleshooting lack of DONE during loading of the bitfile · cd3ccb58
  Andrey Filippov authored 10 years ago
  
  cd3ccb58
02 Jun, 2014 1 commit
- fixed DCI and ODT for all tested modes · 6176aa7b
  Andrey Filippov authored 10 years ago
  
  6176aa7b
01 Jun, 2014 2 commits
- bug fixes, implemented read pattern test, so all major DDR3 modes are tested:... · 01028931
  Andrey Filippov authored 10 years ago
```
bug fixes, implemented read pattern test, so all major DDR3 modes are tested: write and read leveling, write and read
```
  01028931
- added configuration for ISE, timing constraints for Vivado · 46cf253d
  Andrey Filippov authored 10 years ago
  
  46cf253d
31 May, 2014 1 commit
- change DM* I/O standard to SSTL15 · 0bd9ef33
  Andrey Filippov authored 10 years ago
  
  0bd9ef33
28 May, 2014 1 commit
- debugging, next snapshot · 3d67d687
  Andrey Filippov authored 10 years ago
  
  3d67d687
22 May, 2014 2 commits
- debugging · 8b1e18d4
  Andrey Filippov authored 10 years ago
  
  8b1e18d4
- added modules, simulating · c8904b67
  Andrey Filippov authored 10 years ago
  
  c8904b67
15 May, 2014 2 commits
- moved files · c7b65d94
  Andrey Filippov authored 10 years ago
  
  c7b65d94
- working on ddr3 phy · c676b5f2
  Andrey Filippov authored 10 years ago
  
  c676b5f2
29 Apr, 2014 1 commit
- synchronizing with original repo · ea560b4a
  Andrey Filippov authored 10 years ago
  
  ea560b4a
26 Apr, 2014 1 commit
- new subproject · e61b4d60
  Andrey Filippov authored 10 years ago
  
  e61b4d60