Commit 6176aa7b authored by Andrey Filippov's avatar Andrey Filippov
Browse files

fixed DCI and ODT for all tested modes

parent 01028931

.project

+15 −15
Original line number Diff line number Diff line
@@ -56,77 +56,77 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140531223145240.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140602122428009.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140531223145240.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140602122428009.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140531223145240.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140602122428009.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140531223145240.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140602122428009.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140531223145240.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140602122428009.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140531223145240.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140602122428009.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140531222614445.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140602115135083.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140531223145240.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140602122428009.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140531222614445.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140602115135083.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140531223145240.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140602122428009.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140531222614445.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140602115135083.log</location>

		</link>

		<link>

			<name>vivado_state/eddr3-opt-phys.dcp</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140531223145240.dcp</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140602122428009.dcp</location>

		</link>

		<link>

			<name>vivado_state/eddr3-place.dcp</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140531223145240.dcp</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140602122428009.dcp</location>

		</link>

		<link>

			<name>vivado_state/eddr3-route.dcp</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140531223145240.dcp</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140602122428009.dcp</location>

		</link>

		<link>

			<name>vivado_state/eddr3-synth.dcp</name>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140531222614445.dcp</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140602115135083.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

ddrc_control.v

+34 −5
Original line number Diff line number Diff line
@@ -41,14 +41,19 @@ module ddrc_control #( 
    parameter WBUF_DELAY_REL_MASK =   'h3ff,  // address mask to set extra delay

    parameter PAGES_REL =             'h023,  // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}

    parameter PAGES_REL_MASK =        'h3ff,  // address mask to set DQM and DQS patterns

    parameter CMDA_EN_REL =           'h024,  // address to enable('h823)/disable('h822) command/address outputs  

    parameter CMDA_EN_REL =           'h024,  // address to enable('h825)/disable('h824) command/address outputs  

    parameter CMDA_EN_REL_MASK =      'h3fe,  // address mask for command/address outputs

    parameter SDRST_ACT_REL =         'h026,  // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory  

    parameter SDRST_ACT_REL =         'h026,  // address to activate('h827)/deactivate('h826) active-low reset signal to DDR3 memory  

    parameter SDRST_ACT_REL_MASK =    'h3fe,  // address mask for reset DDR3

    parameter CKE_EN_REL =            'h028,  // address to enable('h827)/disable('h826) CKE signal to memory   

    parameter CKE_EN_REL =            'h028,  // address to enable('h829)/disable('h828) CKE signal to memory   

    parameter CKE_EN_REL_MASK =       'h3fe,  // address mask for command/address outputs

    parameter EXTRA_REL =             'h02a,  // address to set extra parameters (currently just inv_clk_div)

    parameter DCI_RST_REL =           'h02a,  // address to activate('h82b)/deactivate('h82a) Zynq DCI calibrate circuitry  

    parameter DCI_RST_REL_MASK =      'h3fe,  // address mask for DCI calibrate circuitry

    parameter DLY_RST_REL =           'h02c,  // address to activate('h82d)/deactivate('h82c) delay calibration circuitry  

    parameter DLY_RST_REL_MASK =      'h3fe,  // address mask for delay calibration circuitry

    parameter EXTRA_REL =             'h02e,  // address to set extra parameters (currently just inv_clk_div)

    parameter EXTRA_REL_MASK =        'h3ff   // address mask for extra parameters

   

)(

    input                         clk,

    input                         mclk,
@@ -73,6 +78,8 @@ module ddrc_control #( 
// control: additional signals

    output                        cmda_en,  // tri-state all command and address lines to DDR chip

    output                        ddr_rst,  // generate DDR3 memory reset signal

    output                        dci_rst,  // active high - reset DCI circuitry

    output                        dly_rst,  // active high - delay calibration circuitry

    output                        ddr_cke,  // control DDR3 memory CKE signal

    

    output                        inv_clk_div, // invert clk_div to ISERDES
@@ -118,6 +125,13 @@ module ddrc_control #( 


    localparam SDRST_ACT_ADDR =     CONTROL_ADDR |      SDRST_ACT_REL;      // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory    

    localparam SDRST_ACT_ADDR_MASK =CONTROL_ADDR_MASK | SDRST_ACT_REL_MASK; // address mask for reset DDR3

    

    localparam DCI_RST_ADDR =       CONTROL_ADDR |      DCI_RST_REL;      // address to activate/deactivate Zynq DCI calibrate circuitry    

    localparam DCI_RST_ADDR_MASK =  CONTROL_ADDR_MASK | DCI_RST_REL_MASK; // address mask for DCI calibrate circuitry

    localparam DLY_RST_ADDR =       CONTROL_ADDR |      DLY_RST_REL;      // address to activate/deactivate delay calibration circuitry    

    localparam DLY_RST_ADDR_MASK =  CONTROL_ADDR_MASK | DLY_RST_REL_MASK; // address mask for delay calibration circuitry

    

    

    localparam CKE_EN_ADDR =        CONTROL_ADDR |      CKE_EN_REL;       // address to enable('h827)/disable('h826) CKE signal to memory  

    localparam CKE_EN_ADDR_MASK =   CONTROL_ADDR_MASK | CKE_EN_REL_MASK;  // address mask for CKE
@@ -147,6 +161,8 @@ module ddrc_control #( 
    reg                  [ 1:0] port1_int_page_r; // port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0) 

    reg                         cmda_en_r;        // enable (tri-state off) all command and address lines to DDR chip

    reg                         ddr_rst_r;        // generate DDR3 memory reset

    reg                         dci_rst_r;  // active high - reset DCI circuitry

    reg                         dly_rst_r;  // active high - reset delay calibration circuitry

    reg                         ddr_cke_r;         // enable CKE to memory



    reg                         inv_clk_div_r;    // invert clk_div to ISERDES
@@ -180,6 +196,9 @@ module ddrc_control #( 
    assign port1_int_page = port1_int_page_r[1:0];

    assign cmda_en =        cmda_en_r;

    assign ddr_rst =        ddr_rst_r;

    assign dci_rst =        dci_rst_r;

    assign dly_rst =        dly_rst_r;

    

    assign ddr_cke=         ddr_cke_r;

    assign inv_clk_div =    inv_clk_div_r;
@@ -235,6 +254,16 @@ module ddrc_control #( 
        else if (fifo_re && (((waddr_fifo_out ^ SDRST_ACT_ADDR) & SDRST_ACT_ADDR_MASK)==0))

                 ddr_rst_r <= waddr_fifo_out[0];



        if (rst) dci_rst_r <= 1'b0; // reset DCI circuitry off (it is ORed with rst later)

        else if (fifo_re && (((waddr_fifo_out ^ DCI_RST_ADDR) & DCI_RST_ADDR_MASK)==0))

                 dci_rst_r <= waddr_fifo_out[0];



        if (rst) dly_rst_r <= 1'b0; // reset DCI circuitry off (it is ORed with rst later)

        else if (fifo_re && (((waddr_fifo_out ^ DLY_RST_ADDR) & DLY_RST_ADDR_MASK)==0))

                 dly_rst_r <= waddr_fifo_out[0];







        if (rst) ddr_cke_r <= 1'b0;

        else if (fifo_re && (((waddr_fifo_out ^ CKE_EN_ADDR) & CKE_EN_ADDR_MASK)==0))

                 ddr_cke_r <= waddr_fifo_out[0];

ddrc_test01.v

+21 −4
Original line number Diff line number Diff line
@@ -83,13 +83,17 @@ module ddrc_test01 #( 
    parameter WBUF_DELAY_REL_MASK =   'h3ff,  // address mask to set extra delay

    parameter PAGES_REL =             'h023,  // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}

    parameter PAGES_REL_MASK =        'h3ff,  // address mask to set DQM and DQS patterns

    parameter CMDA_EN_REL =           'h024,  // address to enable('h823)/disable('h822) command/address outputs  

    parameter CMDA_EN_REL =           'h024,  // address to enable('h825)/disable('h824) command/address outputs  

    parameter CMDA_EN_REL_MASK =      'h3fe,  // address mask for command/address outputs

    parameter SDRST_ACT_REL =         'h026,  // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory  

    parameter SDRST_ACT_REL =         'h026,  // address to activate('h827)/deactivate('h826) active-low reset signal to DDR3 memory  

    parameter SDRST_ACT_REL_MASK =    'h3fe,  // address mask for reset DDR3

    parameter CKE_EN_REL =            'h028,  // address to enable('h827)/disable('h826) CKE signal to memory   

    parameter CKE_EN_REL =            'h028,  // address to enable('h829)/disable('h828) CKE signal to memory   

    parameter CKE_EN_REL_MASK =       'h3fe,  // address mask for command/address outputs

    parameter EXTRA_REL =             'h02a,  // address to set extra parameters (currently just inv_clk_div)

    parameter DCI_RST_REL =           'h02a,  // address to activate('h82b)/deactivate('h82a) Zynq DCI calibrate circuitry  

    parameter DCI_RST_REL_MASK =      'h3fe,  // address mask for DCI calibrate circuitry

    parameter DLY_RST_REL =           'h02a,  // address to activate('h82d)/deactivate('h82c) delay calibration circuitry  

    parameter DLY_RST_REL_MASK =      'h3fe,  // address mask for delay calibration circuitry

    parameter EXTRA_REL =             'h02e,  // address to set extra parameters (currently just inv_clk_div)

    parameter EXTRA_REL_MASK =        'h3ff   // address mask for extra parameters

)(

    // DDR3 interface
@@ -225,6 +229,11 @@ module ddrc_test01 #( 
// additional control signals

   wire        cmda_en; // enable DDR3 memory control and addreee outputs

   wire        ddr_rst; // generate DDR3 memory reset (active hight)

   wire        dci_rst;  // active high - reset DCI circuitry

   wire        dly_rst;  // active high - reset delay calibration circuitry

   

   

   

   wire        ddr_cke; // control of the DDR3 memory CKE signal

   

   wire        inv_clk_div; // input
@@ -384,6 +393,10 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); 
        .SDRST_ACT_REL_MASK(SDRST_ACT_REL_MASK),

        .CKE_EN_REL        (CKE_EN_REL),   

        .CKE_EN_REL_MASK   (CKE_EN_REL_MASK),

        .DCI_RST_REL       (DCI_RST_REL),

        .DCI_RST_REL_MASK  (DCI_RST_REL_MASK),

        .DLY_RST_REL       (DLY_RST_REL),

        .DLY_RST_REL_MASK  (DLY_RST_REL_MASK),

        .EXTRA_REL         (EXTRA_REL),

        .EXTRA_REL_MASK    (EXTRA_REL_MASK)

    ) ddrc_control_i (
@@ -405,6 +418,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); 
        .dly_set             (set),                     // output

        .cmda_en             (cmda_en),                 // output

        .ddr_rst             (ddr_rst),                 // output

        .dci_rst             (dci_rst),                 // output

        .dly_rst             (dly_rst),                 // output

        .ddr_cke             (ddr_cke),                 // output

        .inv_clk_div         (inv_clk_div),             // output

        .dqs_pattern         (dqs_pattern[7:0]),        // output[7:0]
@@ -532,6 +547,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); 
        .port1_data     (axiwr_bram_wdata[31:0]), // input[31:0] 

        .cmda_en        (cmda_en), // input

        .ddr_rst        (ddr_rst), // input

        .dci_rst        (dci_rst), // input

        .dly_rst        (dly_rst), // input

        .ddr_cke        (ddr_cke), // input

        .inv_clk_div    (inv_clk_div), // input

        .dqs_pattern    (dqs_pattern), // input[7:0]

ddrc_test01_testbench.sav

+18 −13
Original line number Diff line number Diff line 
[*]

[*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI

[*] Sun Jun  1 23:19:02 2014

[*] Mon Jun  2 06:48:00 2014

[*]

[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140601171040635.lxt"

[dumpfile_mtime] "Sun Jun  1 23:14:06 2014"

[dumpfile_size] 76198101

[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140602003755521.lxt"

[dumpfile_mtime] "Mon Jun  2 06:40:41 2014"

[dumpfile_size] 76024228

[savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav"

[timestart] 116772900

[timestart] 102360000

[size] 1920 1180

[pos] 0 108

*-16.459938 116901250 114486875 114489375 114571875 114574375 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

*-22.533184 131161875 114486875 114489375 114571875 114574375 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[treeopen] ddrc_test01_testbench.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.
@@ -36,9 +37,9 @@ 
[treeopen] ddrc_test01_testbench.simul_axi_master_rdaddr_i.

[treeopen] ddrc_test01_testbench.simul_axi_master_wraddr_i.

[sst_width] 334

[signals_width] 407

[signals_width] 403

[sst_expanded] 1

[sst_vpaned_height] 820

[sst_vpaned_height] 755

@28

ddrc_test01_testbench.RST[0]

ddrc_test01_testbench.CLK[0]
@@ -1306,8 +1307,12 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.set[0] 
-ddrc_sequencer

@800200

-ddr_sequencer_i_selected

@c00200

-tristate_control

@28

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDODT[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dqs[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dq[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_dci_in[0]

@22

ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dqs_tri_pattern_r[15:0]

@28
@@ -1332,7 +1337,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_dq_tri_in[0] 
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_dq_tri[7:0]

@28

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.iobufs_dqs_i.T[0]

@1401200

@1000200

-tristate_control

@28

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.sdclk[0]
@@ -1391,7 +1396,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_clk[0] 
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_data[31:0]

@28

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_we[0]

@23

@22

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_addr[9:0]

@800028

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
@@ -1822,7 +1827,7 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.we[0] 
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wem[0]

@1401200

-wdata_i

@800200

@c00200

-axibram_read_i

@28

ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.aclk[0]
@@ -1922,7 +1927,7 @@ ddrc_test01_testbench.SIMUL_AXI_FULL[0] 
ddrc_test01_testbench.rstb[0]

@200

-

@1000200

@1401200

-axibram_read_i

@c00200

-ddrc_status

ddrc_test01_testbench.tf

+91 −61

File changed.

Preview size limit exceeded, changes collapsed.