Commit bda74800 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

preparing for testing membridge module on the target system

parent 079114c1

.project

+15 −15
Original line number Diff line number Diff line
@@ -62,77 +62,77 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150428234740722.log</location>

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			<type>1</type>

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		<link>

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			<type>1</type>

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			<type>1</type>

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</projectDescription>

py393/dbg/x393_mcntrl.pickle

+59378 −59795

File changed.

Preview size limit exceeded, changes collapsed.

py393/test_mcntrl.py

+4 −1
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ import x393_mcntrl_buffers 
import x393_mcntrl_tests

import x393_mcntrl_eyepatterns

import x393_mcntrl_adjust

import x393_mcntrl_membridge

import vrlg

__all__ = []

__version__ = 0.1
@@ -330,7 +331,7 @@ USAGE 
    x393Tests=       x393_mcntrl_tests.X393McntrlTests(verbose,args.simulated)

    x393Eyepatterns= x393_mcntrl_eyepatterns.X393McntrlEyepattern(verbose,args.simulated)

    x393Adjust=      x393_mcntrl_adjust.X393McntrlAdjust(verbose,args.simulated,args.localparams)

    

    X393Membridge=   x393_mcntrl_membridge.X393McntrlMembridge(verbose,args.simulated)

    '''

    print ("----------------------")

    print("x393_mem.__dict__="+str(x393_mem.__dict__))
@@ -354,6 +355,8 @@ USAGE 
    extractTasks(x393_mcntrl_tests.X393McntrlTests,x393Tests)

    extractTasks(x393_mcntrl_eyepatterns.X393McntrlEyepattern,x393Eyepatterns)

    extractTasks(x393_mcntrl_adjust.X393McntrlAdjust,x393Adjust)

    extractTasks(x393_mcntrl_membridge.X393McntrlMembridge,X393Membridge)

    



    for cmdLine in commands:

        print ('Running task: '+str(cmdLine))

py393/vrlg.py

+67 −25
Original line number Diff line number Diff line
@@ -121,14 +121,16 @@ def restore_default(vname=None): 


DFLT_REFRESH_ADDR__TYPE = str

NUM_CYCLES_09__RAW = str

MEMBRIDGE_SIZE64__TYPE = str

DQSTRI_LAST__TYPE = str

DLY_LD_MASK__TYPE = str

STATUS_MSB_RSHFT__TYPE = str

MCONTR_BUF0_RD_ADDR = int

MCNTRL_SCANLINE_WINDOW_WH__RAW = str

MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int

WSEL = int

MCNTRL_TEST01_CHN3_STATUS_CNTRL = int

MCNTRL_PS_EN_RST__TYPE = str

LD_DLY_LANE1_IDELAY = int

MCONTR_TOP_16BIT_STATUS_CNTRL__TYPE = str

MCNTRL_TILED_CHN4_ADDR = int

WINDOW_Y0__RAW = str
@@ -146,26 +148,29 @@ TILED_STARTX__TYPE = str 
HIGH_PERFORMANCE_MODE__TYPE = str

MCONTR_PHY_STATUS_REG_ADDR__TYPE = str

MCONTR_TOP_16BIT_ADDR__TYPE = str

AFI_LO_ADDR64__TYPE = str

WBUF_DLY_WLV__TYPE = str

TEST01_SUSPEND = int

MCONTR_TOP_16BIT_CHN_EN = int

NUM_XFER_BITS__TYPE = str

AFI_SIZE64 = int

DLY_LANE1_IDELAY__TYPE = str

REF_JITTER1__RAW = str

MCNTRL_TILED_MASK__TYPE = str

MCONTR_BUF1_WR_ADDR = int

MCNTRL_SCANLINE_MASK__TYPE = str

DFLT_DQ_TRI_ON_PATTERN = int

MCONTR_PHY_0BIT_SDRST_ACT = int

DEFAULT_STATUS_MODE = int

MEMBRIDGE_START64__TYPE = str

TILED_EXTRA_PAGES__TYPE = str

DLY_LD__TYPE = str

MCNTRL_TEST01_CHN2_STATUS_CNTRL__TYPE = str

MCNTRL_SCANLINE_FRAME_PAGE_RESET = int

STATUS_2LSB_SHFT__TYPE = str

DFLT_WBUF_DELAY__RAW = str

DLY_LANE1_ODELAY__TYPE = str

MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str

TILE_VSTEP__RAW = str

MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str

MEMBRIDGE_LEN64__TYPE = str

NUM_CYCLES_04 = int

NUM_CYCLES_05 = int

DLY_LD = int
@@ -180,7 +185,7 @@ MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str 
NUM_CYCLES_13__RAW = str

MCONTR_BUF0_RD_ADDR__TYPE = str

STATUS_ADDR__RAW = str

MCNTRL_SCANLINE_MASK__TYPE = str

DLY_LANE0_IDELAY__TYPE = str

MCNTRL_PS_ADDR__TYPE = str

WINDOW_WIDTH__RAW = str

CHNBUF_READ_LATENCY = int
@@ -199,7 +204,8 @@ MCNTRL_TILED_TILE_WHS = int 
FRAME_START_ADDRESS__TYPE = str

MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int

MCNTRL_TILED_STATUS_CNTRL__RAW = str

DQSTRI_FIRST = int

MEMBRIDGE_ADDR__RAW = str

DLY_PHASE = int

DFLT_DQS_TRI_OFF_PATTERN = int

NUM_CYCLES_03__TYPE = str

MCONTR_TOP_16BIT_CHN_EN__TYPE = str
@@ -211,8 +217,9 @@ VERBOSE = int 
DLY_LANE1_ODELAY = long

MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str

CMD_DONE_BIT__TYPE = str

MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str

MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str

DLY_LANE0_IDELAY = long

CLKFBOUT_DIV_AXIHP = int

NUM_CYCLES_13__TYPE = str

AXI_RD_ADDR_BITS__RAW = str

MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
@@ -220,11 +227,13 @@ MCONTR_WR_MASK__RAW = str 
MCNTRL_TILED_WINDOW_STARTXY = int

MCONTR_TOP_0BIT_MCONTR_EN = int

SCANLINE_EXTRA_PAGES__RAW = str

MEMBRIDGE_LEN64__RAW = str

MCONTR_PHY_16BIT_EXTRA = int

MCONTR_ARBIT_ADDR_MASK__TYPE = str

TEST01_NEXT_PAGE__TYPE = str

MCONTR_PHY_0BIT_DLY_SET__TYPE = str

MCONTR_PHY_STATUS_REG_ADDR = int

NUM_CYCLES_LOW_BIT = int

CLKFBOUT_MULT_REF = int

NUM_CYCLES_14__RAW = str

MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
@@ -254,7 +263,7 @@ MCONTR_BUF2_WR_ADDR__RAW = str 
NUM_CYCLES_11__TYPE = str

MCNTRL_SCANLINE_STARTADDR__TYPE = str

WBUF_DLY_DFLT__RAW = str

DLY_PHASE = int

DQSTRI_FIRST = int

LD_DLY_CMDA__TYPE = str

DLY_CMDA_ODELAY__TYPE = str

LD_DLY_CMDA = int
@@ -267,10 +276,13 @@ MCNTRL_SCANLINE_MASK = int 
TILE_HEIGHT = int

AXI_WR_ADDR_BITS__TYPE = str

MCNTRL_PS_MASK = int

MEMBRIDGE_CTRL = int

MCNTRL_TEST01_STATUS_REG_CHN3_ADDR = int

COLADDR_NUMBER = int

MCONTR_PHY_STATUS_CNTRL = int

MCNTRL_PS_ADDR__RAW = str

MCONTR_BUF2_RD_ADDR__TYPE = str

CLKFBOUT_DIV_AXIHP__RAW = str

TILED_STARTX__RAW = str

WRITE_BLOCK_OFFSET__TYPE = str

STATUS_ADDR_MASK = int
@@ -279,7 +291,7 @@ AXI_WR_ADDR_BITS = int 
TEST01_NEXT_PAGE = int

CLKFBOUT_MULT__RAW = str

MAX_TILE_HEIGHT__RAW = str

INITIALIZE_OFFSET__TYPE = str

MCNTRL_TEST01_CHN1_STATUS_CNTRL = int

IBUF_LOW_PWR = str

CONTROL_ADDR = int

DQSTRI_FIRST__TYPE = str
@@ -318,7 +330,9 @@ LD_DLY_LANE1_ODELAY__RAW = str 
MCNTRL_TILED_WINDOW_WH__TYPE = str

MCONTR_WR_MASK__TYPE = str

SS_MOD_PERIOD__RAW = str

MEMBRIDGE_WIDTH64__TYPE = str

MAX_TILE_HEIGHT = int

AFI_LO_ADDR64__RAW = str

MCNTRL_SCANLINE_STARTADDR__RAW = str

MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str

MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
@@ -329,8 +343,10 @@ MCONTR_TOP_STATUS_REG_ADDR__TYPE = str 
MCONTR_PHY_16BIT_WBUF_DELAY = int

DEFAULT_STATUS_MODE__RAW = str

DLY_LANE1_DQS_WLV_IDELAY__TYPE = str

TILE_HEIGHT__RAW = str

FRAME_WIDTH_BITS = int

MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str

MEMBRIDGE_STATUS_CNTRL = int

SLEW_CMDA__TYPE = str

MCONTR_RD_MASK__TYPE = str

READ_BLOCK_OFFSET__RAW = str
@@ -339,6 +355,7 @@ SLEW_DQ__RAW = str 
FRAME_HEIGHT_BITS__TYPE = str

DLY_DQS_IDELAY = long

MCONTR_BUF3_RD_ADDR__TYPE = str

MEMBRIDGE_ADDR = int

DLY_DQ_ODELAY__TYPE = str

MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str

MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
@@ -352,11 +369,13 @@ DLY_LANE0_DQS_WLV_IDELAY__TYPE = str 
MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str

SCANLINE_EXTRA_PAGES__TYPE = str

PHASE_WIDTH__RAW = str

MEMBRIDGE_START64 = int

MEMBRIDGE_SIZE64__RAW = str

DFLT_DQS_PATTERN = int

DLY_LANE0_DQS_WLV_IDELAY__RAW = str

MCNTRL_TEST01_CHN2_MODE__TYPE = str

DLY_LANE1_IDELAY__RAW = str

MCONTR_BUF1_RD_ADDR = int

MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str

SLEW_CLK = str

LD_DLY_LANE1_ODELAY__TYPE = str

MCNTRL_PS_STATUS_CNTRL = int
@@ -365,7 +384,7 @@ SS_MODE__TYPE = str 
MCONTR_TOP_16BIT_REFRESH_ADDRESS__RAW = str

WINDOW_Y0__TYPE = str

MCONTR_PHY_0BIT_DLY_RST__TYPE = str

MCONTR_BUF1_WR_ADDR__TYPE = str

CLKFBOUT_MULT_AXIHP__RAW = str

BUFFER_DEPTH32__TYPE = str

MCONTR_TOP_16BIT_STATUS_CNTRL = int

MCONTR_BUF4_RD_ADDR__RAW = str
@@ -380,8 +399,10 @@ DLY_CMDA = long 
DLY_LANE0_IDELAY__RAW = str

MCONTR_ARBIT_ADDR = int

MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str

MEMBRIDGE_CTRL__RAW = str

CLKFBOUT_DIV_REF__TYPE = str

NUM_CYCLES_04__TYPE = str

WSEL__RAW = str

MCNTRL_SCANLINE_MODE__RAW = str

READ_PATTERN_OFFSET__TYPE = str

MCNTRL_TILED_PENDING_CNTR_BITS = int
@@ -390,14 +411,15 @@ MAX_TILE_WIDTH__TYPE = str 
MCONTR_CMD_WR_ADDR = int

MCONTR_BUF3_RD_ADDR__RAW = str

CLKIN_PERIOD = int

MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str

DLY_LANE1_ODELAY__TYPE = str

RSEL__TYPE = str

MCNTRL_TEST01_MASK__RAW = str

MCONTR_PHY_16BIT_ADDR_MASK = int

MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str

HIGH_PERFORMANCE_MODE = str

NUM_CYCLES_07__RAW = str

DQTRI_LAST__RAW = str

MCONTR_BUF1_RD_ADDR__RAW = str

TILE_WIDTH = int

CLKFBOUT_PHASE = float

DFLT_DQM_PATTERN = int

MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
@@ -438,8 +460,8 @@ MCNTRL_PS_CMD__RAW = str 
MCONTR_BUF3_WR_ADDR = int

NEWPAR = int

MCNTRL_PS_MASK__RAW = str

AFI_SIZE64__RAW = str

MCONTR_PHY_0BIT_CKE_EN = int

MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str

BUFFER_DEPTH32 = int

MCNTRL_TILED_CHN2_ADDR__TYPE = str

SLEW_DQS = str
@@ -447,6 +469,7 @@ DFLT_REFRESH_ADDR = int 
MCONTR_WR_MASK = int

MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int

TEST01_SUSPEND__RAW = str

MEMBRIDGE_STATUS_CNTRL__TYPE = str

T_REFI__TYPE = str

STATUS_DEPTH__RAW = str

DFLT_DQ_TRI_ON_PATTERN__TYPE = str
@@ -454,7 +477,6 @@ MCONTR_TOP_0BIT_ADDR_MASK__RAW = str 
TEST01_START_FRAME = int

DQTRI_FIRST__TYPE = str

MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str

DLY_LANE0_IDELAY__TYPE = str

T_RFC__RAW = str

DLY_CMDA__TYPE = str

CLKFBOUT_MULT__TYPE = str
@@ -477,20 +499,24 @@ COLADDR_NUMBER__TYPE = str 
MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int

TEST01_SUSPEND__TYPE = str

PICKLE = str

AFI_SIZE64__TYPE = str

NUM_CYCLES_15__RAW = str

MCONTR_PHY_0BIT_ADDR_MASK = int

MCNTRL_TILED_TILE_WHS__TYPE = str

DLY_DQ_IDELAY = long

WINDOW_X0 = int

DFLT_WBUF_DELAY__TYPE = str

MCNTRL_TEST01_CHN1_STATUS_CNTRL = int

INITIALIZE_OFFSET__TYPE = str

LD_DLY_LANE0_ODELAY = int

SCANLINE_EXTRA_PAGES = int

READ_PATTERN_OFFSET__RAW = str

MCNTRL_SCANLINE_CHN1_ADDR__RAW = str

TILE_HEIGHT__RAW = str

MEMBRIDGE_LEN64 = int

MEMBRIDGE_SIZE64 = int

PICKLE__TYPE = str

MCONTR_PHY_0BIT_CKE_EN__TYPE = str

AFI_LO_ADDR64 = int

RSEL = int

MCNTRL_TILED_MODE__TYPE = str

DIVCLK_DIVIDE = int

NUM_CYCLES_07__TYPE = str
@@ -512,23 +538,25 @@ MCONTR_PHY_0BIT_DLY_RST = int 
MCONTR_PHY_16BIT_ADDR__TYPE = str

TILED_STARTY = int

TILED_STARTX = int

MEMBRIDGE_MASK__TYPE = str

AXI_WR_ADDR_BITS__RAW = str

MCONTR_BUF3_RD_ADDR = int

DFLT_REFRESH_PERIOD__TYPE = str

MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str

MCNTRL_TILED_MASK = int

NUM_CYCLES_03__RAW = str

MCONTR_BUF1_WR_ADDR__RAW = str

CLKFBOUT_PHASE__TYPE = str

MCONTR_PHY_16BIT_ADDR_MASK__RAW = str

DLY_LANE1_DQS_WLV_IDELAY = long

MCNTRL_TILED_WINDOW_WH = int

CLKFBOUT_PHASE__TYPE = str

NUM_CYCLES_06__RAW = str

MCNTRL_TILED_WINDOW_X0Y0__TYPE = str

NUM_XFER_BITS__RAW = str

MCNTRL_TILED_WINDOW_STARTXY__RAW = str

CLKFBOUT_MULT_AXIHP = int

DLY_CMDA_ODELAY = long

MCONTR_TOP_0BIT_ADDR = int

MEMBRIDGE_LO_ADDR64__TYPE = str

MCNTRL_SCANLINE_MODE = int

MCONTR_ARBIT_ADDR_MASK = int

NUM_CYCLES_05__RAW = str
@@ -541,6 +569,7 @@ MCONTR_TOP_0BIT_REFRESH_EN = int 
MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int

SLEW_CMDA__RAW = str

MCNTRL_TEST01_CHN2_MODE__RAW = str

CLKFBOUT_MULT_AXIHP__TYPE = str

LD_DLY_PHASE__RAW = str

MCONTR_TOP_STATUS_REG_ADDR__RAW = str

MCONTR_ARBIT_ADDR__TYPE = str
@@ -560,12 +589,13 @@ MCONTR_BUF2_RD_ADDR = int 
MCONTR_BUF2_WR_ADDR__TYPE = str

NUM_CYCLES_02__TYPE = str

DQTRI_LAST__TYPE = str

TILE_WIDTH = int

TEST_INITIAL_BURST = int

FRAME_HEIGHT_BITS__RAW = str

MCNTRL_TILED_STARTADDR = int

WINDOW_HEIGHT__TYPE = str

MCNTRL_TILED_FRAME_FULL_WIDTH = int

TILE_HEIGHT__TYPE = str

CLKFBOUT_DIV_AXIHP__TYPE = str

MCNTRL_TILED_CHN4_ADDR__TYPE = str

FRAME_HEIGHT_BITS = int

MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
@@ -590,15 +620,16 @@ REF_JITTER1__TYPE = str 
MCNTRL_SCANLINE_MODE__TYPE = str

MCONTR_PHY_16BIT_PATTERNS_TRI = int

DLY_CMDA__RAW = str

NUM_CYCLES_LOW_BIT = int

MEMBRIDGE_MASK = int

READ_BLOCK_OFFSET = int

T_REFI__RAW = str

STATUS_MSB_RSHFT = int

BUFFER_DEPTH32__RAW = str

RSEL__RAW = str

CLKIN_PERIOD__TYPE = str

DIVCLK_DIVIDE__RAW = str

DLY_LANE0_ODELAY__TYPE = str

COLADDR_NUMBER = int

DLY_LANE0_IDELAY = long

SDCLK_PHASE__TYPE = str

SCANLINE_STARTY__TYPE = str

REFRESH_OFFSET__RAW = str
@@ -607,14 +638,17 @@ MCNTRL_TEST01_CHN1_MODE__RAW = str 
MCONTR_BUF4_RD_ADDR__TYPE = str

LD_DLY_LANE0_ODELAY__TYPE = str

MCONTR_TOP_16BIT_ADDR__RAW = str

MEMBRIDGE_LO_ADDR64 = int

MCNTRL_SCANLINE_PENDING_CNTR_BITS = int

DFLT_DQS_TRI_ON_PATTERN__TYPE = str

MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str

TILED_KEEP_OPEN__RAW = str

MCNTRL_SCANLINE_STARTADDR = int

MEMBRIDGE_WIDTH64__RAW = str

MCONTR_TOP_0BIT_ADDR__TYPE = str

CLKFBOUT_MULT_REF__TYPE = str

MCNTRL_PS_CMD__TYPE = str

MEMBRIDGE_START64__RAW = str

STATUS_MSB_RSHFT__RAW = str

STATUS_PSHIFTER_RDY_MASK = int

NUM_CYCLES_04__RAW = str
@@ -632,6 +666,8 @@ MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str 
VERBOSE__RAW = str

WBUF_DLY_WLV = int

MCONTR_BUF3_WR_ADDR__RAW = str

MEMBRIDGE_LO_ADDR64__RAW = str

MEMBRIDGE_WIDTH64 = int

MCNTRL_TEST01_CHN3_MODE = int

LD_DLY_PHASE__TYPE = str

MCONTR_PHY_0BIT_ADDR__TYPE = str
@@ -644,11 +680,12 @@ STATUS_ADDR_MASK__RAW = str 
MCNTRL_SCANLINE_CHN3_ADDR = int

DLY_SET__TYPE = str

MCONTR_TOP_16BIT_ADDR = int

MCONTR_BUF1_RD_ADDR__TYPE = str

DLY_DM_ODELAY = long

MEMBRIDGE_STATUS_CNTRL__RAW = str

MCONTR_TOP_16BIT_REFRESH_ADDRESS = int

DFLT_DQS_TRI_OFF_PATTERN__RAW = str

FRAME_FULL_WIDTH = int

MEMBRIDGE_STATUS_REG = int

NUM_CYCLES_13 = int

NUM_CYCLES_12 = int

NUM_CYCLES_11 = int
@@ -690,7 +727,7 @@ CLKIN_PERIOD__RAW = str 
INITIALIZE_OFFSET = int

MCNTRL_PS_MASK__TYPE = str

CLK_DIV_PHASE__RAW = str

LD_DLY_LANE1_IDELAY = int

MCNTRL_PS_EN_RST__TYPE = str

MCONTR_PHY_16BIT_PATTERNS__TYPE = str

MCONTR_PHY_0BIT_CKE_EN__RAW = str

PICKLE__RAW = str
@@ -727,6 +764,7 @@ MCLK_PHASE__RAW = str 
MCONTR_TOP_16BIT_REFRESH_PERIOD = int

T_REFI = int

MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str

WSEL__TYPE = str

STATUS_SEQ_SHFT__TYPE = str

DFLT_CHN_EN__TYPE = str

MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
@@ -747,15 +785,17 @@ SS_EN = str 
DLY_LANE0_ODELAY = long

CLKFBOUT_DIV_REF = int

WRITELEV_OFFSET = int

MEMBRIDGE_ADDR__TYPE = str

MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str

VERBOSE__TYPE = str

TILED_KEEP_OPEN = int

MCNTRL_SCANLINE_MASK__RAW = str

MCNTRL_SCANLINE_WINDOW_STARTXY = int

TEST_INITIAL_BURST = int

MCONTR_ARBIT_ADDR__RAW = str

MEMBRIDGE_MASK__RAW = str

MCNTRL_TEST01_ADDR = int

MCONTR_TOP_0BIT_MCONTR_EN__TYPE = str

MEMBRIDGE_CTRL__TYPE = str

MCONTR_BUF4_WR_ADDR__RAW = str

TILED_KEEP_OPEN__TYPE = str

CONTROL_ADDR_MASK__TYPE = str
@@ -771,6 +811,7 @@ REFRESH_OFFSET__TYPE = str 
DFLT_INV_CLK_DIV__TYPE = str

MAX_TILE_WIDTH = int

CHNBUF_READ_LATENCY__RAW = str

MEMBRIDGE_STATUS_REG__TYPE = str

MCONTR_BUF4_RD_ADDR = int

SS_MOD_PERIOD__TYPE = str

MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
@@ -783,6 +824,7 @@ INITIALIZE_OFFSET__RAW = str 
CMD_DONE_BIT__RAW = str

MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str

CLK_DIV_PHASE = float

MEMBRIDGE_STATUS_REG__RAW = str

MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str

MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str

MCONTR_BUF0_WR_ADDR__TYPE = str

py393/x393_axi_control_status.py

+17 −15
Original line number Diff line number Diff line
@@ -187,19 +187,19 @@ class X393AxiControlStatus(object): 
                              timeout=10.0):          # maximal timeout (0 - no timeout)

        """

        Poll specified status register until some condition is matched

        <status_address> -         status register address (currently 0..255)

        <status_control_address> - control register address (to control status generation)

        <status_mode>            - status generation mode:

        @param status_address   status register address (currently 0..255)

        @param status_control_address> - control register address (to control status generation)

        @param status_mode status generation mode:

                             0: disable status generation,

                             1: single status request,

                             2: auto status, keep specified seq number,

                             4: auto, inc sequence number 

        <pattern> -                26-bit pattern to match

        <mask> -                   26-bit mask to enable pattern matching (0-s - ignore)

        <invert_match> -           invert match (wait until matching condition becomes false)

        <wait_seq>-                wait for the correct sequence number, if False - assume always correct

        <timeout>                  maximal time to wait for condition

        Return 1 if success, 0 - if timeout

        @param pattern       26-bit pattern to match

        @param mask          26-bit mask to enable pattern matching (0-s - ignore)

        @param invert_match  invert match (wait until matching condition becomes false)

        @param wait_seq      wait for the correct sequence number, if False - assume always correct

        @param timeout       maximal time to wait for condition

        @return 1 if success, 0 - if timeout

        """

        match=False

        endTime=None
@@ -245,10 +245,11 @@ class X393AxiControlStatus(object): 
        print ("MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR:%s"%(hx(self.read_status(vrlg.MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),8)))

        print ("MCNTRL_TILED_STATUS_REG_CHN2_ADDR:   %s"%(hx(self.read_status(vrlg.MCNTRL_TILED_STATUS_REG_CHN2_ADDR),8)))

        print ("MCNTRL_TILED_STATUS_REG_CHN4_ADDR:   %s"%(hx(self.read_status(vrlg.MCNTRL_TILED_STATUS_REG_CHN4_ADDR),8)))

        print ("MCNTRL_TEST01_STATUS_REG_CHN1_ADDR:  %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR),8)))

#        print ("MCNTRL_TEST01_STATUS_REG_CHN1_ADDR:  %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR),8)))

        print ("MCNTRL_TEST01_STATUS_REG_CHN2_ADDR:  %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),8)))

        print ("MCNTRL_TEST01_STATUS_REG_CHN3_ADDR:  %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),8)))

        print ("MCNTRL_TEST01_STATUS_REG_CHN4_ADDR:  %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),8)))

        print ("MEMBRIDGE_STATUS_REG:                %s"%(hx(self.read_status(vrlg.MEMBRIDGE_STATUS_REG),8)))



    def program_status(self,

                       base_addr,   # input [29:0] base_addr;
@@ -289,10 +290,11 @@ class X393AxiControlStatus(object): 
        self.program_status (vrlg.MCNTRL_SCANLINE_CHN3_ADDR, vrlg.MCNTRL_SCANLINE_STATUS_CNTRL,   mode,seq_num)# //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,

        self.program_status (vrlg.MCNTRL_TILED_CHN2_ADDR,    vrlg.MCNTRL_TILED_STATUS_CNTRL,      mode,seq_num)# //MCNTRL_TILED_STATUS_REG_CHN4_ADDR=   'h6,

        self.program_status (vrlg.MCNTRL_TILED_CHN4_ADDR,    vrlg.MCNTRL_TILED_STATUS_CNTRL,      mode,seq_num)#; //MCNTRL_TILED_STATUS_REG_CHN4_ADDR=   'h6,

        self.program_status (vrlg.MCNTRL_TEST01_ADDR,        vrlg.MCNTRL_TEST01_CHN1_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,

#        self.program_status (vrlg.MCNTRL_TEST01_ADDR,        vrlg.MCNTRL_TEST01_CHN1_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,

        self.program_status (vrlg.MCNTRL_TEST01_ADDR,        vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,

        self.program_status (vrlg.MCNTRL_TEST01_ADDR,        vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR=  'h3d,

        self.program_status (vrlg.MCNTRL_TEST01_ADDR,        vrlg.MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR=  'h3e,

        self.program_status (vrlg.MEMBRIDGE_ADDR,            vrlg.MEMBRIDGE_STATUS_CNTRL,         mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR=  'h3e,

        

    def enable_cmda(self,

                    en): # input en;