change DM* I/O standard to SSTL15 (0bd9ef33) · Commits · Elphel / x393

.project

+15 −15

Original line number	Diff line number	Diff line
		@@ -46,77 +46,77 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140515155524262.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140531004107237.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140522174846453.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140531003924649.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140515155524262.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140531004107237.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140522174846453.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140531003924649.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140522174846453.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140531003924649.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140515155524262.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140531004107237.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140522174846453.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140531003924649.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140515155524262.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140531004107237.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140522174846453.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140531003924649.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140515155524262.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140531004107237.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140522174846453.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140531003924649.log</location>
		</link>
		<link>
		<name>vivado_state/eddr3-opt-phys.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140515155524262.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140531004107237.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-place.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140522174846453.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140531003924649.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-route.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140515155524262.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140531004107237.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-synth.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140522174846453.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140531003924649.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

ddrc_test01.v

+4 −3

Original line number	Diff line number	Diff line
		@@ -255,19 +255,20 @@ always @ (posedge axi_rst or posedge axi_aclk) begin
		if (axi_rst) select_status <= 1'b0;
		else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
		end
		/*

		// Clock and reset from PS
		reg frst_inv;
		always @ (negedge frst[0] or posedge axi_aclk) begin
		if (!frst[0]) frst_inv <= 1'b1;
		else frst_inv <= 1'b0;
		end
		*/

		/*
		`ifndef IVERILOG
		(* dont_touch = "true" *)
		`endif
		wire frst_inv= ~frst[0];

		*/

		//BUFG bufg_axi_rst_i (.O(axi_rst),.I(~frst[0]));
		BUFG bufg_axi_rst_i (.O(axi_rst),.I(frst_inv));

ddrc_test01.xdc

+4 −2

Original line number	Diff line number	Diff line
		@@ -194,11 +194,13 @@ set_property PACKAGE_PIN G7 [get_ports {NDQSU}]
		set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSU}]

		# inout SDDML, // LDM I/O pad (actually only output)
		set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDML}]
		#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDML}]
		set_property IOSTANDARD SSTL15 [get_ports {SDDML}]
		set_property PACKAGE_PIN L5 [get_ports {SDDML}]

		# inout SDDMU, // UDM I/O pad (actually only output)
		set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDMU}]
		#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDMU}]
		set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
		set_property PACKAGE_PIN J5 [get_ports {SDDMU}]

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