- 19 Nov, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 15 Nov, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 12 Nov, 2015 1 commit
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Andrey Filippov authored
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- 11 Nov, 2015 1 commit
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Andrey Filippov authored
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- 08 Nov, 2015 5 commits
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Andrey Filippov authored
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Andrey Filippov authored
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Andrey Filippov authored
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Andrey Filippov authored
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Andrey Filippov authored
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- 07 Nov, 2015 1 commit
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Andrey Filippov authored
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- 06 Nov, 2015 2 commits
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Andrey Filippov authored
Fixed generate that instantiated 4*4 histogram modules (including disables), tried with single histogram per channel - added 8% of all slices
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Andrey Filippov authored
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- 03 Nov, 2015 1 commit
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Andrey Filippov authored
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- 01 Nov, 2015 2 commits
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Andrey Filippov authored
Made several modifications to fix all timing violations to run compressor @250MHz - 1.0 Gigapixel/sec in JP4 mode
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Andrey Filippov authored
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- 31 Oct, 2015 1 commit
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Andrey Filippov authored
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- 29 Oct, 2015 1 commit
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Andrey Filippov authored
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- 28 Oct, 2015 1 commit
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Andrey Filippov authored
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- 27 Oct, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 25 Oct, 2015 1 commit
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Andrey Filippov authored
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- 24 Oct, 2015 1 commit
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Andrey Filippov authored
Imlemented single-clock bit stuffer to aggregate MSB aligned variable-length (1..27) data to 32-bit words
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- 23 Oct, 2015 1 commit
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Andrey Filippov authored
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- 22 Oct, 2015 3 commits
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Andrey Filippov authored
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Andrey Filippov authored
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Andrey Filippov authored
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- 21 Oct, 2015 1 commit
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Andrey Filippov authored
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- 20 Oct, 2015 1 commit
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Andrey Filippov authored
implemented optional skipping/fast forward of the data blocks when buffer is over/underrun during memory access
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- 18 Oct, 2015 1 commit
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Andrey Filippov authored
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- 16 Oct, 2015 1 commit
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Andrey Filippov authored
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- 15 Oct, 2015 1 commit
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Andrey Filippov authored
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- 14 Oct, 2015 1 commit
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Andrey Filippov authored
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- 13 Oct, 2015 1 commit
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Andrey Filippov authored
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- 12 Oct, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 11 Oct, 2015 2 commits
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Andrey Filippov authored
added simuilation modules for frequency multiplication/division, fractional period delays, started parallel12 -> HiSPi packetized SP converter
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Andrey Filippov authored
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- 10 Oct, 2015 1 commit
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Andrey Filippov authored
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