Commit 62cf2722 authored by Andrey Filippov's avatar Andrey Filippov

simulating, starting hardware testing

parent 802a2f02
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151009231255456.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151028193155597.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
......@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_nox2_timing.xdc<-@\#\#@->
VivadoSynthesis_122_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true
VivadoSynthesis_123_SkipSnapshotSynth=true
......
......@@ -76,7 +76,8 @@ module bit_stuffer_27_32#(
// barrel shifter stage 1 (0/8/16/24)
if (ds) case (early_length[4:3])
if (rst) data1 <= 'bx;
else if (ds) case (early_length[4:3])
2'h0: data1 <= { din, 24'b0};
2'h1: data1 <= { 8'b0,din, 16'b0};
2'h2: data1 <= {16'b0,din, 8'b0};
......@@ -84,13 +85,16 @@ module bit_stuffer_27_32#(
endcase
// barrel shifter stage 2 (0/2/4/6)
if (stage[0]) case (dlen1[2:1])
if (rst) data2 <= 'bx;
else if (stage[0]) case (dlen1[2:1])
2'h0: data2 <= { data1, 6'b0};
2'h1: data2 <= { 2'b0,data1, 4'b0};
2'h2: data2 <= { 4'b0,data1, 2'b0};
2'h3: data2 <= { 6'b0,data1 };
endcase
if (stage[0]) case (dlen1[4:0])
if (rst) dmask2_rom <= 'bx;
else if (stage[0]) case (dlen1[4:0])
5'h00: dmask2_rom <= 32'hffffffff;
5'h01: dmask2_rom <= 32'h7fffffff;
5'h02: dmask2_rom <= 32'h3fffffff;
......@@ -125,7 +129,8 @@ module bit_stuffer_27_32#(
5'h1f: dmask2_rom <= 32'h00000001;
endcase
// barrel shifter stage 3 (0/1), combined with output/hold register
if (ds_stage[1]) begin
if (rst) data3 <= 'bx;
else if (ds_stage[1]) begin
data3[DATA3_LEN-1 -: 32] <= (~dmask2_rom & (dlen2[5] ? {data3[DATA3_LEN-1-32 : 0],6'b0}: data3[DATA3_LEN-1 -: 32])) |
( dmask2_rom & (dlen2[0] ? {1'b0,data2[DATA2_LEN-1 -: 31]} : data2[DATA2_LEN-1 -: 32]));
data3[DATA3_LEN-1-32: 0] <= dlen2[0] ? data2[DATA2_LEN-31-1 : 0] : {data2[DATA2_LEN-32-1 : 0], 1'b0};
......@@ -135,9 +140,11 @@ module bit_stuffer_27_32#(
// dv <= (ds_stage[1] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
// dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32]));
// no difference in number of cells
// if (rst ) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
// else if (ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
if (rst || ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
else if (flush_stage[1]) bytes_out <= pre_bits_out_w[4:3];
else if (flush_stage[1]) bytes_out <= pre_bits_out_w[4:3];
flush_out <= flush_stage[2];
......
......@@ -215,7 +215,7 @@ module bit_stuffer_escape(
case (sel0_w)
2'b00 : d_out[ 7: 0] <= fifo_out_barrel_w[ 7: 0];
2'b01 : d_out[ 7: 0] <= fifo_out_barrel_w[15: 8];
2'b01 : d_out[ 7: 0] <= fifo_out_barrel_w[23:16];
2'b10 : d_out[ 7: 0] <= fifo_out_barrel_w[23:16];
2'b11 : d_out[ 7: 0] <= 8'b0;
default : d_out[ 7: 0] <= 'bx;
endcase
......@@ -228,11 +228,14 @@ module bit_stuffer_escape(
if (rst) flush_pend[1] <= 0;
else flush_pend[1] <= flush_pend[0] &&!flush_pend[1] && !rdy_w;
flush_pend[2] <= flush_pend[1];
if (rst) flush_pend[2] <= 0;
else flush_pend[2] <= flush_pend[1];
flush_out <= flush_pend[2];
if (rst) flush_out <= 0;
else flush_out <= flush_pend[2];
if ( rdy_w || flush_pend[1]) casex(bytes_rdy_w[3:0])
if (rst) bytes_out <= 'bx;
else if ( rdy_w || flush_pend[1]) casex(bytes_rdy_w[3:0])
4'b10xx : bytes_out <= 1;
4'b110x : bytes_out <= 2;
4'b1110 : bytes_out <= 3;
......
......@@ -119,9 +119,8 @@ module bit_stuffer_metadata(
data_out_valid <= stb || trailer;
if (xrst) running <= 0;
else if (stb_start) running <= 1;
else if (trailer) running <= 0;
if (xrst || trailer) running <= 0;
else if (stb_start) running <= 1;
done <= trailer_done;
// re-clock abort, extract leading edge
......
/*******************************************************************************
* Module: cmprs_out_fifo32
* Date:2015-06-25
* Author: Andrey Filippov
* Description: Compressor output FIFO, modified to use 32-bit input and xclk
*
* Copyright (c) 2015 Elphel, Inc.
* cmprs_out_fifo32.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmprs_out_fifo32.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmprs_out_fifo32(
// input rst, // mostly for simulation
// wclk domain
input wclk, // source clock (1x pixel clock)
input wrst, // @posedge wclk, sync reset
input we,
input [31:0] wdata,
input wa_rst, // reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
input wlast, // written last 32 bytes of a frame (flush FIFO) - stuffer_done (has to be later than we)
output eof_written_wclk, // eof_written - reclocked to wclk
// rclk domain
input rclk,
input rrst, // @posedge rclk, sync reset
input rst_fifo, // reset FIFO (set read address to write, reset count)
input ren,
output [63:0] rdata,
output eof, // single rclk pulse signalling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output flush_fifo, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
);
reg regen;
reg [ 8:0] raddr;
reg [ 7:0] count32;
reg [ 7:0] lcount32; // counting chunks left in the same frame
reg [ 9:0] waddr;
wire written32b; // written 32 bytes, re-clocked to read clock domain (single-cycle)
wire wlast_rclk;
reg flush_fifo_r;
assign flush_fifo = flush_fifo_r;
assign fifo_count = count32;
assign eof = wlast_rclk;
always @ (posedge wclk) begin
if (wrst) waddr <= 0;
else if (wa_rst) waddr <= waddr & 10'h3f8; // reset 3 LSBs only
else if (we) waddr <= waddr + 1;
end
always @ (posedge rclk) begin
regen <= ren;
if (rst_fifo) raddr <= {waddr[9:3],2'b0};
else if (ren) raddr <= raddr + 1;
if (rst_fifo) count32 <= 0;
else if ( written32b && !(ren && (&raddr[1:0]))) count32 <= count32 + 1;
else if (!written32b && (ren && (&raddr[1:0]))) count32 <= count32 - 1;
if (rst_fifo) lcount32 <= 0;
else if (wlast_rclk) lcount32 <= count32;
else if ((lcount32 !=0) && ren && (&raddr[1:0])) lcount32 <= lcount32 - 1;
if (rst_fifo) flush_fifo_r <= 0;
else if (wlast_rclk) flush_fifo_r <= 1;
else if ((count32[7:1] == 0) && ( !count32[0] || ren)) flush_fifo_r <= 0;
end
// wclk -> rclk
pulse_cross_clock written32b_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(we && (&waddr[2:0])), .out_pulse(written32b),.busy());
pulse_cross_clock wlast_rclk_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(wlast), .out_pulse(wlast_rclk),.busy());
// rclk -> wclk
pulse_cross_clock eof_written_wclk_i (.rst(rrst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
ram_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(6)
) fifo_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
.ren (ren), // input
.regen (regen), // input
.data_out (rdata), // output[63:0]
.wclk (wclk), // input - OK, negedge mclk
.waddr (waddr), // input[10:0]
.we (we), // input
.web (8'hff), // input[7:0]
.data_in (wdata) // input[15:0]
);
endmodule
......@@ -119,9 +119,10 @@ module compressor393 # (
`endif
)(
// input rst, // global reset
input xclk, // global clock input, compressor single clock rate
`ifdef USE_XCLK2X
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
`endif
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge hclk, sync reset
......@@ -388,7 +389,9 @@ module compressor393 # (
) jp_channel_i (
// .rst (rst), // input
.xclk (xclk), // input
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // input
`endif
.mrst (mrst), // input
.xrst (xrst), // input
.hrst (hrst), // input
......
......@@ -46,8 +46,8 @@ module huffman_snglclk (
output last_block,
output reg test_lbw,
output gotLastBlock, // last block done - flush the rest bits
// input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
// output flush_clk, // 1-cycle flush output @ clk_flush
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk, // 1-cycle flush output @ clk_flush
output fifo_or_full // FIFO output register full - just for debuging
);
......@@ -256,7 +256,6 @@ module huffman_snglclk (
.out_bits (do27), // output[26:0] reg
.out_len (dl) // output[4:0] reg
);
/*
pulse_cross_clock flush_clk_i (
.rst (rst),
.src_clk (xclk),
......@@ -264,7 +263,5 @@ module huffman_snglclk (
.in_pulse (flush),
.out_pulse (flush_clk),
.busy ());
*/
endmodule
......@@ -47,7 +47,10 @@ module huffman_stuffer_meta(
output [31:0] data_out, // [31:0] output data
output data_out_valid,// output data valid
output done, // reset by !en, goes high after some delay after flushing
output running // from registering timestamp until done
output running, // from registering timestamp until done
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk // 1-cycle flush output @ clk_flush
`ifdef DEBUG_RING
,output test_lbw,
output gotLastBlock, // last block done - flush the rest bits
......@@ -93,8 +96,8 @@ module huffman_stuffer_meta(
.test_lbw (),
.gotLastBlock (), // last block done - flush the rest bits
`endif
// .clk_flush(), // input
// .flush_clk(), // output
.clk_flush (clk_flush), // input
.flush_clk (flush_clk), // output
.fifo_or_full() // output
);
......
This diff is collapsed.
parameter FPGA_VERSION = 32'h03930050;
\ No newline at end of file
parameter FPGA_VERSION = 32'h03930054; // 'old' sensor/converter with debug
// parameter FPGA_VERSION = 32'h03930053; // trying if(reset ) reg <- 'bx
\ No newline at end of file
......@@ -482,7 +482,7 @@
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 5, // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
//`endif
// other parameters for histogram_saxi module
......
......@@ -188,7 +188,7 @@ module sensor_channel#(
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 5, // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif
// sens_parallel12 other parameters
......
......@@ -23,7 +23,7 @@
module sensor_fifo #(
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, // 4-bit address
parameter SENSOR_FIFO_DELAY = 5 // 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
parameter [3:0] SENSOR_FIFO_DELAY = 5 // 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
)(
// input rst,
input iclk, // input -synchronous clock
......
......@@ -188,7 +188,7 @@ module sensors393 #(
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 5, // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif
// other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
......
......@@ -4,10 +4,12 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI
// `define HISPI
`define USE_PCLK2X
`define USE_XCLK2X
`define DEBUG_RING 1
// `define USE_PCLK2X
// `define DEBUG_RING 1
`define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
`ifdef IVERILOG
......
......@@ -49,12 +49,13 @@ module clocks393#(
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
parameter BUF_CLK1X_XCLK = "BUFG",
`ifdef USE_XCLK2X
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
parameter BUF_CLK1X_XCLK2X = "BUFG",
`endif
parameter CLKIN_PERIOD_SYNC = 20, // 50MHz
parameter DIVCLK_DIVIDE_SYNC = 1,
parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz
......@@ -106,7 +107,9 @@ module clocks393#(
output pclk2x, // global clock for sennors, 2x frequency (now 192MHz)
`endif
output xclk, // global clock for compressor (now 100MHz)
`ifdef USE_XCLK2X
output xclk2x, // global clock for compressor, 2x frequency (now 200MHz)
`endif
output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
output time_ref, // non-global, just RTC (currently just mclk/8 = 25 MHz)
input [1:0] extra_status, // just extra two status bits from the top module
......@@ -232,16 +235,24 @@ module clocks393#(
.DIVCLK_DIVIDE (DIVCLK_DIVIDE_XCLK),
.CLKFBOUT_MULT (CLKFBOUT_MULT_XCLK),
.CLKOUT_DIV_CLK1X (CLKOUT_DIV_XCLK),
.BUF_CLK1X (BUF_CLK1X_XCLK),
`ifdef USE_XCLK2X
.CLKOUT_DIV_CLK2X (CLKOUT_DIV_XCLK2X),
.PHASE_CLK2X (PHASE_CLK2X_XCLK),
.BUF_CLK1X (BUF_CLK1X_XCLK),
.BUF_CLK2X (BUF_CLK1X_XCLK2X)
`else
.BUF_CLK2X ("NONE")
`endif
) dual_clock_xclk_i (
.rst (async_rst || reset_clk[2]), // input
.clk_in (aclk), // input
.pwrdwn (pwrdwn_clk[2]), // input
.clk1x (xclk), // output
`ifdef USE_XCLK2X
.clk2x (xclk2x), // output
`else
.clk2x (), // output
`endif
.locked (locked[2]) // output
);
......
......@@ -198,11 +198,12 @@ module x393 #(
wire pclk; // global clock, sensor pixel rate (96 MHz)
`ifdef USE_PCLK2X
wire pclk2x; // global clock, sensor double pixel rate (192 MHz)
`endif
`endif
// compressor pixel rate can be adjusted independently
wire xclk; // global clock, compressor pixel rate (100 MHz)?
`ifdef USE_XCLK2X
wire xclk2x; // global clock, compressor double pixel rate (200 MHz)
`endif
wire camsync_clk; // global clock used for external synchronization. 96MHz in x353.
// Make it independent of pixel, compressor and mclk so it can be frozen
wire logger_clk; // global clock for the event logger. Use 100 MHz, shared with camsync_clk
......@@ -1814,9 +1815,10 @@ assign axi_grst = axi_rst_pre;
`endif
) compressor393_i (
// .rst (axi_rst), // input
.xclk (xclk), // input
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // input
`endif
.mclk (mclk), // input
.mrst (mrst), // input
.xrst (xrst), // input
......@@ -2178,10 +2180,12 @@ assign axi_grst = axi_rst_pre;
.DIVCLK_DIVIDE_XCLK (DIVCLK_DIVIDE_XCLK),
.CLKFBOUT_MULT_XCLK (CLKFBOUT_MULT_XCLK),
.CLKOUT_DIV_XCLK (CLKOUT_DIV_XCLK),
.BUF_CLK1X_XCLK (BUF_CLK1X_XCLK),
`ifdef USE_XCLK2X
.CLKOUT_DIV_XCLK2X (CLKOUT_DIV_XCLK2X),
.PHASE_CLK2X_XCLK (PHASE_CLK2X_XCLK),
.BUF_CLK1X_XCLK (BUF_CLK1X_XCLK),
.BUF_CLK1X_XCLK2X (BUF_CLK1X_XCLK2X),
`endif
.CLKIN_PERIOD_SYNC (CLKIN_PERIOD_SYNC),
.DIVCLK_DIVIDE_SYNC (DIVCLK_DIVIDE_SYNC),
.CLKFBOUT_MULT_SYNC (CLKFBOUT_MULT_SYNC),
......@@ -2228,7 +2232,9 @@ assign axi_grst = axi_rst_pre;
.pclk2x (pclk2x), // output
`endif
.xclk (xclk), // output
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // output
`endif
.sync_clk (camsync_clk), // output
.time_ref (time_ref), // output
.extra_status ({1'b0,idelay_ctrl_rdy}), // input[1:0]
......
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