Commit 62cf2722 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

simulating, starting hardware testing

parent 802a2f02

.project

+8 −8
Original line number Diff line number Diff line
@@ -62,42 +62,42 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151009231737365.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151028193641990.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151009231737365.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151028193641990.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151009231737365.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151028193641990.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151009231737365.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151028193641990.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151009231737365.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151028193641990.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151009231737365.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151028193641990.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151009231255456.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151028193155597.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151009231737365.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151028193641990.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

.settings/com.elphel.vdt.VivadoSynthesis.prefs

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000 
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->

VivadoSynthesis_115_flatten_hierarchy=none

VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->

VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->

VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_nox2_timing.xdc<-@\#\#@->

VivadoSynthesis_122_SkipSnapshotSynth=true

VivadoSynthesis_123_ResetProject=true

VivadoSynthesis_123_SkipSnapshotSynth=true

compressor_jp/bit_stuffer_27_32.v

+13 −6
Original line number Diff line number Diff line
@@ -76,7 +76,8 @@ module bit_stuffer_27_32#( 
        



        // barrel shifter stage 1 (0/8/16/24)

        if (ds) case (early_length[4:3])

        if (rst) data1 <= 'bx;

        else if (ds) case (early_length[4:3])

            2'h0: data1 <= {      din, 24'b0};

            2'h1: data1 <= { 8'b0,din, 16'b0};

            2'h2: data1 <= {16'b0,din,  8'b0};
@@ -84,13 +85,16 @@ module bit_stuffer_27_32#( 
        endcase

    

        // barrel shifter stage 2 (0/2/4/6)

        if (stage[0]) case (dlen1[2:1])

        if (rst) data2 <= 'bx;

        else if (stage[0]) case (dlen1[2:1])

            2'h0: data2 <= {      data1, 6'b0};

            2'h1: data2 <= { 2'b0,data1, 4'b0};

            2'h2: data2 <= { 4'b0,data1, 2'b0};

            2'h3: data2 <= { 6'b0,data1      };

        endcase

        if (stage[0]) case (dlen1[4:0])

        

        if (rst) dmask2_rom <= 'bx;

        else if (stage[0]) case (dlen1[4:0])

            5'h00: dmask2_rom <= 32'hffffffff;

            5'h01: dmask2_rom <= 32'h7fffffff;

            5'h02: dmask2_rom <= 32'h3fffffff;
@@ -125,7 +129,8 @@ module bit_stuffer_27_32#( 
            5'h1f: dmask2_rom <= 32'h00000001;

        endcase

        // barrel shifter stage 3 (0/1), combined with output/hold register

        if (ds_stage[1]) begin

        if (rst) data3 <= 'bx;

        else if (ds_stage[1]) begin

            data3[DATA3_LEN-1 -: 32] <= (~dmask2_rom & (dlen2[5] ? {data3[DATA3_LEN-1-32 : 0],6'b0}: data3[DATA3_LEN-1 -: 32])) |

                               ( dmask2_rom & (dlen2[0] ? {1'b0,data2[DATA2_LEN-1 -: 31]} : data2[DATA2_LEN-1 -: 32]));

            data3[DATA3_LEN-1-32: 0] <= dlen2[0] ? data2[DATA2_LEN-31-1 : 0] : {data2[DATA2_LEN-32-1 : 0], 1'b0};
@@ -135,7 +140,9 @@ module bit_stuffer_27_32#( 
//        dv <= (ds_stage[1] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));

//        dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));

        dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32]));



// no difference in number of cells

//        if      (rst )                bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes

//        else if (ds_stage[1])         bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes

        if  (rst || ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes

        else if (flush_stage[1])      bytes_out <= pre_bits_out_w[4:3];

compressor_jp/bit_stuffer_escape.v

+7 −4
Original line number Diff line number Diff line
@@ -215,7 +215,7 @@ module bit_stuffer_escape( 
            case (sel0_w)

                2'b00 :   d_out[ 7: 0] <= fifo_out_barrel_w[ 7: 0];

                2'b01 :   d_out[ 7: 0] <= fifo_out_barrel_w[15: 8]; 

                2'b01 :   d_out[ 7: 0] <= fifo_out_barrel_w[23:16]; 

                2'b10 :   d_out[ 7: 0] <= fifo_out_barrel_w[23:16]; 

                2'b11 :   d_out[ 7: 0] <= 8'b0;

                default : d_out[ 7: 0] <= 'bx;

            endcase
@@ -228,11 +228,14 @@ module bit_stuffer_escape( 
        if (rst) flush_pend[1] <= 0;

        else     flush_pend[1] <= flush_pend[0] &&!flush_pend[1] && !rdy_w;

        

        flush_pend[2] <= flush_pend[1];

        if (rst) flush_pend[2] <= 0;

        else     flush_pend[2] <= flush_pend[1];

        

        flush_out <= flush_pend[2]; 

        if (rst) flush_out <=  0;

        else     flush_out <= flush_pend[2]; 

        

        if ( rdy_w || flush_pend[1]) casex(bytes_rdy_w[3:0])

        if (rst) bytes_out <= 'bx;

        else if ( rdy_w || flush_pend[1]) casex(bytes_rdy_w[3:0])

            4'b10xx :  bytes_out <= 1;

            4'b110x :  bytes_out <= 2;

            4'b1110 :  bytes_out <= 3;

compressor_jp/bit_stuffer_metadata.v

+2 −3
Original line number Diff line number Diff line
@@ -119,9 +119,8 @@ module bit_stuffer_metadata( 
        data_out_valid <= stb || trailer;

        

        

        if      (xrst)        running <= 0;

        if      (xrst || trailer) running <= 0;

        else if (stb_start)       running <= 1;

        else if (trailer)     running <= 0;

        

        done <= trailer_done;

        // re-clock abort, extract leading edge