Commit 59774283 authored by Andrey Filippov's avatar Andrey Filippov

processing frame syn before previous frame is finished (fast forward, skipping memory transactions)

parent 2b1975c3
......@@ -67,7 +67,7 @@
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
parameter WOI_WIDTH= 64,
parameter QUADRANTS_PXD_HACT_VACT = 6'h01 // 2 bits each: data-0, hact - 1, vact - 2
parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
parameter SENSOR_PRIORITY = 0 // 1000 // 1000 - works OK, testing recover from too early Frame Sync // 5 usec for 200MHz mclk
\ No newline at end of file
......@@ -300,6 +300,7 @@ module mcntrl393 #(
output [3:0] sens_buf_rd, // (), // input
input [255:0] sens_buf_dout, // (), // output[63:0]
input [3:0] sens_page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer
output [3:0] sens_xfer_skipped, // single mclk pulse on each bit indicating one skipped (not written) block.
// compressor subsystem interface
// Buffer interfaces, combined for 4 channels
output [3:0] cmprs_xfer_reset_page_rd, // from mcntrl_tiled_rw (
......@@ -1098,6 +1099,7 @@ module mcntrl393 #(
.xfer_done (sens_seq_done[i]), // input : page sequence over
.xfer_page_rst_wr (sens_rpage_set[i]), // output @ posedge mclk
.xfer_page_rst_rd (), // output @ negedge mclk
.xfer_skipped (sens_xfer_skipped[i]), // output reg
.cmd_wrmem () // output
);
......@@ -1237,6 +1239,7 @@ module mcntrl393 #(
.xfer_done (seq_done1), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page1_wr), // output
.xfer_page_rst_rd (xfer_reset_page1_rd), // output
.xfer_skipped (), // output reg
.cmd_wrmem (cmd_wrmem_chn1) // output
);
......@@ -1300,6 +1303,7 @@ module mcntrl393 #(
.xfer_done (seq_done3), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page3_wr), // output
.xfer_page_rst_rd (xfer_reset_page3_rd), // output
.xfer_skipped (), // output reg
.cmd_wrmem () // output
);
......
This diff is collapsed.
......@@ -413,6 +413,7 @@ module x393 #(
wire [3:0] sens_buf_rd; // (), // input
wire [255:0] sens_buf_dout; // (), // output[63:0]
wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer
wire [3:0] sens_xfer_skipped; // single mclk pulse on every skipped (not written) block to record error statistics
wire trigger_mode; // (), // input
wire [3:0] trig_in; // input[3:0]
......@@ -1131,7 +1132,7 @@ assign axi_grst = axi_rst_pre;
.sens_buf_rd (sens_buf_rd), // output[3:0]
.sens_buf_dout (sens_buf_dout), // input[255:0]
.sens_page_written (sens_page_written), // input [3:0] single mclk pulse: buffer page (full or partial) is written to the memory buffer
.sens_xfer_skipped (sens_xfer_skipped), // output reg
// compressor interface
.cmprs_xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // output[3:0]
.cmprs_buf_wpage_nxt (cmprs_buf_wpage_nxt), // output[3:0]
......
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Tue Oct 20 00:35:32 2015
[*] Wed Oct 21 03:45:23 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151019173150201.fst"
[dumpfile_mtime] "Tue Oct 20 00:11:59 2015"
[dumpfile_size] 246875731
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151020195643294.fst"
[dumpfile_mtime] "Wed Oct 21 02:34:57 2015"
[dumpfile_size] 269754303
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 0
[timestart] 93798600
[size] 1823 1180
[pos] 1917 0
*-25.380077 116922388 99347388 99907388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-16.380077 94047388 178682388 184032388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
......@@ -49,11 +49,11 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 512
[signals_width] 347
[sst_width] 280
[signals_width] 262
[sst_expanded] 1
[sst_vpaned_height] 670
@821
@820
x393_testbench03.TEST_TITLE[639:0]
@800200
-x393_top
......@@ -853,7 +853,7 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
@1401200
-group_end
@c00022
@800022
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
......@@ -865,7 +865,7 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
(6)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(7)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(8)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
@1401200
@1001200
-group_end
@c00022
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
......@@ -883,7 +883,26 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
-group_end
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.calc_valid
@29
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.skip_run
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_delayed
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_mod
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.busy_r
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pre_want
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.want_r
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending
@800028
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending_long[1:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending_long[1:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending_long[1:0]
@1001200
-group_end
@200
-
@1000200
......
......@@ -113,8 +113,8 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
parameter TRIG_PERIOD = 6000 ;
`ifdef HISPI
parameter HBLANK= 90; // 12; /// 52; //*********************
parameter BLANK_ROWS_BEFORE= 9; // 3; //8; ///2+2 - a little faster than compressor
parameter HBLANK= 52; // 90; // 12; /// 52; //*********************
parameter BLANK_ROWS_BEFORE= 3; // 9; // 3; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 1; //8;
`else
......@@ -2648,6 +2648,8 @@ task setup_sensor_channel;
// Enable arbitration of sensor-to-memory controller
enable_memcntrl_en_dis(4'h8 + {2'b0,num_sensor}, 1);
// write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,ENABLED_CHANNELS});
// Set sesnor channel priority - 5 usec bonus to compressor/other channels
configure_channel_priority(4'h8 + {2'b0,num_sensor}, SENSOR_PRIORITY); // lowest priority channel 1
compressor_run (num_sensor, 0); // reset compressor
......
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