Commit 4ca48f7b authored by Andrey Filippov's avatar Andrey Filippov
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Made several modifications to fix all timing violations to run compressor... 

Made several modifications to fix all timing violations to run compressor @250MHz - 1.0 Gigapixel/sec in JP4 mode
parent ba35eb7a

.project

+8 −8
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@@ -62,42 +62,42 @@ 
		<link>

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compressor_jp/bit_stuffer_escape.v

+2 −1
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@@ -185,7 +185,8 @@ module bit_stuffer_escape( 
        default: fifo_re_mask_w <= 'bx; // impossible num_zeros_w 

    endcase



    assign fifo_re = flush_pend[2]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left

//    assign fifo_re = flush_pend[2]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left

    assign fifo_re = fifo_nempty & (({4{rdy_w}} & fifo_re_mask_w) | {4{flush_pend[2]}});// when flushing read whatever is left



    always @(posedge xclk) begin

        if (rst || flush_pend[2])   cry_ff <= 0;

compressor_jp/csconvert18a.v

+5 −2
Original line number Diff line number Diff line
@@ -584,9 +584,12 @@ always @ (posedge CLK) begin 
  if (~ywe_r) use_cr <= ~(bayer_phase[1] ^ odd_line);

end

assign      cbcrmult2 = use_cr?m_cr:m_cb;  // maybe will need a register? (use_cr will still be good as it is valid early)

assign      cbcrmulto=cbcrmult1*cbcrmult2;

//assign      cbcrmulto = cbcrmult1*cbcrmult2;

assign      cbcrmulto = cbcrmult1*cbcrmult2_r;

reg [9:0] cbcrmult2_r; // will be one cycle later than cbcrmult2, but is still OK. Will be absorbed into the DSP block

// will preserve extra bit, but do not need to add half of the truncated MSB - on average there will be no shift after subtraction

always @ (posedge CLK) begin

  cbcrmult2_r <= cbcrmult2;

  cbcrmultr[10:0] <= cbcrmulto[17:7];

  cbcr[10:0] <= sub_y? (cbcr[10:0]-cbcrmultr[10:0]+ 1'b1):cbcrmultr[10:0];

end

compressor_jp/jp_channel.v

+15 −1
Original line number Diff line number Diff line
@@ -907,7 +907,7 @@ module jp_channel#( 
    end

    

    

    

`ifdef USE_OLD_XDCT393    

    

    xdct393 xdct393_i (

        .clk                (xclk),                // input
@@ -920,6 +920,20 @@ module jp_channel#( 
        .dv                 (),  // not used: output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)

        .d_out              (dct_out)              // output[12:0] 

    );

`else

    xdct393r xdct393_i (

        .clk                (xclk),                // input

        .en                 (frame_en),            // input  if zero will reset transpose memory page numbers

        .start              (dct_start),           // input  single-cycle start pulse that goes with the first pixel data. Other 63 should follow

        .xin                (yc_nodc),             // input[9:0] 

        .last_in            (dct_last_in),         // output reg  output high during input of the last of 64 pixels in a 8x8 block //

        .pre_first_out      (dct_pre_first_out),   // outpu 1 cycle ahead of the first output in a 64 block

///        .dv                 (dct_dv),           // output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)

        .dv                 (),  // not used: output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)

        .d_out              (dct_out)              // output[12:0] 

    );

`endif    

    

    wire          quant_start;

    dly_16 #(.WIDTH(1)) i_quant_start (.clk(xclk),.rst(1'b0), .dly(4'd0), .din(dct_pre_first_out), .dout(quant_start));    // dly=0+1

fpga_version.vh

+4 −1
Original line number Diff line number Diff line 
    parameter FPGA_VERSION =          32'h03930059; // 'new' (no pclk2x, no xclk2x  clocks) sensor/converter w/o debug - ???

      parameter FPGA_VERSION =          32'h0393005c; // 250MHz ???

//    parameter FPGA_VERSION =          32'h0393005b; // 250MHz Not tested, timing violation in bit_stuffer_escape: xclk -0.808 -142.047 515

//    parameter FPGA_VERSION =          32'h0393005a; // Trying xclk = 250MHz - timing viloations in xdct393, but particular hardware works

//    parameter FPGA_VERSION =          32'h03930059; // 'new' (no pclk2x, no xclk2x  clocks) sensor/converter w/o debug - OK

//    parameter FPGA_VERSION =          32'h03930058; // 'new' (no pclk2x, no xclk2x  clocks) sensor/converter w/o debug - broken end of frame

//    parameter FPGA_VERSION =          32'h03930057; // 'new' (no pclk2x, yes xclk2x  clocks) sensor/converter w/o debug - OK

//    parameter FPGA_VERSION =          32'h03930056; // 'new' (no 2x clocks) sensor/converter w/o debug - broken