Commit 759ea200 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Testing hardware, added configurable lane mapping

parent 81da483f

.project

+8 −8
Original line number Diff line number Diff line
@@ -62,42 +62,42 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151110124625814.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151111121710210.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151110124625814.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151111121710210.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151110124625814.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151111121710210.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151110124625814.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151111121710210.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151110124625814.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151111121710210.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151110124625814.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151111121710210.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151110124146463.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151111121710210.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151110124625814.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151111121710210.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

fpga_version.vh

+4 −1
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@@ -31,7 +31,10 @@ 
 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 *******************************************************************************/

    parameter FPGA_VERSION =          32'h0393006c; // will try debug for HiSPi.  xclk violated by -0.030, slices 15062 (76.65%)

    parameter FPGA_VERSION =          32'h0393006e; // Trying lane switch again after bug fix, failing 1 in  ddr3_mclk -> ddr3_clk_div by  -0.023

//    parameter FPGA_VERSION =          32'h0393006d; // -1 with lane switch - does not work

//    parameter FPGA_VERSION =          32'h0393006d; // Reversing pixels/lanes order xclk violated -0.154

//    parameter FPGA_VERSION =          32'h0393006c; // will try debug for HiSPi.  xclk violated by -0.030, slices 15062 (76.65%)

//    parameter FPGA_VERSION =          32'h0393006b; // Correcting sensor external clock generation - was wrong division. xclk violated by 0.095 ns

//    parameter FPGA_VERSION =          32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization x40..x60

//    parameter FPGA_VERSION =          32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization

py393/dbg/x393_mcntrl.pickle

+65258 −65729

File changed.

Preview size limit exceeded, changes collapsed.

py393/x393_jpeg.py

+38 −5
Original line number Diff line number Diff line
@@ -819,24 +819,51 @@ class X393Jpeg(object): 
ff d9

"""        

"""

#should be no MSB first (0x31c68400)



cd /usr/local/verilog/; test_mcntrl.py @hargs

measure_all "*DI"

setup_all_sensors True None 0xf

#compressor_control  all  None  None  None None None  3

set_sensor_hispi_lanes 0 1 2 3 0

compressor_control  all  None  None  None None None  2

program_gamma all 0 0.57 0.04

write_sensor_i2c  0 1 0 0x030600b4

print_sensor_i2c 0 0x306 0xff 0x10 0

print_sensor_i2c 0 0x303a 0xff 0x10 0

print_sensor_i2c 0 0x301a 0xff 0x10 0

print_sensor_i2c 0 0x31c6 0xff 0x10 0

write_sensor_i2c  0 1 0 0x31c68402

print_sensor_i2c 0 0x31c6 0xff 0x10 0

write_sensor_i2c  0 1 0 0x301a001c

write_sensor_i2c  0 1 0 0x31c68400

print_sensor_i2c 0 0x31c6 0xff 0x10 0

print_sensor_i2c 0 0x306e 0xff 0x10 0

write_sensor_i2c  0 1 0 0x306e9280



#test pattern - 100% color bars

write_sensor_i2c  0 1 0 0x30700003

#test pattern - fadiong color bars

write_sensor_i2c  0 1 0 0x30700002

#test pattern - fading color bars

write_sensor_i2c  0 1 0 0x30700003

print_sensor_i2c 0 0x3070 0xff 0x10 0



#Exposure 0x800 lines

write_sensor_i2c  0 1 0 0x30120800



#default gain = 0xa, set red and blue (outdoors)

write_sensor_i2c  0 1 0 0x3028000a

write_sensor_i2c  0 1 0 0x302c000d

write_sensor_i2c  0 1 0 0x302e0010



#default gain = 0xa, set red and blue (indoors)

write_sensor_i2c  0 1 0 0x3028000a

write_sensor_i2c  0 1 0 0x302c000b

write_sensor_i2c  0 1 0 0x302e0010



write_sensor_i2c  0 1 0 0x301a001c

print_sensor_i2c 0 0x31c6 0xff 0x10 0





compressor_control 0 2

jpeg_write  "img.jpeg" 0
@@ -1046,6 +1073,12 @@ root@elphel393:/sys/devices/amba.0/f8007100.ps7-xadc# cat /sys/devices/amba.0/f8 


write_sensor_i2c  0 1 0 0xff200000

print_sensor_i2c 0 

#set JP46

compressor_control  all  None  None  None  2

#JP4

compressor_control  all  None  None  None  5

#JPEG

compressor_control  all  None  None  None  0

py393/x393_sens_cmprs.py

+2 −1
Original line number Diff line number Diff line
@@ -75,7 +75,8 @@ SENSOR_INTERFACES={SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface" 
                   SENSOR_INTERFACE_HISPI:    {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}}



SENSOR_DEFAULTS= {SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100},

                   SENSOR_INTERFACE_HISPI:   {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}

#                   SENSOR_INTERFACE_HISPI:   {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}

                   SENSOR_INTERFACE_HISPI:   {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}



class X393SensCmprs(object):

    DRY_MODE =           True # True