Commit ea56e79d authored by Andrey Filippov's avatar Andrey Filippov

Implemented global switching between old/new histograms

parent 12f27fa3
This diff is collapsed.
......@@ -283,7 +283,9 @@ module sensors393 #(
// input rst,
// will generate it here
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
`ifdef USE_PCLK2X
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
`endif
input ref_clk, // IODELAY calibration
input dly_rst,
input mrst, // @posedge mclk, sync reset
......@@ -592,7 +594,9 @@ module sensors393 #(
`endif
) sensor_channel_i (
.pclk (pclk), // input
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // input
`endif
.mrst (mrst), // input
.prst (prst), // input
......
......@@ -4,6 +4,8 @@
`define PRELOAD_BRAMS
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI
// `define USE_PCLK2X
// `define DEBUG_RING 1
`define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
......
......@@ -40,11 +40,12 @@ module clocks393#(
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter BUF_CLK1X_PCLK = "BUFG",
`ifdef USE_PCLK2X
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
`endif
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
......@@ -101,7 +102,9 @@ module clocks393#(
output aclk, // global clock 50 MHz (used for maxi0)
output hclk, // global clock 150MHz (used for afi*, saxi*)
output pclk, // global clock for sensors (now 96MHz), based on external clock generator
`ifdef USE_PCLK2X
output pclk2x, // global clock for sennors, 2x frequency (now 192MHz)
`endif
output xclk, // global clock for compressor (now 100MHz)
output xclk2x, // global clock for compressor, 2x frequency (now 200MHz)
output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
......@@ -203,16 +206,24 @@ module clocks393#(
.DIVCLK_DIVIDE (DIVCLK_DIVIDE_PCLK),
.CLKFBOUT_MULT (CLKFBOUT_MULT_PCLK),
.CLKOUT_DIV_CLK1X (CLKOUT_DIV_PCLK),
.CLKOUT_DIV_CLK2X (CLKOUT_DIV_PCLK2X),
.BUF_CLK1X (BUF_CLK1X_PCLK)
`ifdef USE_PCLK2X
,.CLKOUT_DIV_CLK2X (CLKOUT_DIV_PCLK2X),
.PHASE_CLK2X (PHASE_CLK2X_PCLK),
.BUF_CLK1X (BUF_CLK1X_PCLK),
.BUF_CLK2X (BUF_CLK1X_PCLK2X)
`else
,.BUF_CLK2X ("NONE")
`endif
) dual_clock_pclk_i (
.rst (async_rst || reset_clk[1]), // input
.clk_in (ffclk0), // input
.pwrdwn (pwrdwn_clk[1]), // input
.clk1x (pclk), // output
`ifdef USE_PCLK2X
.clk2x (pclk2x), // output
`else
.clk2x (), // output not connected
`endif
.locked (locked[1]) // output
);
......
......@@ -196,8 +196,9 @@ module x393 #(
//TODO: Create missing clocks
wire pclk; // global clock, sensor pixel rate (96 MHz)
`ifdef USE_PCLK2X
wire pclk2x; // global clock, sensor double pixel rate (192 MHz)
`endif
// compressor pixel rate can be adjusted independently
wire xclk; // global clock, compressor pixel rate (100 MHz)?
wire xclk2x; // global clock, compressor double pixel rate (200 MHz)
......@@ -413,6 +414,7 @@ module x393 #(
wire [3:0] sens_buf_rd; // (), // input
wire [255:0] sens_buf_dout; // (), // output[63:0]
wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer
// TODO: Add counter(s) to count sens_xfer_skipped pulses
wire [3:0] sens_xfer_skipped; // single mclk pulse on every skipped (not written) block to record error statistics
wire trigger_mode; // (), // input
wire [3:0] trig_in; // input[3:0]
......@@ -1597,7 +1599,9 @@ assign axi_grst = axi_rst_pre;
) sensors393_i (
// .rst (axi_rst), // input
.pclk (pclk), // input
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // input
`endif
.ref_clk (ref_clk), // input
.dly_rst (idelay_ctrl_reset), // input
.mrst (mrst), // input
......@@ -2164,10 +2168,12 @@ assign axi_grst = axi_rst_pre;
.DIVCLK_DIVIDE_PCLK (DIVCLK_DIVIDE_PCLK),
.CLKFBOUT_MULT_PCLK (CLKFBOUT_MULT_PCLK),
.CLKOUT_DIV_PCLK (CLKOUT_DIV_PCLK),
.BUF_CLK1X_PCLK (BUF_CLK1X_PCLK),
`ifdef USE_PCLK2X
.CLKOUT_DIV_PCLK2X (CLKOUT_DIV_PCLK2X),
.PHASE_CLK2X_PCLK (PHASE_CLK2X_PCLK),
.BUF_CLK1X_PCLK (BUF_CLK1X_PCLK),
.BUF_CLK1X_PCLK2X (BUF_CLK1X_PCLK2X),
`endif
.CLKIN_PERIOD_XCLK (CLKIN_PERIOD_XCLK),
.DIVCLK_DIVIDE_XCLK (DIVCLK_DIVIDE_XCLK),
.CLKFBOUT_MULT_XCLK (CLKFBOUT_MULT_XCLK),
......@@ -2218,7 +2224,9 @@ assign axi_grst = axi_rst_pre;
.aclk (axi_aclk), // output
.hclk (hclk), // output
.pclk (pclk), // output
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // output
`endif
.xclk (xclk), // output
.xclk2x (xclk2x), // output
.sync_clk (camsync_clk), // output
......
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